An optical proximity correction method and a computer-readable storage medium

Abstract

The present invention provides an optical proximity correction method and a computer-readable storage medium, which are applied to the field of semiconductor technology. In the present invention, after performing the first optical proximity correction on all the main patterns in the original layout to obtain the first corrected layout, at least one main pattern with stitching defects can be screened out from the first corrected layout, and the screened main pattern is re-performed optical proximity correction to obtain the second corrected pattern, that is, only a part of the main patterns in the original layout are re-performed optical proximity correction, which can reduce the number of optical proximity correction iterations and improve the efficiency of optical proximity correction; specifically, the main patterns can be screened by the way of whether the correction methods of the main patterns in the relevant layout blocks are the same, and then by re-performing the optical proximity correction, the behaviors and changes of the screened main patterns in different layout blocks are adjusted to be unified, so as to achieve the purpose of reducing the edge placement error (EPE).

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an optical proximity correction method and a computer-readable storage medium. Background Art

[0002] With the development of the semiconductor industry, people's requirements for the performance and energy consumption of chips are becoming increasingly stringent. To obtain chips with smaller areas, higher performance, and lower energy consumption, it is necessary to further reduce the size of each pattern on the chip and the spacing between each pattern. The reduction of the spacing will cause the design distance between some patterns on the layout to be less than the light wavelength. Therefore, it is necessary to correct the layout before it is printed on the mask plate to prevent the occurrence of the optical proximity effect (OPE) during the lithography process, and to avoid pattern distortion caused by the inconsistency between the patterns printed on the chip and the design. The technology for correcting the layout to avoid the optical proximity effect is the optical proximity correction (OPC) technology.

[0003] Currently, the computing power of existing EDA software and computer server clusters is not sufficient to support the one-time processing of the entire chip layout. Generally, the complete layout needs to be cut into micron-scale patches, processed separately, and finally the results of each processed patch layout are integrated (stitched) to obtain the complete layout. However, it is possible that different pattern regions of a polygon main pattern in the layout are cut into different patches. At this time, the polygon main pattern can be defined as a global polygon. Since the patches are processed distributively, it is impossible to fully and uniformly consider the behavior and changes of the global polygon in different patches, which will inevitably cause problems with poor pattern consistency at the junction of adjacent patches. Summary of the Invention

[0004] The purpose of the present invention is to provide an optical proximity correction method and a computer-readable storage medium to reduce the edge placement error (EPE), increase the process window, and improve the product yield.

[0005] In a first aspect, to solve the above technical problems, the present invention provides an optical proximity correction method, including: providing an initial layout, where the initial layout includes a plurality of main patterns.

[0006] The initial layout is segmented to obtain a plurality of layout patches, where at least one of the main patterns is segmented into a plurality of sub-patterns, and different sub-patterns are located in different layout patches.

[0007] Perform first optical proximity correction on the patterns within the several divided layout blocks respectively, and splice the corrected multiple layout blocks to obtain the first corrected layout of the initial layout.

[0008] Determine at least one first corrected pattern with splicing defects from the first corrected layout, and form a pattern set with the main pattern corresponding to the determined first corrected pattern and other main patterns located around the main pattern.

[0009] Take a pattern set as a new layout block, and perform second optical proximity correction on the main pattern corresponding to the first corrected pattern in the pattern set to obtain the second corrected pattern of the main pattern.

[0010] Remove the first corrected pattern corresponding to the main pattern determined in the first corrected layout, and backfill the second corrected pattern corresponding to the main pattern to the removed position on the first corrected layout to obtain the second corrected layout.

[0011] In some alternative examples, before dividing the initial layout, corresponding auxiliary patterns may be added to the intervals between adjacent main patterns in the initial layout according to a preset auxiliary pattern addition rule.

[0012] In some alternative examples, after obtaining the second corrected layout, it may further include:

[0013] Perform pattern inspection on the second corrected layout to determine whether the second corrected layout lacks the first corrected pattern or the second corrected pattern corresponding to the main pattern. If so, return to execute the step of removing the first corrected pattern corresponding to the main pattern determined in the first corrected layout and backfilling the second corrected pattern corresponding to the main pattern to the removed position on the first corrected layout to obtain the second corrected layout.

[0014] In some alternative examples, the pattern inspection may include: performing an exclusive OR operation on the second corrected layout and the initial layout.

[0015] In some alternative examples, at least part of a line edge of a main pattern divided into multiple sub-patterns may be located in different layout blocks.

[0016] In some alternative examples, the step of determining at least one first corrected pattern with splicing defects from the first corrected layout may include:

[0017] Determine whether the correction methods of the partial line segments of a line side of the main figure located in different layout sub-blocks in the relevant layout sub-blocks are the same. If they are different, then regard the main figure containing this line side as the main figure with stitching defects.

[0018] In some alternative examples, if the correction methods of the partial line segments of the main figure located in different layout sub-blocks in the relevant layout sub-blocks are the same, then perform an intersection operation on the first corrected figures of the sub-figures corresponding to the parts of this partial line segment in different layout sub-blocks.

[0019] In some alternative examples, the step of determining at least one first corrected figure with stitching defects from the first corrected layout may include:

[0020] Set at least one cut point on the partial line segments of the main figure located in different layout sub-blocks to cut the line segment into multiple sub-segments, and determine whether the correction methods of the sub-segments in the relevant layout sub-blocks are the same. If they are different, then regard the main figure containing this sub-segment as the main figure with stitching defects.

[0021] In some alternative examples, the correction method of the first optical proximity correction may include: performing an outward edge expansion process or an inward edge contraction process on the line edge of the main figure in a direction perpendicular to this line edge.

[0022] In a second aspect, the present invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus;

[0023] The memory is used to store a computer program;

[0024] The processor is used to implement the method steps of the optical proximity correction as described above when executing the program stored on the memory.

[0025] In a third aspect, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and the computer program implements the method steps of the optical proximity correction as described above when executed by a processor.

[0026] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0027] The present invention provides an optical proximity correction method, comprising: providing an initial layout, the initial layout including a plurality of main patterns, slicing the initial layout to obtain a plurality of layout blocks, wherein at least one of the main patterns is sliced into a plurality of sub-patterns, and different sub-patterns are located in different layout blocks, performing a first optical proximity correction on the patterns in the plurality of layout blocks respectively, and splicing the corrected plurality of layout blocks to obtain a first corrected layout of the initial layout, determining at least one first corrected pattern with a splicing defect from the first corrected layout, and forming a pattern set with the main pattern corresponding to the determined first corrected pattern and other main patterns located around the main pattern, taking the pattern set as a new layout block, and performing a second optical proximity correction on the main pattern corresponding to the first corrected pattern in the pattern set to obtain a second corrected pattern of the main pattern, removing the first corrected pattern corresponding to the main pattern determined in the first corrected layout, and backfilling the second corrected pattern corresponding to the main pattern to the removed position on the first corrected layout to obtain a second corrected layout.

[0028] In the present invention, after performing at least one optical proximity correction on all the main patterns in the original layout to obtain a first corrected layout, at least one main pattern with a splicing defect is screened out from the first corrected layout, and the screened main pattern is re-performed with optical proximity correction to obtain a second corrected pattern, that is, only part of the main patterns in the original layout are re-performed with optical proximity correction, such as the main patterns (global polygons) whose different graphic regions are sliced into different layout blocks. The unexpected effect is that the number of optical proximity correction iterations of the original layout can be reduced, that is, the efficiency of optical proximity correction is improved; specifically, the first corrected pattern corresponding to the screened main pattern in the first corrected layout can be replaced with the second corrected pattern, so as to combine the first corrected patterns of part of the main patterns and the second corrected patterns of at least one main pattern to form the final corrected layout of the original layout. The unexpected effect is that by using the way whether the correction methods of the main patterns in the relevant layout blocks are the same, it is determined whether the behaviors and changes of the main patterns, such as global polygons, in different layout blocks are unified, and by re-performing optical proximity correction, the behaviors and changes of the main patterns in different layout blocks are adjusted to be unified, thereby achieving the purpose of reducing the edge placement error EPE, increasing the process window, and improving the product yield. Description of the Drawings

[0029] The drawings are used to provide a further understanding of the present application, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application, but do not constitute a limitation to the present application. In the drawings:

[0030] Figure 1Schematic flowchart of an optical proximity correction method in an embodiment of the present invention.

[0031] Figure 2 An example diagram of an original layout in an embodiment of the present invention.

[0032] Figure 3 In an embodiment of the present invention Figure 2 An example diagram of a plurality of layout blocks obtained after splitting the original layout shown.

[0033] Figure 4 In an embodiment of the present invention Figure 3 An enlarged example diagram of a partial graph of the global polygon shown.

[0034] Figure 5 In an embodiment of the present invention Figure 4 An example diagram of a target layout corresponding to the partial graph of the global polygon shown.

[0035] Figure 6 In an embodiment of the present invention Figure 4 An example diagram of a first corrected graph after performing an optical proximity correction once on the partial graph of the global polygon shown according to the layout block where it is located.

[0036] Figure 7 In an embodiment of the present invention Figure 4 An example diagram of a first corrected graph after performing an optical proximity correction once on the partial graph of the global polygon shown according to another layout block where it is located.

[0037] Figure 8 In an embodiment of the present invention, the Figures 5 to 7 Example diagram of a graph obtained by superimposing the graphs shown.

[0038] Figure 9 In an embodiment of the present invention Figure 4 The partial graph of the global polygon shown performs Figure 1 An example diagram of a second corrected graph after performing the optical proximity correction method shown.

[0039] Wherein, the reference numerals are:

[0040] 100 - Original layout, 101 - Global polygon, 102 - Other main graphics, 10 / 10a~10c - Layout blocks, AA - Cutting line, 1011 - Sub - graphics, 101a - One - line side of the global polygon, 101b - Another - line side of the global polygon, S1 - Target layout of the local graphics of the global polygon, S2 / S3 - First - corrected graphics after one - time optical proximity correction of the local graphics of the global polygon according to different layout blocks, S4 - Second - corrected graphics after the second - time optical proximity correction of the local graphics of the global polygon.

[0041] In the attached drawings, the same components are denoted by the same reference numerals, and the drawings are not drawn to actual scale. Detailed implementation manners

[0042] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below in conjunction with the attached drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the attached drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present invention and to be able to fully convey the scope of the present invention to those skilled in the art.

[0043] The layout refers to mapping the circuit design circuit diagram or circuit description language to the physical description level, so that the designed circuit can be mapped onto the wafer for production. The layout is a graph containing physical information such as the device type, device size, relative position between devices, and connection relationship between each device of the integrated circuit. These graphs are composed of graphs located on different drawing layers. For example, the layout usually includes a via layer, a metal wire layer, an insulating layer, a contact layer, a packaging layer, etc. Among them, the metal wire layer (Metal Layer) is mainly used to realize the internal circuit connection of the chip. The metal wire is generally made of metal materials such as copper and aluminum. Therefore, the metal wire layer usually involves the problem of global polygons. The present invention needs to properly handle the global polygons during the optical proximity correction process so that the global polygons can be normally stitched (assembled) after distributed operation.

[0044] The existing optical proximity correction method divides the entire layout into multiple adjacent sub-blocks, and polygons belonging to the same sub-block perform OPC operations (optical proximity correction operations) on a separate central processing unit (CPU). After the OPC calculations for all sub-blocks are completed, the different sub-blocks are then merged into a complete layout. If, according to the existing technology, the corrected graphics after the OPC operations on at least a part of at least one edge of the global polygon in different layout sub-blocks are directly overlapped as the stitched complete layout, there will inevitably be a situation where the behavior and changes of the global polygon in different layout sub-blocks cannot be fully and uniformly considered. That is, the same part of the same edge of the global polygon will perform OPC operations with different correction rules or correction methods in different layout sub-blocks. Therefore, near the stitched layout sub-blocks, there often appear stitching (patching or integration) problems caused by inconsistencies, leading to difficult-to-solve weaknesses, such as a large edge placement error (EPE) and a small process window.

[0045] To solve the above problems, the present invention provides an optical proximity correction method and a computer-readable storage medium to reduce the edge placement error (EPE), increase the process window, and improve the product yield.

[0046] Please refer to Figure 1 , which shows a schematic flowchart of the optical proximity correction method in an embodiment of the present invention. As Figure 1 shown, the optical proximity correction method may at least include the following steps:

[0047] Step S101: Provide an initial layout, where the initial layout includes a plurality of main graphics.

[0048] Step S102: Divide the initial layout to obtain several layout sub-blocks, where at least one of the main graphics is divided into multiple sub-graphics, and different sub-graphics are located in different layout sub-blocks.

[0049] Step S103: Perform a first optical proximity correction on the graphics in the several layout sub-blocks respectively, and stitch the corrected multiple layout sub-blocks to obtain a first corrected layout of the initial layout.

[0050] Step S104: Determine at least one first corrected graphic with stitching defects from the first corrected layout, and form a graphic set with the main graphic corresponding to the determined first corrected graphic and other main graphics located around the main graphic.

[0051] Step S105: Take one of the graphic sets as a new layout block, and perform a second optical proximity correction on the main graphic corresponding to the first corrected graphic in the graphic set to obtain a second corrected graphic of the main graphic.

[0052] Step S106: Remove the first corrected graphic corresponding to the main graphic determined in the first corrected layout, and backfill the second corrected graphic corresponding to the main graphic to the position removed on the first corrected layout to obtain a second corrected layout.

[0053] In the present invention, at least one of the main graphics in the initial layout is a global polygon. When the global polygon is divided into different layout blocks, at least a part of at least one edge of the global polygon (which can also be called a partial edge) will be simultaneously divided into different layout blocks. Thus, when the first optical proximity correction operation (hereinafter simply referred to as the first OPC operation) is performed on each of the layout blocks separately on a CPU, at least a part of at least one edge of the global polygon (or a part of the edge) will perform different first OPC operations in different layout blocks (for example, an outward edge expansion process is performed in one layout block, while an inward edge contraction process is performed in another layout block). Therefore, after performing the first OPC operation, by judging whether the OPC operation methods of the same part of the same edge of the global polygon (the same part of the edge on a certain edge) in different layout blocks are consistent, the global polygons with stitching inconsistency problems can be screened out from the initial layout. Then, the global polygon and at least one other main graphic around it are taken as a new layout block (which can also be called a new layout block). That is, in the present invention, when performing the second OPC operation, the screened global polygon will not be divided in the layout. Therefore, the second corrected graphic obtained after performing the second OPC operation on the screened global polygon will surely not have the problem that the correction methods or correction rules of the second OPC operation for the same part of the same edge are inconsistent, thereby reducing the edge placement error EPE of the global polygon and increasing the process window.

[0054] A specific embodiment of the present invention will be described below with reference to the figures.

[0055] Please refer to Figure 2 , which shows an example diagram of the original layout in an embodiment of the present invention.

[0056] As shown in Figure 2As shown, in the above step S101, an original layout 100 may be provided first, wherein the original layout 100 includes a plurality of main graphics, and the plurality of main graphics include at least a global polygon 101 and other main graphics 102 surrounding the global polygon 101. The interval between the global polygon 101 and other main graphics 102 (the area corresponding to the spacing between the two) may be used as an area for adding auxiliary graphics. Then, in other optional examples, a preset auxiliary graphics adding rule may be further utilized, for example, based on the interval length between the global polygon 101 and other main graphics 102, or the interval length between adjacent other main graphics 102, at least one auxiliary graphic (not shown) is set in the interval, such as an auxiliary graphic in the shape of a grid bar, but not limited thereto.

[0057] Please refer to Figure 3 , which is shown in one embodiment of the present invention. Figure 2 An example diagram of several layout blocks obtained by segmenting the original layout shown in FIG. Figure 3 As shown, in the above step S102, a plurality of mutually spaced dividing lines AA may be sequentially set on the original layout 100 along the longitudinal direction and / or the transverse direction to divide the original layout 100 into at least two layout blocks 10. In one embodiment, the intervals between the plurality of dividing lines AA along the longitudinal direction and / or the transverse direction may be the same or different, so that the sizes or areas of the plurality of layout blocks 10 may be the same or different. For example, in the embodiment of the present invention, the original layout 100 is spaced along the longitudinal direction (e.g. Figure 3 The original layout 100 is divided into two parts (in the Y direction), and at least some of the layout blocks 10 have different areas or sizes, but the invention is not limited thereto. Under this setting, different graphic parts of the global polygon 101 in the original layout 100 are located in at least two different layout blocks 10, that is, in the process of dividing the original layout 100, the global polygon 101 therein will also be divided into multiple sub-graphics 1011, and different sub-graphics 1011 are located in different layout blocks 10.

[0058] Please refer to Figure 4 , which is shown in one embodiment of the present invention Figure 3 An enlarged example of a local figure of the global polygon shown in FIG. Figure 4 As shown, in the embodiment of the present invention, at least part of the main figure divided into a plurality of sub-figures 1011 is located in different layout blocks 10, for example, the same line edge of the global polygon 101 (for example Figure 4The line edge 101a extending in the horizontal X direction or another line edge 101b in it will be simultaneously cut into different layout blocks 10. For example, the line edge 101a of the global polygon 101 will be simultaneously cut into the layout block 10a and the layout block 10b, while its other line edge 101b will be simultaneously cut into the layout block 10b and the layout block 10c. It should be understood that if, in the optical proximity correction method proposed in the embodiment of the present invention, after providing the original layout 100 and before cutting the original layout 100, auxiliary graphics are added to the original layout 100, then during the process of cutting the original layout 100 in step S102, the added auxiliary graphics in it will also be cut into different layout blocks 10, which will not be elaborated here.

[0059] Please refer to Figures 5 to 8 , where Figure 5 is an example diagram of the target layout corresponding to the local graph of the global polygon shown in Figure 4 an embodiment of the present invention. Figure 6 is an example diagram of the first corrected graph after performing optical proximity correction once on the local graph of the global polygon shown in Figure 4 an embodiment of the present invention according to the layout block where it is located. Figure 7 is an example diagram of the first corrected graph after performing optical proximity correction once on the local graph of the global polygon shown in Figure 4 an embodiment of the present invention according to another layout block where it is located. Figure 8 is an example diagram of the graph obtained by superimposing the graphs shown in Figures 5 to 7 an embodiment of the present invention. As shown in Figures 5 to 8 , in the above step S103, the number of layout blocks can be obtained according to step S102, and the same number of servers or processes can be set, and then the first optical proximity correction is performed on the graphs included in each of the layout blocks 10 (for example, Figure 4 the different layout blocks identified by the reference numerals 10a to 10c in the drawing) based on the OPC model set in each server or process. For example, Figure 6 and Figure 7 . In an embodiment, the step of performing the first optical proximity correction on the graphs included in each of the layout blocks 10 is: cutting the line edge of the graph included in the layout block 10, for example, cutting the line edge 101a of the layout block 10a in Figure 4 into multiple sub-segments along the X direction, and then performing an outward edge expansion process or an inward edge contraction process on each sub-segment along the direction perpendicular to the line edge 101a (i.e., the Y direction), so as to obtain the sub-corrected graph after the first optical proximity correction of the graph in each layout block 10.

[0060] Then, the sub-correction patterns corresponding to the multiple layout blocks 10 after the first optical proximity correction are spliced. Specifically, along the cutting line AA set when cutting the original layout 100 in step S102, the sub-correction patterns corresponding to the multiple layout blocks 10 are spliced, so as to form the first corrected layout of the original layout 100 composed of the corrected patterns S2 and S3 shown in, for example Figure 8 ; where Figure 5 and Figure 8 in, S1 is Figure 4 the target pattern of the partial pattern of the global polygon shown, and S2 and S3 are Figure 4 after the partial pattern of the global polygon shown is cut into multiple sub-patterns 1011, the first corrected pattern of the partial pattern of the global polygon obtained by splicing the sub-correction patterns corresponding to the sub-patterns 1011 after the first optical proximity correction with different layout blocks 10. Under this setting, the optical proximity correction method in the prior art is only to stack the correction patterns corresponding to the multiple sub-patterns obtained by cutting the global polygon with different layout blocks after the first optical proximity correction, that is, Figure 6 the S2 shown and Figure 7 the S3 shown are stacked, and then the correction patterns of S2 and S3 are used for exposure and development respectively to form corresponding patterns on the wafer, while the embodiment of the present invention further needs to perform steps S104 to S106 on the correction patterns corresponding to S2 and S3.

[0061] It should be understood that Figure 6 and Figure 7 in the embodiment of the present invention are used to distinguish the correction patterns corresponding to S2 and S3, so the lines of the non-correction patterns are represented by dotted lines, but not limited thereto. And, since the same side edge of the global polygon 101 in the embodiment of the present invention (for example Figure 4 the side edge 101a extending in the horizontal X direction or another side edge 101b in) will be simultaneously cut into different layout blocks 10, for example, the side edge 101a of the global polygon 101 will be simultaneously cut into layout block 10a and layout block 10b, and its another side edge 101b will be simultaneously cut into layout block 10b and layout block 10c; therefore, the side edges simultaneously cut into different layout blocks 10 will be respectively subjected to the first optical proximity correction with different layout blocks 10. For example, the side edge 101a or another side edge 101b of the global polygon 101 will be subjected to multiple first optical proximity corrections, and the correction rules (outward edge expansion processing or inward edge contraction processing) of the first optical proximity correction performed in different layout blocks 10 need to be determined based on the correction rules of each layout block 10, that is, the correction rules of the same part of the same side edge in different layout blocks 10 may be the same or different.

[0062] Please continue to refer to Figures 5 to 8 In the above step S104, after obtaining the first corrected layout of the original layout 100, it can be determined whether the parts of the edges of all the main graphics (global polygon 101 and other main graphics 102) on the original layout 100 located in different layout blocks 10 are corrected in the same way in the first optical proximity correction performed in the relevant layout blocks 10. If they are different, the main graphic containing this edge is regarded as the main graphic with stitching defects. That is, if the correction methods of the first optical proximity correction performed on the same part of the same edge of the main graphic in the relevant layout blocks 10 are respectively edge expansion processing and edge contraction processing (different correction directions), it means that the main graphic containing this edge will have problems with inconsistent stitching. For example, the edge 101a or another edge 101b of the global polygon 101 will be corrected multiple times in the relevant layout block 10 where it is located, and thus the edge 101a or another edge 101b is prone to problems with inconsistent stitching. In another embodiment, after obtaining the first corrected layout of the original layout 100, it is also possible to set at least one cut point on the parts of the edges of all the main graphics (global polygon 101 and other main graphics 102) on the original layout 100 located in different layout blocks 10 to cut the edge into multiple sub-segments, and then determine whether the correction methods of the first optical proximity correction performed on the sub-segments in the relevant layout blocks are the same, so as to judge which main graphics on the original layout 100 will have stitching defects, that is, the main graphic containing this edge will have problems with inconsistent stitching; otherwise, it means that the main graphic containing this edge will not have problems with inconsistent stitching.

[0063] Next, after screening out the main graphics with stitching defects from the original layout 100, for example, the main graphic screened out is the global polygon 101, at least some of the other main graphics 102 located around the global polygon 101 can be further combined with the global polygon 101 into a graphic set to represent the environmental impact of the other main graphics on the global polygon 101 during the second optical proximity correction by the at least some of the other main graphics 102, but not limited thereto. It should be understood that when the main graphics corresponding to multiple first corrected graphics screened out from the first corrected layout all have problems with inconsistent stitching, a graphic set should be formed respectively for each main graphic corresponding to the first corrected graphics screened out and at least some of the other main graphics around it, but not limited thereto.

[0064] After that, in the above step S105, for each of the graphic sets formed in step S104, it can be respectively used as a new layout block, and the main graphic corresponding to the first corrected graphic (such as the global polygon 101) that has the problem of inconsistent splicing and stitching (splicing defect) screened out in each of the graphic sets is subjected to a second optical proximity correction to obtain a second corrected graphic of the main graphic (such as the global polygon 101), for example Figure 9 as shown in S4 Figure 9 illustrated in an embodiment of the present invention Figure 4 a partial graphic of the global polygon shown in Figure 1 an example diagram of the second corrected graphic after performing the optical proximity correction method shown in Figure 9 where S1 in is the target graphic of the partial graphic of the global polygon. Since in the embodiment of the present invention, during the second optical proximity correction of the screened main graphic, it is used as a new layout block, that is, the screened main graphic will not be sliced again, but is subjected to optical proximity correction as a whole, thereby avoiding the problem of reducing the edge placement error EPE and increasing the process window due to the inconsistent behavior and changes of the main graphic such as the global polygon in different layout blocks.

[0065] Next, in the above step S106, the first corrected graphic corresponding to the screened main graphic such as the global polygon 101 in the first corrected layout can be removed, and then the second corrected graphic corresponding to the main graphic such as the global polygon 101 is backfilled to the removed position on the first corrected layout to obtain a second corrected layout. After that, the second corrected layout is subjected to graphic inspection to determine whether the second corrected layout lacks the first corrected graphic or the second corrected graphic corresponding to the main graphic. If so, return to execute step S106. Otherwise, the second corrected layout is used as the target corrected layout of the original layout 100, and the optical proximity correction is ended. In an embodiment, the purpose of performing graphic inspection on the second corrected layout is to check whether there is a problem of missing the replacement of the second corrected graphic of a certain main graphic or replacing the first corrected graphic that does not need to be replaced with the second corrected graphic of another main graphic during the execution of the above step S106. Exemplarily, the graphic inspection may include: performing an exclusive OR operation on the second corrected layout and the initial layout. For example, an exclusive OR operation can be performed on the total number of the first corrected graphics and the main graphics corresponding to the second corrected graphics included in the second corrected layout and the total number of the main graphics included in the initial layout. If the operation result is 0, the second corrected layout is used as the target corrected layout of the original layout 100, and the optical proximity correction is ended. Otherwise, return to execute step S106 until the operation result is 0.

[0066] In one embodiment, if it is determined in the above step S104 that the portions of the line edges of all the main patterns in the original layout 100 located in different layout sub-blocks have the same correction methods for the first optical proximity correction performed in the relevant layout sub-blocks 10, it indicates that the first corrected patterns in the formed first corrected layout do not need to be replaced. Only the corrected patterns corresponding to the intersection operation of the sub-patterns corresponding to the portions of the same line edge in S2 and S3 in Figure 8 or Figure 6 and Figure 7 located in different layout sub-blocks 10 are used as the target corrected layout of the original layout 100, but not limited thereto. Figure 8 or Figure 6 and Figure 7 After the intersection operation of the corrected patterns corresponding to the portions of the same line edge in S2 and S3 in Figure 8 or Figure 6 and Figure 7 located in different layout sub-blocks 10, the corresponding corrected patterns are used as the target corrected layout of the original layout 100, but not limited thereto.

[0067] It can be calculated that by using the optical proximity correction method provided by the prior art to correct the two line edges extending horizontally of the global polygon (such as 101a and 101b in Figure 4 ), the edge placement errors EPE of the corresponding target pattern and the corrected pattern are 2.3 nm and 1.9 nm respectively. And by using the optical proximity correction method provided in the embodiment of the present invention to correct the two line edges extending horizontally of the same global polygon (such as 101a and 101b in Figure 4 ), the edge placement errors EPE of the corresponding target pattern and the corrected pattern are both 0. Obviously, the optical proximity correction method provided by the present invention can achieve the purpose of reducing the edge placement error EPE of the global polygon and increasing the process window. Figure 4 After correcting the two line edges extending horizontally of the global polygon (such as 101a and 101b in Figure 4 ) by using the optical proximity correction method provided by the prior art, the edge placement errors EPE of the corresponding target pattern and the corrected pattern are 2.3 nm and 1.9 nm respectively. And by using the optical proximity correction method provided in the embodiment of the present invention to correct the two line edges extending horizontally of the same global polygon (such as 101a and 101b in Figure 4 ), the edge placement errors EPE of the corresponding target pattern and the corrected pattern are both 0. Obviously, the optical proximity correction method provided by the present invention can achieve the purpose of reducing the edge placement error EPE of the global polygon and increasing the process window. Figure 4 After correcting the two line edges extending horizontally of the same global polygon (such as 101a and 101b in Figure 4 ) by using the optical proximity correction method provided in the embodiment of the present invention, the edge placement errors EPE of the corresponding target pattern and the corrected pattern are both 0. Obviously, the optical proximity correction method provided by the present invention can achieve the purpose of reducing the edge placement error EPE of the global polygon and increasing the process window.

[0068] In summary, the present invention provides an optical proximity correction method, including: providing an initial layout, the initial layout including a plurality of main patterns, dividing the initial layout to obtain a plurality of layout sub-blocks, wherein at least one main pattern is divided into a plurality of sub-patterns, and different sub-patterns are located in different layout sub-blocks, respectively performing a first optical proximity correction on the patterns in the plurality of layout sub-blocks, and splicing the corrected plurality of layout sub-blocks to obtain a first corrected layout of the initial layout, determining at least one first corrected pattern with a splicing defect from the first corrected layout, and forming a graphic set with the main pattern corresponding to the determined first corrected pattern and other main patterns located around the main pattern, using the graphic set as a new layout sub-block, and performing a second optical proximity correction on the main pattern corresponding to the first corrected pattern in the graphic set to obtain a second corrected pattern of the main pattern, removing the first corrected pattern corresponding to the main pattern determined in the first corrected layout, and backfilling the second corrected pattern corresponding to the main pattern to the removed position on the first corrected layout to obtain a second corrected layout.

[0069] In the present invention, after performing at least one optical proximity correction on all the main patterns in the original layout to obtain a first corrected layout, at least one main pattern with a stitching defect is screened out from the first corrected layout, and the screened main pattern is re-performed with optical proximity correction to obtain a second corrected pattern, that is, only a part of the main patterns in the original layout are re-performed with optical proximity correction, such as the main patterns (global polygons) in different graphic regions being sliced into different layout blocks. The unexpected effect is that the number of iterations of the optical proximity correction for the original layout can be reduced, that is, the efficiency of the optical proximity correction is improved; then, the first corrected pattern corresponding to the screened main pattern in the first corrected layout is replaced with the second corrected pattern, so as to combine the first corrected patterns of some of the main patterns and the second corrected patterns of at least one of the main patterns to form the final corrected layout of the original layout. The unexpected effect is that by using the method of whether the correction methods of the main patterns in the relevant layout blocks are the same, it is determined whether the behaviors and changes of the main patterns, such as global polygons, in different layout blocks are unified, and by re-performing the optical proximity correction, the behaviors and changes of the main patterns in different layout blocks are adjusted and unified, thereby achieving the purpose of reducing the edge placement error EPE, increasing the process window, and improving the product yield.

[0070] An embodiment of the present invention further provides an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus.

[0071] The memory is used to store a computer program.

[0072] The processor, when executing the program stored on the memory, implements an optical proximity correction method provided by an embodiment of the present invention.

[0073] In addition, other implementation manners of the optical proximity correction method implemented by the processor executing the program stored on the memory are the same as those mentioned in the method embodiment part, and will not be elaborated here.

[0074] The communication bus mentioned in the above control terminal may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0075] The communication interface is used for communication between the above electronic device and other devices.

[0076] The memory may include a Random Access Memory (RAM), or may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0077] The aforementioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0078] In another embodiment provided by the present invention, there is also provided a computer-readable storage medium, in which instructions are stored. When it runs on a computer, it causes the computer to execute any one of the optical proximity correction methods described in the above embodiments.

[0079] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

[0080] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements but also other elements not expressly listed, or elements that are inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device that includes the element.

[0081] Each embodiment in this specification is described in a related manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the embodiments of the device, electronic device, and computer-readable storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0082] The above are only the preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are all included in the protection scope of the present invention.

Claims

1. An optical proximity correction method, characterized in that, Including: Providing an initial layout, the initial layout including a plurality of main graphics; Dividing the initial layout to obtain a number of layout blocks, where at least one of the main graphics is divided into a plurality of sub-graphics, and different sub-graphics are located in different layout blocks; Performing first optical proximity correction on the graphics in the number of layout blocks respectively, and splicing the corrected layout blocks to obtain a first corrected layout of the initial layout; Determining at least one first corrected graphic with a splicing defect from the first corrected layout, and forming a graphic set with the main graphic corresponding to the determined first corrected graphic and other main graphics located around the main graphic; Taking a graphic set as a new layout block, and performing second optical proximity correction on the main graphic corresponding to the first corrected graphic in the graphic set to obtain a second corrected graphic of the main graphic; Removing the first corrected graphic corresponding to the main graphic determined from the first corrected layout, and backfilling the second corrected graphic corresponding to the main graphic to the removed position on the first corrected layout to obtain a second corrected layout; 2. The optical proximity correction method according to claim 1, wherein Before dividing the initial layout, corresponding auxiliary graphics are added to the intervals between adjacent main graphics in the initial layout according to a preset auxiliary graphic adding rule; 3. The optical proximity correction method according to claim 1, wherein After obtaining the second corrected layout, it further includes: Performing graphic inspection on the second corrected layout to determine whether the second corrected layout lacks the second corrected graphic corresponding to the main graphic. If so, return to execute the step of removing the first corrected graphic corresponding to the main graphic determined from the first corrected layout, and backfilling the second corrected graphic corresponding to the main graphic to the removed position on the first corrected layout to obtain a second corrected layout; 4. The optical proximity correction method according to claim 3, wherein The graphic inspection includes: performing an exclusive OR operation on the second corrected layout and the initial layout; 5. The optical proximity correction method according to claim 1, wherein At least a part of a line edge of the main graphic divided into a plurality of sub-graphics is located in different layout blocks; 6. The optical proximity correction method according to claim 5, characterized in that The step of determining at least one first corrected graphic with a splicing defect from the first corrected layout includes: Judging whether the correction methods of the first optical proximity correction performed on the part of the line edge of the main graphic located in different layout blocks in the relevant layout blocks are the same. If different, the main graphic including the line edge is used as the main graphic with a splicing defect; 7. The optical proximity correction method according to claim 6, wherein If the correction methods of the first optical proximity correction performed on the part of the line edge of the main graphic located in different layout blocks in the relevant layout blocks are the same, it is determined that the first corrected graphic corresponding to the main graphic including the line edge has no splicing defect, and further, the corrected graphic obtained by performing an intersection operation on the first corrected graphics of the part of the line edge in different layout blocks is used as the target corrected layout of the main graphic including the line edge; 8. The optical proximity correction method according to claim 5, characterized in that, The step of determining at least one first corrected graphic with a splicing defect from the first corrected layout includes: At least one cutting point is set on the partial line edges of the main pattern located in different layout blocks to cut the line edges into multiple sub-segments, and it is judged whether the correction methods of the first optical proximity correction performed on the sub-segments in the relevant layout blocks are the same. If they are different, the main pattern containing the sub-segment is used as the main pattern with stitching defects.

9. The optical proximity correction method according to claim 6 or 8, characterized in that, The correction method of the first optical proximity correction includes: performing an outward edge expansion process or an inward edge contraction process on the line edge of the main pattern in a direction perpendicular to the line edge.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the optical proximity correction method according to any one of claims 1 to 9 are implemented.

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