A wide voltage current range v / i source system

Abstract

The application discloses a wide voltage and current range V / I source system, which comprises a power amplifier U1, a parameter measurement unit, a compensation circuit, a current sampling circuit, a voltage sampling circuit, a positive power module, a clamping circuit and a mode selector; the positive power module is connected with a positive power end of the power amplifier U1; the parameter measurement unit has multiple channels to respectively set output voltage / output current of the power amplifier U1, clamping voltage / clamping current of the clamping circuit and adjust output voltage of the positive power module; the compensation circuit can adapt to different capacitive loads to adjust the setting time of output voltage / output current of the power amplifier U1, and the output end of the power amplifier U1 supplies power for a DUT; the application has excellent performance, can improve test quality and reduce test cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of V / I source, and particularly relates to a wide-voltage-current-range V / I source system. BACKGROUND

[0002] A V / I source is a programmable voltage / current source, and is one of the most basic and important devices of ATE (Automatic Test Equipment), which mainly provides voltage / current (FV / FI) for a DUT (Device Under Test) and measures the current / voltage (MI / MV) of corresponding pins. A common voltage / current source can usually only work in one quadrant, while a V / I source can work in four quadrants, that is, when providing positive / negative voltage (FV mode) for the DUT, the current can be positive (flowing to the DUT) or negative (flowing to the V / I source); when providing positive / negative current (FI mode), the voltage can be positive or negative. To ensure the safety of the DUT, the V / I source also integrates a clamping circuit, which can set the upper / lower limit of the clamping current when FV, and if the DUT has an overcurrent anomaly, the VI source will keep the current constant at the upper / lower limit; when FI, the upper / lower limit of the clamping voltage can be set, and if the DUT has an overvoltage anomaly, the VI source will keep the voltage constant at the upper / lower limit. In terms of dynamic performance, the rise time and stability are the two most important indicators of the V / I source. On the one hand, the test cost requires the test time to be as short as possible, so the V / I source output stabilization time needs to be as small as possible, which is usually tens or hundreds of us; on the other hand, the test quality requires that the chip test results are stable and reliable, which requires the V / I source to be stable enough. For a V / I source, a short rise time may cause overshoot and ringing, especially in the scenario of driving a large capacitive load. Therefore, the rise time and stability are also the “sword” and “shield” of the V / I source, and a V / I source for chip production testing usually makes a compromise in these two aspects.

[0003] In recent years, digital-analog hybrid power management chips have developed rapidly. Such chips integrate digital circuits, analog circuits and high-power devices. During production testing, the ATE is required to provide a power source with a large range of voltage and current. For example, when testing a digital circuit module, a low-voltage high-precision voltage is required to be applied, and when testing a power module, a high-voltage large-current power source is required to be provided. Currently, there are few ATE board cards that can simultaneously meet such requirements, and in the test scheme, multiple board cards are often combined to power the chip under test, which increases the complexity of chip testing and also increases the test cost. Figure 1For the existing test scheme, the scheme uses a combination of a pulsed high-voltage large-current board card, a high-voltage small-current board card and a low-voltage small-current board card to power a digital-analog hybrid power management chip. The pulsed high-voltage large-current board card mainly provides a high-power power supply and a load, such as a test power module that needs to use the board card to provide +30V voltage and ±3A current; the measurement of the leakage current of the high-voltage pin of the chip is realized by the high-voltage small-current board card, such as the board card providing +48V to the chip to be tested to measure about 100uA of leakage current; due to the current capacity of the low-voltage board card is usually only 1A, multiple channels need to be connected in parallel to power the chip. Three different specifications of board cards are needed to realize the test of the digital-analog hybrid power management chip, which has high complexity and high test cost. SUMMARY

[0004] The present application aims to at least solve one of the problems in the prior art, and provide a wide voltage and current range V / I source system with reduced test complexity and cost.

[0005] The wide voltage and current range V / I source system according to the embodiments of the present application comprises a power amplifier U1, a parameter measurement unit, a compensation circuit, a current sampling circuit, a voltage sampling circuit, a positive power module, a clamping circuit and a mode selector; the positive power module is connected to the positive power supply end of the power amplifier U1; the parameter measurement unit has multiple channels to respectively set the output voltage / output current of the power amplifier U1, the clamping voltage / clamping current of the clamping circuit and adjust the output voltage of the positive power module; the compensation circuit can adapt to different capacitive loads to adjust the setting time of the output voltage / output current of the power amplifier U1, and the output end of the power amplifier U1 supplies power to the DUT; the current sampling circuit is used to collect the output current of the power amplifier U1 and feed back the current collection signal to the mode selector; the voltage sampling circuit is used to collect the output voltage of the power amplifier U1 and feed back the voltage collection signal to the mode selector; in the FV mode, the mode selector selects the voltage collection signal to feed back to the power amplifier U1 and selects the current collection signal to feed back to the clamping circuit; in the FI mode, the mode selector selects the current collection signal to feed back to the power amplifier U1 and selects the voltage collection signal to feed back to the clamping circuit.

[0006] According to some embodiments of the present application, a negative power module is further included, and the negative power module is connected to the negative power supply end of the power amplifier U1.

[0007] According to some embodiments of the present application, the parameter measurement unit adopts a PMU chip, a DPS or a DAC chip, the parameter measurement unit comprises channel 0, channel 1, channel 2 and channel 3, the channel 0 of the parameter measurement unit is connected to the input end of the power amplifier U1, the channel 1 of the parameter measurement unit is connected to the negative input end of the clamping circuit, the channel 2 of the parameter measurement unit is connected to the positive input end of the clamping circuit, and the channel 3 of the parameter measurement unit is connected to the input end of the positive power supply module.

[0008] According to some embodiments of the present application, the mode selector comprises a voltage / current driving mode selector M1, the input ends of the voltage / current driving mode selector M1 are respectively connected to the output end of the current sampling circuit and the output end of the voltage sampling circuit, the output end of the voltage / current driving mode selector M1 is connected to the input end of the power amplifier U1, in the FV mode, the voltage / current driving mode selector M1 selects the voltage collection signal to feed back to the power amplifier U1, and in the FI mode, the voltage / current driving mode selector M1 selects the current collection signal to feed back to the power amplifier U1.

[0009] According to some embodiments of the present application, the mode selector comprises a current / voltage clamping mode selector M2, the input ends of the current / voltage clamping mode selector M2 are respectively connected to the output end of the current sampling circuit and the output end of the voltage sampling circuit, the output end of the current / voltage clamping mode selector M2 is connected to the input end of the power amplifier U1, in the FV mode, the current / voltage clamping mode selector M2 selects the current collection signal to feed back to the clamping circuit, and in the FI mode, the current / voltage clamping mode selector M2 selects the voltage collection signal to feed back to the clamping circuit.

[0010] According to some embodiments of the present application, the compensation circuit comprises a resistor R3, a plurality of capacitors and a compensation capacitor selector M3, the input ends of the compensation capacitor selector M3 are respectively connected to one end of the plurality of capacitors, the output end of the compensation capacitor selector M3 is respectively connected to the resistor R3 and the inverting input end of the power amplifier U1, the other end of the plurality of capacitors is respectively connected to the output end of the power amplifier U1, and different capacitive loads are adapted by switching the corresponding capacitors through the compensation capacitor selector M3.

[0011] According to some embodiments of the present application, the current sampling circuit comprises a sampling resistor Rsense and an operational amplifier U2, the positive end of the sampling resistor Rsense is respectively connected to the output end of the power amplifier U1 and the non-inverting input end of the operational amplifier U2, the negative end of the sampling resistor Rsense is connected to the inverting input end of the operational amplifier U2, and the output end of the operational amplifier U2 is connected to the input end of the mode selector.

[0012] According to some embodiments of the present application, the current sampling circuit further comprises an operational amplifier U21, a resistor R21 and a resistor R22, the output terminal of the operational amplifier U2 is connected to the non-inverting input terminal of the operational amplifier U21, the inverting input terminal of the operational amplifier U21 is connected to ground through the resistor R21, one end of the resistor R22 is connected to the inverting input terminal of the operational amplifier U21, and the other end of the resistor R22 is connected to the output terminal of the operational amplifier U21 and the input terminal of the mode selector respectively.

[0013] According to some embodiments of the present application, the voltage sampling circuit comprises an operational amplifier U3, an operational amplifier U31, an operational amplifier U32, a resistor R31, a resistor R32 and a resistor R33, the non-inverting input terminal of the operational amplifier U31 is connected to the power input terminal of the DUT, the inverting input terminal of the operational amplifier U31 is connected to its output terminal, the output terminal of the operational amplifier U31 is connected to the non-inverting input terminal of the operational amplifier U3 through the resistor R1, the non-inverting input terminal of the operational amplifier U32 is connected to the ground terminal of the DUT, the inverting input terminal of the operational amplifier U32 is connected to its output terminal, the output terminal of the operational amplifier U32 is connected to the inverting input terminal of the operational amplifier U3 and one end of the resistor R33 through the resistor R32 respectively, and the other end of the resistor R33 is connected to the output terminal of the operational amplifier U3 and the input terminal of the mode selector respectively.

[0014] According to some embodiments of the present application, the mode selector adopts an analog switch.

[0015] The wide voltage and current range V / I source system according to the embodiments of the present application has at least the following beneficial effects:

[0016] 1. A multi-channel parameter measurement unit is used as a voltage regulator, and only one parameter measurement unit is needed to complete the output setting of the V / I source, the clamping setting and the setting of the output voltage of the positive power module; by adjusting the output voltage of the positive power module, a wide range of voltage and current can be obtained, the testing of the analog-digital hybrid power management chip is realized, multiple specifications of voltage and current board cards are not needed, the integration degree is high, and the testing complexity and cost are effectively reduced;

[0017] 2. The compensation circuit is used for adjusting the setting time of the output voltage / output current, can adapt to different capacitive loads, and is thus applicable to scenarios requiring fast response and reduces the chip testing time;

[0018] 3, current sampling circuit, voltage sampling circuit, mode selector and clamping circuit make up feedback network, the feedback network connects the inverting input and output of power amplifier U1, and with power amplifier U1 makes up a inverting summation circuit;Compensation circuit makes up another feedback network, connects the inverting input and output of power amplifier U1, and with power amplifier U1 makes up an integral circuit.This circuit works in FV mode (drive voltage mode) or FI mode (drive current mode), in FV mode, the output voltage of V / I source returns to the input of power amplifier U1 through feedback network, the output current of V / I source returns to the input of clamping circuit through feedback network, as the trigger source of clamping circuit;In FI mode, the output current of V / I source returns to the input of power amplifier U1 through feedback network, the output voltage of V / I source returns to the input of clamping circuit through feedback network, as the trigger source of clamping circuit;This application uses power amplifier U1 as the output driver of V / I source system, at the same time, uses power amplifier U1 as the main amplifier of negative feedback system, performs "summation" operation, in addition, power amplifier U1 is also the main amplifier of integral circuit.I.e. uses one power amplifier U1 to realize summation, integral, drive and other circuit functions.In conventional scheme, summation, integral and drive circuit need one operational amplifier respectively.Therefore, this application has high integration, obviously reduces test cost.

[0019] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0020] The specific embodiments of the present application will be further described with reference to the drawings;

[0021] Figure 1 Is the existing digital-analog hybrid power management chip production test schematic diagram;

[0022] Figure 2 Is the circuit block diagram of V / I source system of the present application;

[0023] Figure 3 Is the circuit schematic diagram of V / I source system of the present application;

[0024] Figure 4 Is the circuit schematic diagram of parameter measurement unit (PMU module);

[0025] Figure 5 Is the circuit schematic diagram of positive power supply module;

[0026] Figure 6 Is the circuit schematic diagram of negative power supply module;

[0027] Figure 7 Is the schematic diagram of current sampling circuit;

[0028] Figure 8 is a schematic diagram of a voltage sampling circuit. DETAILED DESCRIPTION

[0029] This part will describe the specific embodiments of the present application in detail, the preferred embodiments of the present application are shown in the drawings, the role of the drawings is to supplement the description of the text part with graphics, so that people can intuitively and visually understand each technical feature and the overall technical scheme of the present application, but it cannot be understood as a limitation on the protection scope of the present application.

[0030] In the description of the present application, it should be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right and the like, is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation on the present application.

[0031] In the description of the present application, several meanings are one or more, and the meaning of multiple is two or more, greater than, less than, more than and the like are not included in the number, above, below, within and the like are included in the number. If it is described as first, second, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the order of indicated technical features.

[0032] Reference Figures 1 to 8The application provides a wide voltage and current range V / I source system, which comprises a power amplifier U1, a parameter measurement unit 10, a compensation circuit 20, a current sampling circuit 31, a voltage sampling circuit 32, a positive power module 41, a negative power module 42, a clamping circuit 50 and a mode selector 60; the positive power module 41 is connected with the positive power module 41 end of the power amplifier U1, and the negative power module 42 is connected with the negative power module 42 end of the power amplifier U1; the parameter measurement unit 10 has multiple channels to respectively set the output voltage / output current of the power amplifier U1, the clamping voltage / clamping current of the clamping circuit 50 and the output voltage of the positive power module 41; the compensation circuit 20 can adapt to different capacitive loads to adjust the setting time of the output voltage / output current of the power amplifier U1, and the output end of the power amplifier U1 supplies power for the DUT; the current sampling circuit 31 is used for collecting the output current of the power amplifier U1 and feeding back the current collection signal to the mode selector 60; the voltage sampling circuit 32 is used for collecting the output voltage of the power amplifier U1 and feeding back the voltage collection signal to the mode selector 60; in the FV mode, the mode selector 60 selects the voltage collection signal to feed back to the power amplifier U1 and selects the current collection signal to feed back to the clamping circuit 50; in the FI mode, the mode selector 60 selects the current collection signal to feed back to the power amplifier U1 and selects the voltage collection signal to feed back to the clamping circuit 50; wherein the current sampling circuit 31, the voltage sampling circuit 32, the mode selector 60 and the clamping circuit 50 form a feedback network, the feedback network is connected with the inverting input end and the output end of the power amplifier U1 and forms an inverting summing circuit with the power amplifier U1; the compensation circuit 20 forms another feedback network, which is connected with the inverting input end and the output end of the power amplifier U1 and forms an integral circuit with the power amplifier U1. The circuit works in the FV mode (driving voltage mode) or the FI mode (driving current mode), in the FV mode, the output voltage of the V / I source returns to the input end of the power amplifier U1 through the feedback network, the output current of the V / I source returns to the input end of the clamping circuit 50 through the feedback network and serves as the trigger source of the clamping circuit 50; in the FI mode, the output current of the V / I source returns to the input end of the power amplifier U1 through the feedback network, and the output voltage of the V / I source returns to the input end of the clamping circuit 50 through the feedback network and serves as the trigger source of the clamping circuit 50; the application uses the power amplifier U1 as the output driver of the V / I source system and simultaneously uses the power amplifier U1 as the main amplifier of the negative feedback system to perform the "summing" operation, and the power amplifier U1 is also the main amplifier of the integral circuit. That is, one power amplifier U1 realizes the functions of the summing, integral and driving circuits. In the conventional scheme, one operational amplifier is needed for the summing, integral and driving circuits. Therefore, the application has high integration and can obviously reduce the test cost.

[0033] In certain embodiments, as Figure 2and Figure 3 As shown, the mode selector 60 includes a voltage / current drive mode selector M1 and a current / voltage clamping mode selector M2. The input terminal of the voltage / current drive mode selector M1 is connected to the output terminal of the current sampling circuit 31 and the output terminal of the voltage sampling circuit 32, respectively. The output terminal of the voltage / current drive mode selector M1 is connected to the input terminal of the power amplifier U1. In FV mode, the voltage / current drive mode selector M1 selects the voltage acquisition signal to feed back to the power amplifier U1. In FI mode, the voltage / current drive mode selector M1 selects the current acquisition signal to feed back to the power amplifier U1. The input terminals of the current / voltage clamping mode selector M2 are connected to the output terminals of the current sampling circuit 31 and the voltage sampling circuit 32, respectively. The output terminal of the current / voltage clamping mode selector M2 is connected to the input terminal of the power amplifier U1. In FV mode, the current / voltage clamping mode selector M2 selects the current acquisition signal to feed back to the clamping circuit 50. In FI mode, the current / voltage clamping mode selector M2 selects the voltage acquisition signal to feed back to the clamping circuit 50. In this example, the voltage / current drive mode selector M1 and the current / voltage clamping mode selector M2 are both ADG1419. The ADG1419 is an analog switch manufactured by Analog Devices (ADI) with an on-resistance of 2.1Ω and a power supply voltage support of ±15V.

[0034] In some embodiments, such as Figure 3 As shown, the compensation circuit 20 includes a resistor R3, multiple capacitors C1 to C4, and a compensation capacitor selector M3. The input terminals of the compensation capacitor selector M3 are connected to one end of each of the capacitors C1 to C4. The output terminals of the compensation capacitor selector M3 are connected to the resistor R3 and the inverting input terminal of the power amplifier U1. The other ends of the capacitors C1 to C4 are connected to the output terminal of the power amplifier U1. The compensation capacitor selector M3 switches the corresponding capacitor to adapt to different capacitive loads. The specific number of capacitors is not limited here and can be set according to the specific load capacitance.

[0035] like Figure 3 In this circuit, four resistors R1 to R4 are connected to a common node. The other end of resistor R1 is connected to channel 0 of the PMU chip, the other end of resistor R2 is connected to the output of the voltage / current drive mode selector M1, and the other end of resistor R4 is electrically connected to the clamping circuit. Let the currents flowing through R1, R2, R3, and R4 be Ir1, Ir2, Ir3, and Ir4, respectively; the current at the inverting input of power amplifier U1 be In; and the current at the data selector of compensation circuit 20 be Im3. From the current equation, we can obtain...

[0036] Ir1+Ir2+Ir3+Ir4=0 (1)

[0037] Ir3=In+Im3 (2)

[0038] Let the voltage of channel 0 of the parameter measurement unit 10 be Vpmu_ch0, and the voltage of the common node of the R1, R2, R3 and R4 resistors be Vnode, then

[0039]

[0040] Let the output voltage of the voltage / current drive mode selector M1 be Vm1, then

[0041]

[0042] Let the output voltage of the V / I source be Vforce, the output current be Iforce, the output voltage of the voltage sampling circuit 32 be Vsense, the output current of the current sampling circuit 31 be Isense, and the sampling resistor be Rsense. For the convenience of explaining the principle, the line loss is not considered for the time being, and it is considered that the AGND plane has no voltage drop, then

[0043] Vforce = Vsense (5)

[0044] Iforce = Isense (6) When the V / I source system reaches equilibrium, the integrator no longer integrates, and the current flowing through the integration capacitor is 0, that is

[0045] Im3 = 0 (7)

[0046] Let the voltage at the inverting input terminal of the power amplifier U1 be Vn, and the voltage at the non-inverting input terminal be Vp. From the virtual short and the virtual short, it can be obtained that

[0047] In = 0 (8)

[0048] Vn = Vp = 0 (9)

[0049]

[0050] When the output current / voltage does not exceed the clamping range, the clamping circuit 50 outputs a high resistance, so

[0051] Ir4 = 0 (11)

[0052] Let the gain of the voltage sampling circuit 32 be Gain_V. In the FV mode, the voltage / current drive mode selector M1 outputs the voltage of the voltage sampling circuit 32, that is

[0053] Vm1 = [Vsense** Gain_V (12)

[0054] Let the gain of the current sampling circuit 31 be Gain_I. In the FI mode, the voltage / current drive mode selector M1 outputs the voltage of the current sampling circuit 31, that is

[0055] Vm1 = [sense * Resnse * Gain_I (13)

[0056] By integrating equations (1)-(12), we have

[0057]

[0058] By integrating equations (1)-(11) and (13), we have

[0059]

[0060] As can be seen from equation (14), in the FV mode, when the output current does not exceed the clamping range, the output voltage of the V / I source and the voltage of PMU channel 0 are in opposite phases, and the size is R2 / (R1*Gain_V) times the voltage of channel 0. As can be seen from equation (15), in the FI mode, when the output voltage does not exceed the clamping range, the output current of the V / I source and the voltage of channel 0 are in opposite phases, and the size is R2 / (R1*Rsense*Gain_I) times the voltage of channel 0 of the parameter measurement unit 10.

[0061] Let the voltage at the output end of the power amplifier U1 be Vpa, then

[0062]

[0063] The relationship between the output voltage and the resistance R3 and the capacitor can be obtained by sorting

[0064]

[0065] As can be seen from equation (35), the output voltage of the power amplifier U1 is inversely proportional to the integral time constant R3C. The larger the integral time constant, the slower the change of the output voltage of the power amplifier U1.

[0066] Generally speaking, the larger the capacitive load, the larger the integral time constant is required to prevent the V / I source from overshooting and ringing. In order to drive a larger range of capacitive load and at the same time make the output stable time smaller, four capacitors (capacitors C1-C4) are provided in the embodiment, and the corresponding capacitors are switched by the compensation capacitor selector M3 to adapt to different capacitive loads, so as to be applicable to the scene requiring fast response and reduce the chip test time. The compensation capacitor selector of the embodiment uses ADG5401.

[0067] The capacitance of the compensation capacitor needs to be determined by combining the frequency domain and time domain simulation results. From the frequency domain perspective, the phase margin of the loop gain needs to be greater than 45° for a negative feedback system to achieve stable output, otherwise oscillation or ringing effect is likely to occur. The V / I source system is a negative feedback system and needs to follow this principle. The loop gain AC parameters of the V / I source system are simulated by software. The two-port network method is used in the test circuit, the input end (PMU channel 0) is grounded, the connection between the power amplifier U1 output and the feedback loop is disconnected, and an AC voltage source is connected at the feedback loop. To more accurately measure the loop, the test considers the load effect, that is, a copy of the feedback loop is connected to the power amplifier U1 output as its load. The V / I source drive 100uF capacitive load is set in the test circuit, and by adjusting the capacitance of the compensation capacitor C1, when the loop gain is 0dB and the phase is -135°, C1 at this time is the minimum capacitor that meets the phase margin. The C1 capacitance obtained by the test circuit is 215pF. That is, if the V / I source circuit wants to drive a 100uF capacitive load, the compensation capacitor needs to be greater than 215pF.

[0068] The frequency domain analysis obtains the minimum value of the compensation capacitor, which only ensures that the V / I source circuit does not oscillate within the bandwidth range, and the circuit may still have overshoot and ringing. In order to reduce the ringing effect, the compensation capacitor size needs to be adjusted in combination with the time domain waveform, especially the step response result. The V / I source is simulated in time domain by software, and the input of the test circuit is a 250Hz square wave with a high level of 0V and a low level of -2.5V, and the output is a square wave with a low level of 0V and a high level of 50V. By adjusting the capacitance of the compensation capacitor C1, the ringing effect of the output current Isense of the power amplifier U1 and the output voltage Vout of the V / I source is smaller. When C1 is greater than 3nF, the ringing effect can be ignored. By combining the frequency domain and time domain simulation results and the minimum stable time requirement, when the V / I source drives a 100uF capacitive load, the compensation capacitor is 3nF. Based on the above method of combining frequency domain and time domain simulation, the corresponding relationship between the compensation capacitor and the load capacitor of the present embodiment can be obtained, as shown in Table 1.

[0069]

[0070]

[0071] Table 1 compensation capacitor and load capacitor correspondence table

[0072] In some embodiments, the parameter measurement unit 10 employs a PMU chip, which is capable of providing functions such as voltage driving (FV), current driving (FI), measured voltage (MV), and measured current (MI). The PMU chip used in this embodiment is AD5522 of ADI Company. The chip integrates a 16-bit DAC, supports Kelvin connection, and provides four independent output channels (channel 0, channel 1, channel 2, and channel 3). Channel 0 of the parameter measurement unit 10 is connected to the input end of the power amplifier U1, channel 1 of the parameter measurement unit 10 is connected to the negative input end of the clamping circuit 50, channel 2 of the parameter measurement unit 10 is connected to the positive input end of the clamping circuit 50, and channel 3 of the parameter measurement unit 10 is connected to the input end of the positive power module 41. That is, using the multi-channel parameter measurement unit 10 as a voltage regulator, only one parameter measurement unit 10 is needed to complete the output setting of the V / I source, the clamping setting, and the setting of the output voltage of the positive power module 41; by adjusting the output voltage of the positive power module 41, a wide range of voltage and current can be obtained, the testing of the analog-digital hybrid power management chip is realized, multiple specifications of voltage and current board cards are not needed, the integration degree is high, and the testing complexity and cost are effectively reduced.

[0073] Figure 4 The schematic diagram of the PMU chip for this embodiment is shown in FIG. 6. Since the internal sampling resistance of AD5522 only supports 2 mA current at most, in order to improve the universality of the circuit, the system uses an external sampling resistance. The resistance values of the external sampling resistances R82 / R85 / R83 / R84 of the four channels are all 20 Ω, and the PMU can provide an external current of 50 mA at most. The discrete DAC output end usually has only one line, while the PMU output channel supports Kelvin connection, that is, two lines of FORCE and SENSE are provided, and this structure can improve the precision and consistency of the V / I source system. Taking channel 0 as an example, when the system reaches equilibrium, the voltage at the right end of the resistor R1 is 0 V, and assuming that the impedance on the PCB wiring is Rwire, the voltage at the left end of the resistor R1 is

[0074]

[0075] As can be seen from equation (16), due to the influence of the line resistance, the voltage of the resistor R1 will be lower than the output voltage of the PMU. In the PCB design, the sense line of the PMU channel 0 is connected to the pad at the left end of the resistor R1. The sense line feeds back the voltage at the left end of R1 to the PMU chip in real time, so as to adjust the output of the PMU to make the voltage at the left end of R1 be the preset voltage. In summary, using the PMU chip supporting Kelvin output can improve the precision and consistency of the system. In addition, since the PMU chip usually integrates multiple channels, the integration degree of the system can be improved. It should be noted that, in addition to using the PMU chip, the parameter measurement unit 10 can also use a high-precision multi-channel DPS or DAC chip supporting Kelvin output.

[0076] The positive power module 41 can use a positive power DC-DC converter (DCDC+) to provide a positive power supply for the power amplifier U1, Figure 5 The positive power DC-DC converter of the embodiment is shown in the schematic diagram. The circuit mainly consists of an LM5118 chip, an inductor, a diode, a MOSFET, and resistors and capacitors. Since the output voltage range of the power amplifier U1 is wide, and the power supply voltage is fixed, a large voltage difference between the power supply end and the output end will result in low output efficiency and limited output current range. To improve the output current and efficiency of the power amplifier U1, the system uses channel 3 of the PMU chip to adjust the output voltage of the positive power DC-DC converter, so that the output voltage of the positive power DC-DC converter and the output voltage of the power amplifier U1 maintain a small voltage difference. Assuming that the output voltage of the positive power DC-DC converter is Vout, the voltage of the FB pin is Vfb, and the voltage of channel 3 of the PMU chip is Vpmu3, then

[0077]

[0078] where Vfb = 1.23V, R51 = 10K, R52 = 5.1K, R53 = 2K, and after rearrangement,

[0079] Vout = 9.79 - 5*Vpmu3

[0080] The output voltage of the PMU chip is ±11.25V, so the maximum output voltage of the positive power DC-DC converter is 66.04V. Therefore, according to the output needs of the power amplifier U1, the output voltage of the positive power DC-DC converter can be adjusted to obtain a wide range of voltage and current, and at the same time improve the efficiency of the V / I source system.

[0081] The negative power module 42 can use a negative power DC-DC converter (DCDC-), Figure 6 The negative power DC-DC converter of the embodiment is shown in the schematic diagram. The circuit mainly consists of a TPS54360 chip, an inductor, a diode, and resistors and capacitors.

[0082] In some embodiments, the current sampling circuit 31 includes a sampling resistor Rsense and an operational amplifier U2, as shown in Figure 3 The positive end of the sampling resistor Rsense is connected to the output end of the power amplifier U1 and the non-inverting input end of the operational amplifier U2, respectively, the negative end of the sampling resistor Rsense is connected to the inverting input end of the operational amplifier U2, and the output end of the operational amplifier U2 is connected to the input end of the mode selector 60.

[0083] In some embodiments, as shown in Figure 7As shown, the current sampling circuit 31 further comprises an operational amplifier U21, a resistor R21 and a resistor R22, the output terminal of the operational amplifier U2 is connected to the non-inverting input terminal of the operational amplifier U21, the inverting input terminal of the operational amplifier U21 is connected to ground through the resistor R21, one end of the resistor R22 is connected to the inverting input terminal of the operational amplifier U21, and the other end of the resistor R22 is connected to the output terminal of the operational amplifier U21 and the input terminal of the mode selector 60 respectively.

[0084] In some embodiments, as Figure 8 As shown, the voltage sampling circuit 32 comprises an operational amplifier U3, an operational amplifier U31, an operational amplifier U32, a resistor R31, a resistor R32 and a resistor R33, the non-inverting input terminal of the operational amplifier U31 is connected to the power input terminal of the DUT, the inverting input terminal of the operational amplifier U31 is connected to the output terminal thereof, the output terminal of the operational amplifier U31 is connected to the non-inverting input terminal of the operational amplifier U3 through the resistor R1, the non-inverting input terminal of the operational amplifier U32 is connected to the ground terminal of the DUT, the inverting input terminal of the operational amplifier U32 is connected to the output terminal thereof, the output terminal of the operational amplifier U32 is connected to the inverting input terminal of the operational amplifier U3 and one end of the resistor R33 through the resistor R32 respectively, and the other end of the resistor R33 is connected to the output terminal of the operational amplifier U3 and the input terminal of the mode selector 60 respectively. The operational amplifier U31 is a high-voltage amplifier, which functions to collect the power voltage at the DUT terminal. The inverting input terminal and the output terminal thereof are connected, thereby forming a buffer with a gain of 1. Since the DUT is connected to the non-inverting input terminal, the input impedance of this path is very high, and the voltage at the DUT is hardly affected. The high-voltage amplifier used in this embodiment is LTC6090. The operational amplifier U32 is a low-voltage amplifier, which functions to collect the ground voltage at the DUT terminal. The inverting input terminal and the output terminal thereof are connected, thereby forming a buffer with a gain of 1. Since the DUT is connected to the non-inverting input terminal, the input impedance of this path is very high, and the voltage at the DUT is hardly affected. The low-voltage amplifier used in this embodiment is OPA141 chip. The operational amplifier U3 is a low-voltage amplifier, which, together with the resistors R31, R32 and R33, forms a differential amplifier, which functions to subtract the voltages collected by the operational amplifier U31 and the operational amplifier U32, so as to feed back the "absolute" differential voltage at the DUT terminal to the power amplifier U1 or the clamping circuit 50. The operational amplifier U3 used in this embodiment is OPA141 chip.

[0085] The power amplifier U1 is the core of the V / I source, which is used as an amplifier for operation processing such as summation and integration, and is also used as a driver for voltage and current output of the V / I source. In the embodiment, the power amplifier U1 is an OPA541 chip produced by TI. In the embodiment, the non-inverting input terminal of the OPA541 is connected to the ground, the inverting input terminal of the OPA541 is connected to the right end of the resistor R3 and the output terminal of the compensation capacitor selector M3. The output terminal of the OPA541 is connected to the right end of the four compensation capacitors C1-C4, and is connected to the left end of the sampling resistor Rsense. Overall, the PMU chip channel 0, the current sampling circuit 31, the voltage sampling circuit 32, the mode selector 60 and the clamping circuit 50 form a feedback network, which is connected to the inverting input terminal and the output terminal of the power amplifier U1, and forms a non-inverting summation circuit with the power amplifier U1. The input and output relationship is shown in equations (14) and (15). Locally, the OPA541 and the compensation circuit 20 form an integration circuit, which can adjust the output build-up time of the V / I source to adapt to different capacitive loads.

[0086] Therefore, the V / I source system with a wide voltage and current range is built based on the PMU chip + power amplifier U1 + DC-DC converter architecture, and has the following advantages:

[0087] Firstly, the performance of the V / I source system is excellent, and the test quality can be improved while the test cost is reduced. (1) The voltage and current range is wide. In the embodiment, the voltage can reach-20V-+50V, and the current can reach-5A-+5A. By changing the conditions of the positive power DC-DC converter or replacing the power amplifier U1, a wider range of voltage and current can be obtained. (2) The output stable time is small. As shown in Table 1, when driving a 10uF load capacitor, the stable time of outputting a 50V voltage is only 200us; when driving a 1uF load capacitor, the stable time is only 15us; the V / I source system can be applied to scenarios requiring fast response, and the chip test time can be reduced.

[0088] Secondly, the V / I source system has high integration, and the test cost can be reduced. (1) An integrated high-power power amplifier U1 and a DC-DC converter chip are used as the driving source of the system. Compared with the corresponding discrete power amplifier U1 and DC-DC scheme, the V / I source system needs fewer devices. (2) One power amplifier U1 is used to realize the functions of summation, integration and driving circuits. The power amplifier U1 is used as the output driver of the V / I source system, and at the same time, the power amplifier U1 is used as the main amplifier of the negative feedback system to perform the "summation" operation. In addition, the power amplifier U1 is also the main amplifier of the integration circuit. In the conventional scheme, one operational amplifier is needed for the summation, integration and driving circuits. (3) A multi-channel PMU chip is used as a voltage regulator. Only one PMU chip is needed to complete the VI source output setting, clamping setting and DCDC voltage setting.

[0089] It is easily understood by those skilled in the art that the above-mentioned preferred modes can be combined and superimposed freely without conflict.

[0090] The above merely describes the preferred embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation made according to the content of the present application specification and drawings, or direct or indirect application in other related technical fields under the inventive concept of the present application is included in the patent protection scope of the present application.

Claims

1. A wide voltage current range (V / I) source system, characterized in that, The application relates to a power amplifier U1, a parameter measurement unit (10), a compensation circuit (20), a current sampling circuit (31), a voltage sampling circuit (32), a positive power supply module (41), a clamping circuit (50) and a mode selector (60); the positive power supply module (41) is connected with a positive power supply end of the power amplifier U1; the parameter measurement unit (10) has multiple channels for setting output voltage / output current of the power amplifier U1, clamping voltage / clamping current of the clamping circuit (50) and output voltage of the positive power supply module (41) respectively; the compensation circuit (20) can adapt to different capacitive loads for adjusting the setting time of output voltage / output current of the power amplifier U1, and an output end of the power amplifier U1 supplies power for a DUT; the current sampling circuit (31) is used for collecting output current of the power amplifier U1 and feeding back current collection signals to the mode selector (60); the voltage sampling circuit (32) is used for collecting output voltage of the power amplifier U1 and feeding back voltage collection signals to the mode selector (60); in an FV mode, the mode selector (60) selects the voltage collection signals to feed back to the power amplifier U1 and selects the current collection signals to feed back to the clamping circuit (50); in an FI mode, the mode selector (60) selects the current collection signals to feed back to the power amplifier U1 and selects the voltage collection signals to feed back to the clamping circuit (50); the compensation circuit (20) comprises a resistor R3, multiple capacitors and a compensation capacitor selector M3, input ends of the compensation capacitor selector M3 are connected with one ends of the multiple capacitors respectively, an output end of the compensation capacitor selector M3 is connected with the resistor R3 and an inverting input end of the power amplifier U1 respectively, the other ends of the multiple capacitors are connected with output ends of the power amplifier U1 respectively, and different capacitive loads are adapted by switching corresponding capacitors through the compensation capacitor selector M3; wherein the current sampling circuit (31), the voltage sampling circuit (32), the mode selector (60) and the clamping circuit (50) form a feedback network, the feedback network is connected with the inverting input end and the output end of the power amplifier U1 and forms an inverting summing circuit with the power amplifier U1; the compensation circuit (20) forms another feedback network, the feedback network is connected with the inverting input end and the output end of the power amplifier U1 and forms an integral circuit with the power amplifier U1. The application further comprises a negative power supply module (42), and the negative power supply module (42) is connected with a negative power supply end of the power amplifier U1. ​ ​ 2. The wide voltage current range V / I source system of claim 1, wherein: ​ 3. The wide voltage current range V / I source system of claim 1, wherein: The parameter measurement unit (10) adopts PMU chip, DPS or DAC chip, the parameter measurement unit (10) includes channel 0, channel 1, channel 2 and channel 3, the channel 0 of the parameter measurement unit (10) is connected with the input end of the power amplifier U1, the channel 1 of the parameter measurement unit (10) is connected with the negative input end of the clamping circuit (50), the channel 2 of the parameter measurement unit (10) is connected with the positive input end of the clamping circuit (50), and the channel 3 of the parameter measurement unit (10) is connected with the input end of the positive power supply module (41).

4. The wide voltage current range V / I source system of claim 1, wherein: The mode selector (60) includes voltage / current drive mode selector M1, the input end of the voltage / current drive mode selector M1 is connected with the output end of the current sampling circuit (31) and the output end of the voltage sampling circuit (32) respectively, and the output end of the voltage / current drive mode selector M1 is connected with the input end of the power amplifier U1; in FV mode, the voltage / current drive mode selector M1 selects the voltage collection signal to feed back to the power amplifier U1, and in FI mode, the voltage / current drive mode selector M1 selects the current collection signal to feed back to the power amplifier U1.

5. The wide voltage current range V / I source system of claim 1, wherein: The mode selector (60) includes current / voltage clamping mode selector M2, the input end of the current / voltage clamping mode selector M2 is connected with the output end of the current sampling circuit (31) and the output end of the voltage sampling circuit (32) respectively, and the output end of the current / voltage clamping mode selector M2 is connected with the input end of the power amplifier U1; in FV mode, the current / voltage clamping mode selector M2 selects the current collection signal to feed back to the clamping circuit (50), and in FI mode, the current / voltage clamping mode selector M2 selects the voltage collection signal to feed back to the clamping circuit (50).

6. The wide voltage current range V / I source system of claim 1, wherein: The current sampling circuit (31) includes sampling resistor Rsense and operational amplifier U2, the positive end of the sampling resistor Rsense is connected with the output end of the power amplifier U1 and the noninverting input end of the operational amplifier U2 respectively, the negative end of the sampling resistor Rsense is connected with the inverting input end of the operational amplifier U2, and the output end of the operational amplifier U2 is connected with the input end of the mode selector (60).

7. The wide voltage current range V / I source system of claim 1, wherein: The current sampling circuit (31) further includes operational amplifier U21, resistor R21 and resistor R22, the output end of the operational amplifier U2 is connected with the noninverting input end of the operational amplifier U21, the inverting input end of the operational amplifier U21 is connected with the ground through the series connection resistor R21, one end of the resistor R22 is connected with the inverting input end of the operational amplifier U21, and the other end of the resistor R22 is connected with the output end of the operational amplifier U21 and the input end of the mode selector (60) respectively.

8. The wide voltage current range V / I source system of claim 1, wherein: The voltage sampling circuit (32) comprises an operational amplifier U3, an operational amplifier U31, an operational amplifier U32, a resistor R31, a resistor R32, a resistor R33, the non-inverting input terminal of the operational amplifier U31 is connected to the power input terminal of the DUT, the inverting input terminal of the operational amplifier U31 is connected to its output terminal, the output terminal of the operational amplifier U31 is connected to the non-inverting input terminal of the operational amplifier U3 through the series connection of the resistor R1, the non-inverting input terminal of the operational amplifier U32 is connected to the ground terminal of the DUT, the inverting input terminal of the operational amplifier U32 is connected to its output terminal, the output terminal of the operational amplifier U32 is connected to the inverting input terminal of the operational amplifier U3 and one end of the resistor R33 through the series connection of the resistor R32, the other end of the resistor R33 is connected to the output terminal of the operational amplifier U3 and the input terminal of the mode selector (60) respectively.

9. The wide voltage current range V / I source system of claim 1, wherein: The mode selector (60) adopts an analog switch.

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