Generation device for reducing digital signal phase noise
By using real-time phase accumulator and Cordic real-time waveform calculation module in the digital signal generation device, the phase intervals are divided and segmented processing is performed, and the problem of high phase noise of the digital signal is solved, and signal quality improvement and system efficiency optimization are achieved.
Patent Information
- Application Number
- CN202411967842.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-05-13
AI Technical Summary
The phase noise of digital signals is high, affecting the signal quality in the fields of communications, radar, etc.
The real-time phase accumulator and the Cordic real-time waveform calculation module are used to divide the real-time phase values into zero-crossing intervals and peak intervals, and Cordic real-time waveform calculation and comprehensive waveform storage are performed respectively, and the low-phase noise is outputted through high-speed large-bit wide DAC.
It achieves a 40% improvement in phase noise performance, and the phase noise is better than -140dBc/Hz under 1MHz carrier, reducing system noise by 30%, meeting high-end application needs, and reducing system complexity by 50% and power consumption by 40%.
Smart Images
Figure CN119987482A_ABST
Abstract
Description
Technical Field
[0001] This document relates to the field of signal generation technology, and in particular to a generation device for reducing the phase noise of a digitized signal. Background Art
[0002] With the rapid development of science and technology, signal generation technology has gradually evolved from the initial analog generation methods such as LC oscillation circuits and phase-locked loop circuits (PLL) to digital generation methods such as direct digital frequency synthesis (Direct Digital Synthesizer) and digital arbitrary waveform generation (Digital Arbitrary Waveform Generator). It is widely used in various high-tech fields such as communication, computing, radar, and control. It has become the mainstream of current signal generation methods and represents the digital age.
[0003] In the field of signal generation, the characteristics and quality level of a signal are usually described by multiple index parameters, including frequency accuracy, power accuracy, signal-to-noise ratio, spurious-free dynamic range, phase noise, etc. Each index usually affects the working quality of the signal in a certain field. For example, the frequency accuracy index affects the time accuracy in the timing field, and the spurious-free dynamic range index affects the detection range of the radar system. Among these indicators, the phase noise index represents the random fluctuations of the signal phase, which affects the transmission quality and channel capacity in the communication field, and affects the target detection capability and reduces the anti-interference performance in the radar field. It is a very important indicator and measures need to be taken to control and reduce it.
[0004] Therefore, it is necessary to provide a generation device for reducing the phase noise of a digital signal, which can reduce the phase noise of the generated signal while having the advantages of digital signal generation, so as to meet the demand for low phase noise in many application fields such as communication, radar, and testing. Summary of the invention
[0005] The present specification provides a generation device for reducing the phase noise of a digitized signal, so as to solve the problem of high phase noise of a digitized generated signal.
[0006] The present invention provides a generating device for reducing phase noise of a digitized signal, the generating device comprising:
[0007] A real-time phase accumulator is configured to receive a set phase step value and obtain a real-time phase value of a generated signal by a phase equal step accumulation method;
[0008] The phase-amplitude conversion unit includes a Cordic real-time waveform calculation module and a comprehensive waveform storage module, which are configured to divide the phase interval of a complete cycle consisting of the real-time phase value emitted by the real-time accumulator into a zero-crossing interval and a peak interval, and perform Cordic real-time waveform calculation and comprehensive waveform storage respectively;
[0009] A high-speed, large-bitwidth DAC configured to convert signals obtained from Cordic's real-time waveform calculation and integrated waveform storage to obtain a digitally generated signal with low phase noise.
[0010] Furthermore, for the phase interval of a complete cycle formed by the real-time phase value emitted by the real-time accumulator:
[0011] The zero-crossing interval is the area where the signal amplitude change rate is greater than or equal to the set threshold, -30°≤zero-crossing interval range≤30°, or 150°≤zero-crossing interval range≤210°;
[0012] The peak interval is the area where the signal amplitude change rate is less than the set threshold, 30°<peak interval range<150°, or 210°<peak interval range<330°.
[0013] Furthermore, when the real-time phase value is located in the zero-crossing interval, a Cordic real-time waveform calculation module is used to perform Cordic real-time waveform calculation.
[0014] Furthermore, the Cordic real-time waveform calculation includes:
[0015] Convert the 32-bit real-time phase value into an initial vector and a target angle; the abscissa of the initial vector is the compensation coefficient, the ordinate is zero, and the target angle is the real-time phase value;
[0016] Coordinate rotation calculation is performed according to the preset number of iterations, each iteration includes vector rotation and angle update, and the target cosine and sine values of the signal are obtained.
[0017] Furthermore, the zero-crossing interval is divided into two parts, the area within the range of -5°≤zero-crossing interval≤5° is a high-precision area, and the rest are standard-precision areas.
[0018] Furthermore, before the coordinate rotation calculation, the initial vector is preprocessed:
[0019] When in the high-precision area, the initial vector is rotated to the nearest reference angle of the target angle based on a pre-rotation parameter; the pre-rotation parameter is a preset parameter including an initial abscissa value and an initial ordinate value;
[0020] When in the standard precision region, no preprocessing of the initial vector is performed.
[0021] Furthermore, in the coordinate rotation calculation, a dynamic bit width control mechanism is introduced in its iteration:
[0022] When in the high-precision area, 32-bit full-precision calculation is used to execute the preset first number of iterations;
[0023] When in the standard precision area, 24-bit precision calculation is used to perform the second number of iterations.
[0024] The preset first iteration number is greater than the preset second iteration number.
[0025] Furthermore, the coordinate rotation calculation also includes an error detection module after each iteration;
[0026] The error detection module is configured to calculate the error between the current iteration result and the target expected value, and when the error is less than a preset threshold, the next iteration is not performed.
[0027] Furthermore, when the real-time phase value is located in the peak interval, the comprehensive waveform is stored through the comprehensive waveform storage module.
[0028] Furthermore, the comprehensive waveform storage includes:
[0029] The 32-bit real-time phase value is divided into high 16 bits and low 16 bits. The high 16 bits are used as the address of the waveform memory, and the low 16 bits are used for data interpolation calculation.
[0030] The two adjacent stored data are obtained by searching the address corresponding to the upper sixteen bits, and linear interpolation is performed according to the phase value corresponding to the lower sixteen bits to obtain the target waveform amplitude value of the signal.
[0031] At least one of the above technical solutions adopted in the embodiments of this specification can achieve the following beneficial effects:
[0032] (1) Accuracy improvement effect: The 32-bit phase control combined with the segmented processing solution avoids the phase truncation problem in the traditional solution. The phase accuracy is guaranteed by 16-level Cordic operation in the zero-crossing area, and high-precision waveform storage is used in the peak area, which improves the overall phase noise performance by 40%. The phase noise is better than -140dBc / Hz at 1MHz carrier.
[0033] (2) Resource optimization effect: The regional division processing strategy is adopted, and waveform storage is used only in the peak area. The storage depth is reduced to 4096 points, saving 95% of storage resources compared with the traditional full-cycle storage solution. The zero-crossing area adopts a pipeline structure, which occupies less resources and has a processing delay of only 20 clock cycles, greatly improving system efficiency.
[0034] (3) Comprehensive performance: Through high-speed, large-bit-width DAC output, a 4GHz signal bandwidth is achieved, and the dynamic range reaches 85dB. The differential output method combined with low-pass filtering makes the common-mode rejection ratio reach 65dB, and the system noise is reduced by 30%, meeting the needs of high-end applications. Compared with traditional solutions, while maintaining high accuracy, the system complexity is reduced by 50% and the power consumption is reduced by 40%. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0036] Figure 1 A schematic diagram of the composition of a generating device for reducing phase noise of a digital signal provided in an embodiment of this specification;
[0037] Figure 2 A schematic diagram of a DDS internal phase step accumulator provided in an embodiment of this specification;
[0038] Figure 3 A schematic diagram of the real-time phase value output by the internal phase accumulation of the DDS provided in an embodiment of this specification. DETAILED DESCRIPTION
[0039] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.
[0040] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.
[0041] Figure 1 A schematic diagram of a device for reducing phase noise of a digital signal provided in an embodiment of this specification is shown in FIG. Figure 1 , the generating device comprises:
[0042] The real-time phase accumulator is configured to receive the set phase step value and obtain the real-time phase value of the generated signal by phase equal step accumulation.
[0043] The real-time phase accumulator is a DDS module implemented based on FPGA. The DDS module is the core of digital signal generation. Figure 2, is a schematic diagram of a DDS internal phase step accumulator provided in an embodiment of the present specification, receiving a set phase step value, and obtaining a phase step value by a phase equal step accumulation method. Figure 3 The real-time phase value of the DDS internal phase accumulation output shown is the real-time phase value of the generated signal.
[0044] The phase-amplitude conversion unit includes a Cordic real-time waveform calculation module and a comprehensive waveform storage module, which are configured to divide the phase interval of a complete cycle consisting of the real-time phase value emitted by the real-time accumulator into a zero-crossing interval and a peak interval, and perform Cordic real-time waveform calculation and comprehensive waveform storage respectively.
[0045] The phase step value affects the frequency resolution index of the output signal, so the main development direction is to make the bit width wider. The current mainstream phase step value bit width is 32 bits and above. To obtain the waveform of the output signal, the real-time phase value needs to be converted into the real-time amplitude value of the signal to form a waveform, which is called phase-amplitude conversion. This is the key to affecting the phase noise of the output signal. The traditional phase-amplitude conversion is implemented by waveform storage, that is, the waveform amplitude data of a complete cycle is stored in the memory, the real-time phase value is used as the address to query the amplitude value corresponding to the phase, and then the output is read to generate the waveform.
[0046] However, in the actual implementation, the real-time phase value has a bit width of up to 32 bits or more while ensuring the frequency resolution, and the corresponding waveform memory capacity must be 2 32 , that is, the storage depth of 4Gs, and the bit width of each waveform amplitude data is 16 bits, which ultimately requires 8GB of storage capacity, which is very difficult to achieve in a digital system. Therefore, the traditional method is to reduce the width of the real-time phase value. On the premise that the bit width of the previous phase accumulator remains unchanged to ensure the frequency resolution, the output real-time phase value is truncated to reduce the difficulty of waveform storage. This operation is called phase truncation, which directly leads to the deterioration of phase accuracy and increases the phase noise of the output signal.
[0047] The present invention divides the phase interval of a complete cycle formed by the real-time phase value emitted by the real-time accumulator into a zero-crossing interval and a peak interval:
[0048] The zero-crossing interval is the area where the signal amplitude change rate is greater than or equal to the set threshold, -30°≤zero-crossing interval range≤30°, or 150°≤zero-crossing interval range≤210°.
[0049] The peak interval is the area where the signal amplitude change rate is less than the set threshold, 30°<peak interval range<150°, or 210°<peak interval range<330°.
[0050] The present invention adopts a comprehensive processing method combining waveform storage and Cordic real-time calculation, adopts a segmented processing method, uses Cordic real-time calculation in the signal zero-crossing area, and performs phase-amplitude conversion calculation without phase truncation on the 32-bit real-time phase value; uses waveform storage in the signal smooth peak range to find the corresponding amplitude output of the real-time phase value. While avoiding the problem of poor real-time calculation accuracy near the signal smooth peak, it also avoids the problem of excessive storage capacity of the entire cycle waveform. After comprehensive balancing, the real-time phase without truncation phase-amplitude conversion operation within the full waveform period can be obtained, which greatly reduces the phase noise of the output signal.
[0051] The full name of the Cordic algorithm is the Coordinate Rotation Digital Computer. It is a method based on iterative operations to implement various mathematical operations such as trigonometric functions, exponential functions, and logarithmic functions. Through a series of fixed-angle rotation operations, it gradually approaches the required calculation results. During the "phase-amplitude conversion", the full width of the phase value calculated in real time is used to input the Cordic algorithm module. By lengthening the number of rotation approximation calculations of the Cordic algorithm, the calculation accuracy under large bit width is improved to ensure that the amplitude accuracy is not lower than the traditional waveform storage method. This method has been found in engineering practice to be suitable for the calculation of steep waveforms, and the calculation accuracy is sufficient before and after the signal crosses the zero point, but it is not suitable for the calculation of smooth waveforms, and the calculation accuracy is poor near the smooth peak of the signal.
[0052] When the real-time phase value is in the zero-crossing interval, a Cordic real-time waveform calculation module is used to perform Cordic real-time waveform calculation, including:
[0053] Convert the 32-bit real-time phase value into an initial vector and a target angle; the abscissa of the initial vector is the compensation coefficient, the ordinate is zero, and the target angle is the real-time phase value;
[0054] Coordinate rotation calculation is performed according to the preset number of iterations, each iteration includes vector rotation and angle update, and the target cosine and sine values of the signal are obtained.
[0055] Vector rotation is achieved through shifting and addition and subtraction operations, and angle update is completed by looking up the pre-stored basic angle table. After twenty iterative operations, the horizontal and vertical coordinate values of the final vector are obtained, which are the target cosine and sine values of the required signal.
[0056] Furthermore, the present invention further divides the zero-crossing interval into two parts, the part with a range of -5°≤zero-crossing interval≤5° is a high-precision area, and the rest is a standard-precision area.
[0057] Before the coordinate rotation calculation, the initial vector is preprocessed according to whether the phase value is in the high-precision area or the standard-precision area:
[0058] When in the high-precision area, the initial vector is rotated to the nearest reference angle of the target angle based on the pre-rotation parameters to reduce the angular deviation of subsequent iterations; the pre-rotation parameters are preset parameters including initial horizontal coordinate values and initial vertical coordinate values, that is, the pre-rotation is implemented by table lookup, storing several groups of preset rotation parameters, including initial horizontal coordinate values and vertical coordinate values.
[0059] When in the standard precision region, no preprocessing of the initial vector is performed.
[0060] Coordinate rotation calculation, the dynamic bit width control mechanism is introduced in its iteration:
[0061] When in the high-precision area, 32-bit full-precision calculation is used to perform a preset first number of iterations. In one embodiment of the present invention, the preset first number of iterations is 24;
[0062] When in the standard precision area, 24-bit precision calculation is used to perform a preset second number of iterations. In one embodiment of the present invention, the preset second number of iterations is 16;
[0063] The preset first iteration number is greater than the preset second iteration number.
[0064] During each iteration, the data bit width is dynamically adjusted through the shift register to ensure the calculation accuracy of the key bits. At the same time, during the vector rotation process, a pipeline structure is used to process the angle update and vector rotation in parallel.
[0065] In order to improve the computational efficiency, a new angle search mechanism is designed. The basic angle table is divided into a two-level structure of a coarse lookup table and a fine lookup table. The coarse lookup table stores the reference values of larger angle intervals, and the fine lookup table stores the small angle increment values. During the iteration process, the angle range is first quickly located through the coarse lookup table, and then the fine lookup table is used for accurate search to reduce the number of table lookups.
[0066] Coordinate rotation calculation, after each iteration, an error detection module is also set;
[0067] The error detection module is configured to calculate the error between the current iteration result and the target expected value, and when the error is less than a preset threshold, the next iteration is not performed.
[0068] In one embodiment of the present invention, the error threshold is set to 10 in the high precision area. -9 , the standard precision area is set to 10 -7 .
[0069] Finally, a compensation correction mechanism is added to the output link. Due to the use of differentiated iteration strategies, there may be slight accuracy differences in the output results of different accuracy zones. By establishing an accuracy mapping relationship, the output results are calibrated for consistency to ensure a smooth transition of outputs in adjacent areas.
[0070] In order to achieve smooth switching between the two processing methods, a gradual transition mechanism is designed at the interval boundary. When the real-time phase value is in the transition area, the Cordic result and the storage search result are calculated at the same time, and the final output value is obtained by weighted average. The weight coefficient changes cosine with the position of the phase value in the transition area to ensure the continuity and smoothness of the output waveform.
[0071] In one embodiment of the present invention, when the input phase value is 0°, it is located in the zero-crossing interval, and the output amplitude value obtained by twenty Cordic iterations is zero; when the input phase value is 90°, it is located in the peak interval, and the output amplitude value obtained by waveform storage search is the positive full scale; when the input phase value is 30°, it is located in the transition area, and the Cordic calculation value and the storage search value are weighted averaged with a weight of 0.5 to obtain the final output value.
[0072] When the real-time phase value is within the peak interval, a comprehensive waveform storage module is used to store the comprehensive waveform, including:
[0073] The 32-bit real-time phase value is divided into high 16 bits and low 16 bits. The high 16 bits are used as the address of the waveform memory, and the low 16 bits are used for data interpolation calculation.
[0074] The two adjacent stored data are obtained by searching the address corresponding to the upper sixteen bits, and linear interpolation is performed according to the phase value corresponding to the lower sixteen bits to obtain the target waveform amplitude value of the signal.
[0075] The waveform memory pre-stores 8192 sampling points of sine waveform data, each of which is 16 bits wide. The two adjacent stored data are obtained by searching the high-order address, and then linear interpolation is performed according to the low-order value to obtain the final waveform amplitude value, which is the target waveform amplitude value of the required signal.
[0076] A high-speed, large-bitwidth DAC configured to convert signals obtained from Cordic's real-time waveform calculation and integrated waveform storage to obtain a digitally generated signal with low phase noise.
[0077] The low phase noise waveform data generated digitally in the FPGA needs to be output through the DAC. The traditional method sets the output frequency to within 0.4Fs of the DAC operating clock frequency. At the same time, in order to reduce costs and implementation difficulties, the Fs value is often reduced as much as possible. In fact, at the same output frequency Fo, the higher the DAC operating clock frequency Fs, the better the phase noise of the output signal. At the same time, the amplitude quantization error will also affect the output signal phase noise. Therefore, the present invention uses a DAC with an operating frequency of up to 10GHz and a data bit width of 16bit as a digital-to-analog converter to reduce the phase noise value introduced by the DAC device.
[0078] In summary, the present invention combines the waveform storage type and the Cordic real-time calculation type waveform generation method, as well as a DAC with a 10GHz high speed and a 16-bit data bit width, to obtain a generation device that reduces the phase noise of a digital signal. Compared with the traditional digital signal generation method, the present invention greatly reduces the phase noise level caused by truncation of the phase and amplitude due to digitization, improves the signal generation quality, and has great practical value and progressive significance in various high-tech fields such as communication, computing, radar, and control.
[0079] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims
1. A generating device for reducing phase noise of a digitized signal, characterized in that: The generating device comprises: A real-time phase accumulator is configured to receive a set phase step value and obtain a real-time phase value of a generated signal by a phase equal step accumulation method; The phase-amplitude conversion unit includes a Cordic real-time waveform calculation module and a comprehensive waveform storage module, which are configured to divide the phase interval of a complete cycle consisting of the real-time phase value emitted by the real-time accumulator into a zero-crossing interval and a peak interval, and perform Cordic real-time waveform calculation and comprehensive waveform storage respectively; A high-speed, large-bitwidth DAC configured to convert signals obtained from Cordic's real-time waveform calculation and integrated waveform storage to obtain a digitally generated signal with low phase noise.
2. The device for reducing phase noise of a digital signal according to claim 1, characterized in that: The phase interval of a complete cycle formed by the real-time phase value emitted by the real-time accumulator is divided into a zero-crossing interval and a peak interval: The zero-crossing interval is the area where the signal amplitude change rate is greater than or equal to the set threshold, -30°≤zero-crossing interval range≤30°, or 150°≤zero-crossing interval range≤210°; The peak interval is the area where the signal amplitude change rate is less than the set threshold, 30°<peak interval range<150°, or 210°<peak interval range<330°.
3. The device for reducing phase noise of a digital signal according to claim 1, characterized in that: When the real-time phase value is located in the zero-crossing interval, the Cordic real-time waveform calculation module performs Cordic real-time waveform calculation.
4. The device for reducing phase noise of a digital signal according to claim 3, characterized in that: The Cordic real-time waveform calculation includes: Convert the 32-bit real-time phase value into an initial vector and a target angle; the abscissa of the initial vector is the compensation coefficient, the ordinate is zero, and the target angle is the real-time phase value; Coordinate rotation calculation is performed according to the preset number of iterations, each iteration includes vector rotation and angle update, and the target cosine and sine values of the signal are obtained.
5. The device for reducing phase noise of a digital signal according to claim 4, characterized in that: The zero-crossing interval is divided into two parts: -5°≤zero-crossing interval range≤5° is a high-precision area, and the rest are standard-precision areas.
6. The device for reducing phase noise of a digitized signal according to claim 5, characterized in that: Before the coordinate rotation calculation, the initial vector is preprocessed: When in the high-precision area, the initial vector is rotated to the nearest reference angle of the target angle based on a pre-rotation parameter; the pre-rotation parameter is a preset parameter including an initial abscissa value and an initial ordinate value; When in the standard precision region, no preprocessing of the initial vector is performed.
7. The device for reducing phase noise of a digitized signal according to claim 5, characterized in that: The coordinate rotation calculation introduces a dynamic bit width control mechanism in its iteration: When in the high-precision area, 32-bit full-precision calculation is used to execute the preset first number of iterations; When in the standard precision area, 24-bit precision calculation is used to perform the second number of iterations. The preset first iteration number is greater than the preset second iteration number.
8. The device for reducing phase noise of a digitized signal according to claim 4, characterized in that: The coordinate rotation calculation further includes an error detection module after each iteration; The error detection module is configured to calculate the error between the current iteration result and the target expected value, and when the error is less than a preset threshold, the next iteration is not performed.
9. The device for reducing phase noise of a digitized signal according to claim 1, characterized in that: When the real-time phase value is located in the peak interval, the comprehensive waveform is stored through the comprehensive waveform storage module.
10. The device for reducing phase noise of a digitized signal according to claim 9, characterized in that: The comprehensive waveform storage includes: The 32-bit real-time phase value is divided into high 16 bits and low 16 bits. The high 16 bits are used as the address of the waveform memory, and the low 16 bits are used for data interpolation calculation. The two adjacent stored data are obtained by searching the address corresponding to the upper sixteen bits, and linear interpolation is performed according to the phase value corresponding to the lower sixteen bits to obtain the target waveform amplitude value of the signal.