A cold reset method, system, electronic device and storage medium

Abstract

The present disclosure provides a cold reset method, system, electronic device, and storage medium, relating to the field of computer technologies. A cold reset method includes: any processor on a first control board triggers a cold reset, and a target processor on the first control board obtains reset information of the cold reset; the first control board is a board for controlling all tasks of the system, and the target processor is the same as or different from the processor that triggers the cold reset; the target processor sends the reset information to a reset processor on a second control board; the second control board is a board for executing image processing tasks; the reset processor resets a retimer on the second control board based on the reset information, and the retimer is connected to a graphics processor on the second control board. Thus, it can be ensured that the retimer is reset in a timely manner when the system performs a cold reset, so as to ensure that the retimer reloads the graphics processor connected thereto, avoid loss of the graphics processor, and not affect the normal use of other devices.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a cold reset method, system, electronic device, and storage medium. Background Art

[0002] The rate supported by the Peripheral Component Interconnect Express (PCIe) standard is getting higher and higher. For signal quality, the length limit of PCIe signals is also getting higher. To extend the length of PCIe signal traces and ensure signal quality, a retimer chip is added to the PCIe link. The retimer chip is a graphics processor extender or retimer, which can enhance the transmission quality of PCIe signals in the PCIe link.

[0003] When a server using PCIe for communication between internal components performs a cold reset, the main power on the system does not lose power, but the PCIe reference clock signal (PCIe RECLK) sent by the corresponding processing unit will be interrupted for a certain period of time, resulting in the loss of the Graphics Processing Unit (GPU) on the HGX platform with a retimer connected to the backend. Here, the HGX platform is a GPU-accelerated computing framework.

[0004] Therefore, a solution to the problem of losing the GPU due to retimer anomalies during cold reset is crucial. Summary of the Invention

[0005] The present disclosure provides a cold reset method, system, electronic device, and storage medium to at least solve the above technical problems existing in the prior art.

[0006] According to a first aspect of the present disclosure, a cold reset method is provided, including: any processor on a first control board triggers a cold reset, and a target processor on the first control board obtains reset information of the cold reset; the first control board is a board that controls all tasks of the system, and the target processor is the same as or different from the processor that triggers the cold reset; the target processor sends the reset information to a reset processor on a second control board; the second control board is a board that executes image processing tasks; the reset processor resets a retimer on the second control board based on the reset information, and the retimer is connected to a graphics processor on the second control board.

[0007] In an implementable embodiment, any processor on the first control board triggering a cold reset includes: any processor on the first control board triggering a cold reset and sending the reset information of the cold reset to a first signal controller on the first control board; the first signal controller storing the reset information in a register in the first signal controller and generating a prompt signal, and sending the prompt signal to the target processor.

[0008] In an implementable embodiment, the target processor on the first control board obtaining the reset information of the cold reset includes: the target processor, in response to the prompt signal, reading the reset information in the register through an internal integrated circuit bus.

[0009] In an implementable embodiment, a cold reset method further includes: the first signal controller, in response to the target processor having read the reset information, clearing the reset information from the register.

[0010] In an implementable embodiment, the processor triggering the cold reset is a first processor, and the first processor is different from the target processor. The sending the reset information of the cold reset to the first signal controller on the first control board includes: the first processor sending the reset information of the cold reset to the first signal controller through a general-purpose input / output interface.

[0011] In an implementable embodiment, the processor triggering the cold reset is a second processor, and the second processor is the same as the target processor. The sending the reset information of the cold reset to the first signal controller on the first control board includes: the second processor sending the reset information of the cold reset to the first signal controller through a hardware reset signal.

[0012] In an implementable embodiment, the target processor sending the reset information to a reset processor on a second control board includes: the target processor sending the reset information to the reset processor on the second control board through a universal serial bus.

[0013] In an implementable embodiment, the reset processor resetting a retimer on the second control board based on the reset information includes: the reset processor, in response to the reset information, pulling down an enable signal of the retimer to a first level and pulling up the enable signal to a second level after a first target duration, so that the retimer completes the reset; the first level is less than the second level.

[0014] In an implementable embodiment, after the target processor reads the reset information in the register via the internal integrated circuit bus in response to the prompt signal, the method further includes: in response to the target processor being unable to read the reset information in the register, the first signal controller sends the reset information to a second signal controller on a third control board; the third control board is a board for signal exchange; the second signal controller resets the second control board based on the reset information.

[0015] In an implementable embodiment, the second signal controller resets the second control board based on the reset information, including: the second signal controller pulls down the power enable signal of the second control board to a third level in response to the reset information, and raises the power enable signal to a fourth level after a second target duration to cause the second control board to complete the reset; the third level is less than the fourth level.

[0016] In an implementable embodiment, after any processor on the first control board triggers a cold reset, the method further includes: in response to the target processor being unable to obtain the reset information of the cold reset, the target processor generates a warning message and displays the warning message; the warning message is used to indicate that the cold reset is not completed.

[0017] According to a second aspect of the present disclosure, there is provided a cold reset system, including: a first control board, the first control board is a board for controlling all tasks of the system, including at least two processors; any one of the at least two processors is used to trigger a cold reset, and a target processor among the at least two processors is used to obtain the reset information of the cold reset and send the reset information to a reset processor on a second control board, the target processor is the same as or different from the processor that triggers the cold reset; a second control board, the second control board is a board for performing image processing tasks, including a reset processor, a retimer, and a graphics processor, the retimer is connected to the graphics processor on the second control board; the reset processor is used to reset the retimer on the second control board based on the reset information.

[0018] In an implementable embodiment, the first control board further includes a first signal controller; any one of the at least two processors is used to trigger a cold reset and send the reset information of the cold reset to the first signal controller on the first control board; the first signal controller is used to store the reset information in a register in the first signal controller and generate a prompt signal, and send the prompt signal to the target processor.

[0019] In one implementable manner, the target processor is further configured to: in response to the prompt signal, read the reset information from the register through an internal integrated circuit bus.

[0020] In one implementable manner, the first signal controller is further configured to: in response to the target processor having read the reset information, clear the reset information from the register.

[0021] In one implementable manner, among the at least two processors, there is a first processor, and the first processor is configured to send the reset information of the cold reset to the first signal controller through a general-purpose input / output interface.

[0022] In one implementable manner, among the at least two processors, there is a second processor, and the second processor is configured to send the reset information of the cold reset to the first signal controller through a hardware reset signal.

[0023] In one implementable manner, the target processor is further configured to: send the reset information to a reset processor on a second control board through a universal serial bus.

[0024] According to a third aspect of the present disclosure, there is provided an electronic device, including the cold reset system of the present disclosure, and the cold reset system is capable of executing the cold reset method of the present disclosure.

[0025] According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, and the computer instructions are used to cause a computer to execute the method of the present disclosure.

[0026] For a cold reset method, system, electronic device, and storage medium of the present disclosure, if any processor on a first control board triggers a cold reset, a target processor on the first control board obtains the reset information of the cold reset, and the target processor is the same as or different from the processor that triggers the cold reset. Then, the target processor sends the reset information to a reset processor on a second control board, and the reset processor resets a retimer on the second control board based on the reset information. The retimer is connected to a graphics processor on the second control board. Thus, after a cold reset occurs on the first control board, the target processor on the first control board obtains the reset information of the cold reset and directly sends the reset information to the reset processor on the second control board. The reset processor independently resets the retimer on the second control board, so as to ensure that the retimer reloads the graphics processor connected thereto, avoid loss of the graphics processor, and not affect the normal use of other devices.

[0027] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] By referring to the drawings and reading the following detailed description, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0029] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0030] Figure 1 The flowchart of a cold reset method according to an embodiment of the present disclosure is shown; Figure 1 ;

[0031] Figure 2 The flowchart of a cold reset method according to an embodiment of the present disclosure is shown; Figure 2 ;

[0032] Figure 3 The flowchart of a cold reset method according to an embodiment of the present disclosure is shown; Figure 3 ;

[0033] Figure 4 The structural schematic diagram of a cold reset system in the prior art is shown;

[0034] Figure 5 The structural schematic diagram of a cold reset system according to an embodiment of the present disclosure is shown; Figure 1 ;

[0035] Figure 6 The structural schematic diagram of a cold reset system according to an embodiment of the present disclosure is shown; Figure 2 ;

[0036] Figure 7 The structural schematic diagram of the composition of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] In order to make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0038] The speed supported by PCIe is getting higher and higher. For the sake of signal quality, the length limit of PCIe signals is also getting higher. To extend the length of PCIe signal traces and ensure signal quality, a retimer chip is added to the PCIe link. In practical applications, the retimer chip is used to equalize and enhance the transmitted signals. For example, the transmission distance of PCIe 5.0 signals is inherently long, and the use of a retimer chip can make the transmission distance of PCIe 5.0 signals even longer to ensure the quality of PCIe 5.0 signals. When the length of the PCIe link exceeds the length required by the PCIe specification, the role of the retimer is essential.

[0039] The designs of retimer chips from all manufacturers follow the retimer-supplemental-features specification. In this specification, the signals that the retimer chip must use are defined, and there are a small number of additional signals that can be designed by the manufacturers themselves. In the actual design of retimer chips, compatible designs can be made for chips from different manufacturers.

[0040] For some retimer chips, during various verification or testing processes, if a clock interruption (CLK interruption) occurs, the reset signal of the retimer chip needs to be reset once to enable the retimer to work properly. Otherwise, the retimer chip cannot establish a PCIe signal connection. Specifically, when a server using PCIe for inter-component communication performs a cold reset, the main power on the system does not lose power, but the PCIe RECLK signal sent by the corresponding processing unit will be interrupted for a certain period of time, resulting in the loss of GPUs on the HGX platform with retimer chips connected at the back end. Among them, the corresponding processing unit can be a central processing unit (CPU, Central Processing Unit), and the HGX platform is a GPU-accelerated computing framework.

[0041] When a clock interruption occurs in the retimer chip, the retimer chip must be reset once to resume normal operation. However, since the delta-next of the HGX architecture is often a finished product system of GPU manufacturers and does not have external signals reserved, the chip reset signal of the retimer cannot be controlled. Among them, delta-next is a high-performance computing platform that provides users with excellent computing performance and flexible deployment options through powerful GPU configurations and optimized interconnect technologies.

[0042] For the problem of GPU loss caused by retimer anomalies during cold reset, the following methods are generally used to solve it:

[0043] Figure 4 Fig. shows the structural schematic diagram of the cold reset system in the prior art, as Figure 4 shown, the cold reset system includes a motherboard (MB, Motherboard), a Switch board, and an HGX platform. The motherboard includes a CPU, a baseboard management controller (BMC, Baseboard Management Controller), and a complex programmable logic device (CPLD, Complex Programmable Logic Device), that is, the MB CPLD; the Switch board also includes a CPLD. To distinguish it from the CPLD on the motherboard, the CPLD on the Switch board can be called the SW CPLD; the HGX platform includes a field programmable gate array (FPGA, Field Programmable Gate Array), a retimer, and a GPU.

[0044] When a cold reset occurs on the motherboard, it can inform the SW CPLD on the Switch board through the general purpose input / output (GPIO, General Purpose Input / Output) interface. After receiving the reset signal, the SW CPLD pulls down and then raises the base power enable signal (BASE_PWR_EN signal) of the HGX, enabling the HGX to power off and then power on as a whole. At the same time, the retimer also powers off and then powers on, causing the retimer to reload the firmware.

[0045] As Figure 4 shown, the process of resetting the HGX is as follows:

[0046] 1. There are two cases when a cold reset occurs in the system. One is triggered by the basic input / output system (BIOS, Basic Input / Output System), and the other is triggered by the BMC. When triggered by the BIOS, the CPU will execute the trigger instruction of the BIOS, and the CPU will inform the MB CPLD that a cold reset has been triggered through the GPIO1 signal between the CPU and the MB CPLD; when triggered by the BMC, the BMC informs the MB CPLD through a hardware reset signal (such as the SYS_RESET_N signal).

[0047] 2. When the MB CPLD obtains the cold reset signal triggered by the BIOS or the BMC, it informs the SW CPLD of the cold reset signal through the GPIO2 signal between the MB CPLD and the SW CPLD.

[0048] 3. After the SW CPLD obtains the notification signal, it will pull down the BASE_PWR_EN signal of the HGX, enabling the HGX to perform a power-down timing sequence. After pulling it down for 2 seconds, it will release the signal, ensuring that the power-down time of the HGX meets the specification requirements, and then power it on again.

[0049] 4. The Retimer will also power on during the power-up and power-down process of the HGX, reload the firmware, and reload the PCIe link simultaneously, thus avoiding GPU loss.

[0050] However, this method requires that the CPU can notify the MB CPLD, and the MB CPLD can notify the SW CPLD. That is, there need to be reserved signals between the CPU and the MB CPLD, and between the MB CPLD and the SW CPLD. Otherwise, it is impossible to achieve a power-on reset for the HGX, and the motherboard or Switch board needs to be redesigned, wasting time and cost.

[0051] Based on the above disadvantages of the existing cold reset method, the present disclosure proposes a cold reset method, system, electronic device, and storage medium to at least solve the above technical problems existing in the prior art.

[0052] Figure 5 The structure of a cold reset system according to an embodiment of the present disclosure is shown Figure 1 , as Figure 5 shown, a cold reset system includes:

[0053] The first control board 10, which is a board for controlling all tasks of the system, includes at least two processors; any one of the at least two processors is used to trigger a cold reset, and the target processor among the at least two processors is used to obtain the reset information of the cold reset and send the reset information to the reset processor 31 on the second control board 30. The target processor may be the same as or different from the processor that triggers the cold reset;

[0054] The second control board 30, which is a board for performing image processing tasks, includes a reset processor 31, a retimer 32, and a graphics processor 33. The retimer 32 is connected to the graphics processor 33 on the second control board 30; the reset processor 31 is used to reset the retimer 32 on the second control board 30 based on the reset information.

[0055] In this embodiment, the first control board is the board for all tasks of the control system, and the first control board can be the main board; the second control board is the board for executing image processing tasks, and the second control board can be HGX. At least two processors in the first control board 10 can be the first processor 11 and the second processor 12, the target processor can be the second processor 12. After any one of the at least two processors triggers a cold reset, the generated reset information can include the source of the reset event, the type of the reset event, a timestamp or a serial number, the reason for the reset trigger, and system status information, etc. Among them, the source of the reset event can include whether it is triggered by the BIOS or the BMC; the timestamp or the serial number can be used to distinguish different reset events; the reason for the reset trigger can include BIOS setting changes, system exceptions, user operations through the BMC web interface, etc.; the system status information includes power status, device status, etc., which are used for subsequent analysis or processing.

[0056] In this embodiment, if the target processor is the second processor 12, the second processor 12 can obtain the reset information of the cold reset and send the reset information to the reset processor 31 on the second control board 30. The reset processor 31 can reset the retimer 32 (i.e., Retimer) on the second control board 30 based on the reset information. After the retimer 32 is reset, it will reload the firmware and reload the PCIe link at the same time, so as to avoid GPU loss. It should be emphasized that the target processor will send the reset information to the reset processor 31 only when the system triggers a cold reset. If the system triggers a warm reset, it will not obtain the reset information, that is, it will not start the process of resetting the retimer 32.

[0057] In the present disclosure, the target processor (such as the second processor 12) on the first control board 10 will obtain the reset information of the cold reset after a cold reset occurs on the first control board 10, and directly send the reset information to the reset processor 31 on the second control board 30. The reset processor 31 will separately reset the retimer 32 on the second control board 30, so as to ensure that the retimer 32 reloads the graphics processor 33 connected thereto, avoid the loss of the graphics processor, and does not affect the normal use of other devices; in addition, there is no need to reserve signals between the CPU and the MB CPLD, and between the MB CPLD and the SW CPLD, and the retimer 32 can be directly reset, avoiding wasting time and cost.

[0058] In an implementable embodiment, the first control board 10 further includes a first signal controller 13; any one of at least two processors is configured to trigger a cold reset and send the reset information of the cold reset to the first signal controller 13 on the first control board 10; the first signal controller 13 is configured to store the reset information in a register 14 in the first signal controller 13 and generate a prompt signal, and send the prompt signal to the target processor.

[0059] In this embodiment, a register 14 is provided in the first signal controller 13. After any one of at least two processors triggers a cold reset, it will send the reset information to the first signal controller 13. The first signal controller 13 will store the reset information in the register 14 and generate a prompt signal, and send the prompt signal to the target processor. The prompt signal indicates that the reset information has been stored in the register 14 and is used to prompt the target processor to read the reset information in the register 14.

[0060] In an implementable embodiment, the target processor is further configured to: in response to the prompt signal, read the reset information in the register 14 through an internal integrated circuit bus. That is, the target processor can read the reset information from the register 14 through an internal integrated circuit bus (I2C, Inter-Integrated Circuit). I2C is a serial communication protocol applied to electronic devices and is mainly used for short-distance and low-speed communication scenarios.

[0061] In an implementable embodiment, the first signal controller 13 is further configured to: in response to the target processor having read the reset information, clear the reset information from the register 14.

[0062] In this implementable embodiment, a flag bit is provided in the first signal controller 13. The flag bit is used to indicate whether the target processor has read the reset information in the register 14. When the first signal controller 13 stores the reset information in the register 14, it will set the flag bit to "unread". After the target processor reads the reset information from the register 14, it will clear the flag bit or set it to "read". In response to the flag bit being cleared or set to "read", the first signal controller 13 will clear the reset information from the register 14.

[0063] In an implementable embodiment, among at least two processors, there is a first processor 11, and the first processor 11 is configured to send the reset information of the cold reset to the first signal controller 13 through a general-purpose input / output interface. That is, the first processor 11 can send the reset information of the cold reset to the first signal controller 13 through the general-purpose input / output interface GPIO. GPIO is a common hardware interface, which is widely used in devices such as embedded systems, microcontrollers, and computer motherboards. The GPIO interface allows hardware devices to communicate with external circuits through simple digital signals to implement input / output functions.

[0064] In an implementable embodiment, among at least two processors, there is a second processor 12, and the second processor 12 is configured to send the reset information of the cold reset to the first signal controller 13 through a hardware reset signal. That is, the second processor 12 can send the reset information of the cold reset to the first signal controller 13 through hardware reset signals such as SYS_RESET_N and RST_N. Herein, the "N" in hardware reset signals such as SYS_RESET_N and RST_N indicates that this is a signal effective at low level, that is, when the signal is at low level, the system will trigger a reset operation. The SYS_RESET_N signal is a common hardware signal, usually used for system reset operations, while RST_N is usually used for resetting specific devices or modules.

[0065] In an implementable embodiment, the target processor is further configured to: send the reset information to the reset processor 31 on the second control board 30 through a universal serial bus. That is, the target processor can send the reset information to the reset processor 31 on the second control board 30 through the universal serial bus (USB, Universal Serial Bus).

[0066] In an implementable embodiment, the reset processor 31 is further configured to: in response to the reset information, pull down the enable signal of the retimer 32 to a first level, and after a first target duration, pull up the enable signal to a second level, so that the retimer 32 completes the reset; the first level is less than the second level.

[0067] In the present implementable embodiment, after the reset processor 31 responds to the received reset information, it will parse the reset information to determine the operation that needs to be executed as indicated by the reset information. For example, if the reset processor 31 parses that the reset information indicates that the re-timer 32 needs to be reset, it will pull down the enable signal of the re-timer 32 to the first level, that is, the low level, usually 0V or grounded, to make the re-timer 32 enter the reset state and maintain this state for the first target duration, such as 1 second, to ensure that the re-timer 32 is fully reset, and then pull up the enable signal of the re-timer 32 to the second level, that is, the high level, usually 3.3V or 5V, to power on the re-timer 32 again, thereby completing the reset. Among them, it is possible to determine whether the first target duration is reached through the timer or counter inside the FPGA.

[0068] After the enable signal of the re-timer 32 is pulled up to the second level, the re-timer 32 will be powered on again. At this time, the internal circuit of the re-timer 32 will be re-initialized, all registers and status information will be cleared, and the re-timer 32 will re-load the firmware. The firmware usually includes the device driver and configuration parameters, and will also check the hardware status to ensure the normal operation of the device.

[0069] After the re-timer 32 re-loads the firmware, it will attempt to re-establish the PCIe link. This process includes: detecting the integrity of the PCIe signal; re-establishing the connection with other devices (such as CPU, GPU, etc.) on the PCIe bus; setting the relevant parameters of the PCIe link according to the configuration parameters in the firmware, including parameters such as rate and width; verifying whether the link works properly to ensure the reliability of data transmission. Thus, GPU loss can be avoided.

[0070] In an implementable embodiment, a cold reset system further includes a third control board 20. The first signal controller 13 is further configured to: send the reset information to the second signal controller 21 on the third control board 20. The third control board 20 is a board card used for signal exchange; the second signal controller 21 is configured to reset the second control board 30 based on the reset information.

[0071] In the present feasible embodiment, the third control board 20 is disposed between the first control board 10 and the second control board 30 and is used for signal exchange between the first control board 10 and the second control board 30, so as to achieve efficient data transmission between the first control board 10 and the second control board 30. The third control board 20 includes a second signal controller 21. If the target processor cannot read the reset information in the register, for example, the I2C bus connection between the target processor and the register 14 is poor, short-circuited or open-circuited, and the BMC is damaged or misconfigured, etc., the first signal controller 13 will send the reset information to the second signal controller 21 on the third control board 20. The second signal controller 21 can reset the entire second control board 30 based on the reset information. During this process, the retimer 32 in the second control board 30 will also be powered on again, so as to complete the reset, and the firmware will be reloaded, and the PCIe link will be reloaded at the same time, so as to avoid GPU loss.

[0072] In a feasible embodiment, the second signal controller 21 is further configured to: in response to the reset information, pull down the power enable signal of the second control board 30 to a third level, and pull up the power enable signal to a fourth level after a second target duration to enable the second control board 30 to complete the reset; the third level is less than the fourth level.

[0073] In the present feasible embodiment, after the second signal controller 21 responds to the received reset information, it will parse the reset information to determine the operation that needs to be executed indicated by the reset information. For example, if the second signal controller 21 parses that the reset information indicates that the second control board 30 needs to be reset, it will pull down the power enable signal of the second control board 30 to a third level, that is, a low level, usually 0V or grounded, to make the second control board 30 enter the reset state, and maintain this state for a second target duration, such as 2 seconds, to ensure that the second control board 30 is completely reset, and then pull up the power enable signal of the second control board 30 to a fourth level, that is, a high level, usually 3.3V or 5V, to power on the second control board 30 again, so as to complete the reset. Among them, it can be determined whether the first target duration is reached through a timer or a counter inside the second signal controller 21.

[0074] During the reset process of the second control board 30, the retimer 32 in the second control board 30 will also be powered on again. At this time, the internal circuit of the retimer 32 will be re-initialized, all registers and status information will be cleared, and the retimer 32 will reload the firmware. The firmware usually includes device driver programs and configuration parameters, and will also check the hardware status to ensure the normal operation of the device.

[0075] After the retimer 32 reloads the firmware, it will attempt to re - establish the PCIe link. This process includes: detecting the integrity of the PCIe signal; re - establishing connections with other devices on the PCIe bus (such as the CPU, GPU, etc.); setting the relevant parameters of the PCIe link according to the configuration parameters in the firmware, including parameters such as rate and width; verifying whether the link is working properly to ensure the reliability of data transmission. Thus, GPU loss can be avoided.

[0076] In an implementable embodiment, the target processor is further configured to: generate a warning message and display the warning message; the warning message is used to indicate that the cold reset is not completed.

[0077] In this implementable embodiment, if the target processor cannot obtain the reset information of the cold reset, such as the target processor is in a restart state and the BMC configuration is incorrect, a warning message can be generated in the BMC web interface and displayed; the warning message is used to indicate that the cold reset is not completed, and the user can perform a shutdown and then power - on operation on the device based on this warning message to ensure that the user can take corresponding measures in a timely manner for the situation where the cold reset is not completed.

[0078] Figure 6 The structural schematic of a cold reset system according to an embodiment of the present disclosure is shown Figure 2 , such as Figure 6 shown, Figure 5 In [reference], the first control board 10 can be the main board, the first processor 11 can be the CPU, the second processor 12 can be the BMC, the target processor can be the BMC, the first signal controller 13 can be the MB CPLD; the second control board 30 can be the HGX, the reset processor 31 can be the FPGA, the retimer 32 is the retimer chip, and the graphics processor 33 is the GPU; the second control board 20 can be the Switch board, and the second signal controller 21 can be the SW CPLD.

[0079] When a cold reset occurs on the main board, it notifies the MB CPLD on the main board through GPIO1. The MB CPLD stores the reset information in the register and sends a prompt signal ALERT to the BMC. The BMC reads the register of the MB CPLD to obtain the reset information, and then the BMC notifies the FPGA on the HGX through the USB link between them that the retimer chip needs to be reset. The above process specifically includes:

[0080] 1. When the server is running, a cold reset occurs in the following situations:

[0081] a. When modifying some configuration options under the BIOS configuration, a cold reset is required to make the modified options take effect. Or when certain exceptions occur in the operating system during system operation, the operating system will inform the BIOS, and the BIOS will trigger a cold reset. At the same time, the CPU executes the trigger instruction of the BIOS, and the CPU will inform the MB CPLD that a cold reset has been triggered through the GPIO1 signal between the CPU and the MB CPLD;

[0082] b. When the user of the server performs a forced system restart (i.e., a cold reset of the system) on the server through the BMC web interface, the BMC will trigger the SYS_RESET_N signal and inform the MB CPLD of the reset information;

[0083] 2. When the CPU or BMC triggers a cold reset, the MB CPLD stores the reset information in the register inside the MB CPLD and sends a prompt signal ALERT to inform the BMC that it needs to read the reset information in the register. After the BMC reads the reset information in the register, the MB CPLD will clear the data in the register;

[0084] 3. After receiving the prompt signal ALERT, the BMC reads the register in the MB CPLD. When it determines that the system triggers a cold reset, it directly transmits the read reset information to the FPGA on the HGX through the USB link;

[0085] 4. After receiving the information, the FPGA individually pulls down the EN signal of the retimer chip for 1 s and then releases it. After the retimer chip is powered on, it will reload the firmware and re-link the PCIe signal to ensure that the GPU is not lost;

[0086] 5. If the BMC cannot read the reset information in the register, the MB CPLD will inform the SW CPLD of the reset information through the GPIO signal between the MB CPLD and the SW CPLD;

[0087] 6. After obtaining the reset information, the SW CPLD will pull down the BASE_PWR_EN signal of the HGX to enable the entire HGX to perform a power-down timing sequence. After pulling it down for 2 s and then releasing it, the power-down time of the HGX can meet the specification requirements and then power on again;

[0088] 7. The retimer chip will also be powered on during the power-on and power-off process of the HGX, reload the firmware, and reload the PCIe link at the same time to avoid GPU loss;

[0089] 8. If the BMC fails to obtain the reset information for cold reset, a warning message will be generated and displayed in the BMC web. The warning message is used to indicate that the system cold reset is not completed. Users can perform a shutdown and then power-on operation on the device based on this warning message to ensure that they can take corresponding measures in a timely manner for the incomplete cold reset situation.

[0090] Thus, when a cold reset occurs at the BIOS or BMC side, the BMC notifies the FPGA on the HGX through the USB link to power on and off the retimer chip separately, without affecting the normal use of other devices. Moreover, after a cold reset occurs, it can ensure that the retimer reloads the firmware and re-links the PCIe signal.

[0091] Figure 1 The flowchart of a cold reset method according to an embodiment of the present disclosure is shown Figure 1 , as Figure 1 shown, a cold reset method, applied to a cold reset system, includes:

[0092] Step S101, any processor on the first control board triggers a cold reset, and the target processor on the first control board obtains the reset information of the cold reset.

[0093] In this embodiment, the first control board is the board that controls all tasks of the system. The first control board can be the main board. The first control board 10 includes at least two processors. The at least two processors can be the first processor 11 and the second processor 12. The target processor is the same as or different from the processor that triggers the cold reset. The target processor can be the second processor 12. After any processor among the at least two processors triggers a cold reset, the generated reset information can include the source of the reset event, the type of the reset event, the timestamp or serial number, the reset trigger reason, and the system status information, etc. Among them, the source of the reset event can include whether it is triggered by the BIOS or the BMC; the timestamp or serial number can be used to distinguish different reset events; the reset trigger reason can include BIOS setting changes, system exceptions, user operations through the BMC web interface, etc.; the system status information includes the power status, device status, etc., which are used for subsequent analysis or processing.

[0094] Step S102, the target processor sends the reset information to the reset processor on the second control board.

[0095] In this embodiment, the second control board is the board that executes the image processing task. The second control board can be the HGX. If the target processor is the second processor 12, then the second processor 12 can obtain the reset information of the cold reset and send the reset information to the reset processor 31 on the second control board 30.

[0096] Step S103, the reset processor resets the retimer on the second control board based on the reset information.

[0097] In this embodiment, the retimer 32 is connected to the graphics processor on the second control board. The reset processor 31 can reset the retimer 32 (i.e., Retimer) on the second control board 30 based on the received reset information. After the retimer 32 is reset, it will reload the firmware and reload the PCIe link simultaneously, thus avoiding GPU loss. It should be emphasized that the target processor will send the reset information to the reset processor 31 only when the system triggers a cold reset. If the system triggers a warm reset, it will not obtain the reset information, that is, the process of resetting the retimer 32 will not be started.

[0098] In the present disclosure, the target processor (such as the second processor 12) on the first control board 10 will obtain the reset information of the cold reset after a cold reset occurs on the first control board 10, and directly send the reset information to the reset processor 31 on the second control board 30. The reset processor 31 alone resets the retimer 32 on the second control board 30, so as to ensure that the retimer 32 reloads the connected graphics processor 33, avoid the loss of the graphics processor, and does not affect the normal use of other devices. In addition, there is no need to reserve signals between the CPU and the MB CPLD, and between the MB CPLD and the SW CPLD, and the retimer 32 can be directly reset, avoiding wasting time and cost.

[0099] Figure 2 Shows the flow schematic of a cold reset method according to an embodiment of the present disclosure Figure 2 , such as Figure 2 shown, a cold reset method includes:

[0100] Step S201, any processor on the first control board triggers a cold reset and sends the reset information of the cold reset to the first signal controller on the first control board.

[0101] In this embodiment, the first control board 10 further includes a first signal controller 13. After any processor on the first control board triggers a cold reset, it will send the reset information of the cold reset to the first signal controller 13 on the first control board 10.

[0102] Step S202, the first signal controller stores the reset information in the register in the first signal controller, generates a prompt signal, and sends the prompt signal to the target processor.

[0103] In this embodiment, a register 14 is provided in the first signal controller 13. After the first signal controller 13 receives the reset information, it stores the reset information in the register 14 and generates a prompt signal, which is sent to the target processor. The prompt signal indicates that the reset information has been stored in the register 14 and is used to prompt the target processor to read the reset information in the register 14.

[0104] Step S203: In response to the prompt signal, the target processor reads the reset information in the register through the internal integrated circuit bus.

[0105] In this embodiment, after the target processor receives the prompt signal, it responds to the prompt signal and reads the reset information from the register 14 through I2C. I2C is a serial communication protocol applied to electronic devices and is mainly used in short-distance and low-speed communication scenarios.

[0106] Step S204: The target processor sends the reset information to the reset processor on the second control board.

[0107] Step S205: The reset processor resets the retimer on the second control board based on the reset information.

[0108] The specific implementation details of steps S204 - S205 are similar to those of steps S102 - S103 and will not be elaborated here.

[0109] In another embodiment, a cold reset method further includes: in response to the target processor having read the reset information, the first signal controller clears the reset information from the register.

[0110] In this embodiment, a flag bit is provided in the first signal controller 13. This flag bit is used to indicate whether the target processor has read the reset information in the register 14. When the first signal controller 13 stores the reset information in the register 14, it sets this flag bit to "unread". After the target processor reads the reset information from the register 14, it clears this flag bit or sets it to "read". In response to this flag bit being cleared or set to "read", the first signal controller 13 clears the reset information from the register 14.

[0111] In another embodiment, the processor that triggers the cold reset is the first processor, which is different from the target processor. Sending the reset information of the cold reset to the first signal controller on the first control board includes: the first processor sending the reset information of the cold reset to the first signal controller through a general-purpose input / output interface. That is, the first processor 11 can send the reset information of the cold reset to the first signal controller 13 through the general-purpose input / output interface GPIO. GPIO is a common hardware interface widely used in devices such as embedded systems, microcontrollers, and computer motherboards. The GPIO interface allows hardware devices to communicate with external circuits through simple digital signals to achieve input / output functions.

[0112] In another embodiment, the processor that triggers the cold reset is the second processor, which is the same as the target processor. Sending the reset information of the cold reset to the first signal controller on the first control board includes: the second processor sending the reset information of the cold reset to the first signal controller through a hardware reset signal. That is, the second processor 12 can send the reset information of the cold reset to the first signal controller 13 through hardware reset signals such as SYS_RESET_N and RST_N. Among them, the "N" in hardware reset signals such as SYS_RESET_N and RST_N indicates that this is a low-level effective signal, that is, when the signal is at a low level, the system will trigger a reset operation. The SYS_RESET_N signal is a common hardware signal usually used for system reset operations, while RST_N is usually used for resetting specific devices or modules.

[0113] In another embodiment, step S102 "the target processor sends the reset information to the reset processor on the second control board" includes: the target processor sending the reset information to the reset processor on the second control board through a universal serial bus. That is, the target processor can send the reset information to the reset processor 31 on the second control board 30 through USB.

[0114] In another embodiment, step S103 "the reset processor resets the retimer on the second control board based on the reset information" includes: the reset processor, in response to the reset information, pulls the enable signal of the retimer down to the first level and raises the enable signal to the second level after the first target duration, so that the retimer completes the reset; the first level is less than the second level.

[0115] In this embodiment, after the reset processor 31 receives the reset information, it will parse the reset information to determine the operation that needs to be executed as indicated by the reset information. For example, if the reset processor 31 parses that the reset information indicates that the re-timer 32 needs to be reset, it will pull the enable signal of the re-timer 32 down to the first level, that is, the low level, usually 0V or grounded, to make the re-timer 32 enter the reset state and maintain this state for the first target duration, such as 1 second, to ensure that the re-timer 32 is fully reset, and then pull the enable signal of the re-timer 32 up to the second level, that is, the high level, usually 3.3V or 5V, to power on the re-timer 32 again, thus completing the reset. Among them, the internal timer or counter of the FPGA can be used to determine whether the first target duration is reached.

[0116] After the enable signal of the re-timer 32 is pulled up to the second level, the re-timer 32 will be powered on again. At this time, the internal circuit of the re-timer 32 will be re-initialized, all registers and status information will be cleared, and the re-timer 32 will reload the firmware. The firmware usually contains the device driver and configuration parameters, and will also check the hardware status to ensure the normal operation of the device.

[0117] After the re-timer 32 reloads the firmware, it will attempt to re-establish the PCIe link. This process includes: detecting the integrity of the PCIe signal; re-establishing the connection with other devices (such as CPU, GPU, etc.) on the PCIe bus; setting the relevant parameters of the PCIe link according to the configuration parameters in the firmware, including parameters such as rate and width; verifying whether the link works properly to ensure the reliability of data transmission. Thus, GPU loss can be avoided.

[0118] Figure 3 The flowchart of a cold reset method according to an embodiment of the present disclosure is shown Figure 3 , as Figure 3 shown, a cold reset method includes:

[0119] Step S301, any processor on the first control board triggers a cold reset and sends the reset information of the cold reset to the first signal controller on the first control board.

[0120] Step S302, the first signal controller stores the reset information in the register in the first signal controller and generates a prompt signal, and sends the prompt signal to the target processor.

[0121] The specific implementation details of steps S301 - S302 are similar to those of steps S201 - S202, and will not be elaborated here.

[0122] If the target processor can read the reset information in the register, steps S303 - S304 are executed:

[0123] Step S303: The target processor sends the reset information to the reset processor on the second control board.

[0124] Step S304: The reset processor resets the retimer on the second control board based on the reset information.

[0125] The specific implementation details of Steps S303 - S304 are similar to those of Steps S204 - S205, and will not be elaborated here.

[0126] If the target processor cannot read the reset information from the register, then Steps S305 - S306 are executed:

[0127] Step S305: The first signal controller sends the reset information to the second signal controller on the third control board.

[0128] In this embodiment, the cold reset system further includes a third control board 20. The third control board 20 is a board for signal exchange, which is arranged between the first control board 10 and the second control board 30 and is used for signal exchange between the first control board 10 and the second control board 30, so as to achieve efficient data transmission between the first control board 10 and the second control board 30. The third control board 20 includes a second signal controller 21. If the target processor cannot read the reset information from the register, for example, the I2C bus connection between the target processor and the register 14 is poor, short - circuited or open - circuited, and the BMC is damaged or misconfigured, etc., then the first signal controller 13 will send the reset information to the second signal controller 21 on the third control board 20.

[0129] Step S306: The second signal controller resets the second control board based on the reset information.

[0130] In this embodiment, the second signal controller 21 can reset the entire second control board 30 based on the reset information. During this process, the retimer 32 in the second control board 30 will also be powered on again, so as to complete the reset, and the firmware will be re - loaded, and the PCIe link will be re - loaded at the same time, thus avoiding GPU loss.

[0131] In another embodiment, Step S306 "The second signal controller resets the second control board based on the reset information" includes: The second signal controller responds to the reset information, pulls the power enable signal of the second control board down to the third level, and pulls the power enable signal up to the fourth level after the second target duration to enable the second control board to complete the reset; the third level is less than the fourth level.

[0132] In this embodiment, after the second signal controller 21 responds to the received reset information, it will parse the reset information to determine the operation that needs to be executed as indicated by the reset information. For example, if the second signal controller 21 parses that the reset information indicates that the second control board 30 needs to be reset, it will pull down the power enable signal of the second control board 30 to the third level, that is, the low level, usually 0V or grounded, to make the second control board 30 enter the reset state and maintain this state for the second target duration, such as 2 seconds, to ensure that the second control board 30 is fully reset, and then pull up the power enable signal of the second control board 30 to the fourth level, that is, the high level, usually 3.3V or 5V, to power on the second control board 30 again, thus completing the reset. Among them, whether the first target duration is reached can be determined by a timer or a counter inside the second signal controller 21.

[0133] During the reset process of the second control board 30, the re-timer 32 in the second control board 30 will also be powered on again. At this time, the internal circuit of the re-timer 32 will be re-initialized, all registers and status information will be cleared, and the re-timer 32 will re-load the firmware. The firmware usually includes the device driver and configuration parameters, and will also check the hardware status to ensure the normal operation of the device.

[0134] After the re-timer 32 re-loads the firmware, it will attempt to re-establish the PCIe link. This process includes: detecting the integrity of the PCIe signal; re-establishing connections with other devices (such as CPUs, GPUs, etc.) on the PCIe bus; setting relevant parameters of the PCIe link according to the configuration parameters in the firmware, including parameters such as rate and width; verifying whether the link is working properly to ensure the reliability of data transmission. Thus, GPU loss can be avoided.

[0135] In another embodiment, after "any processor on the first control board triggers a cold reset" in step S101, the method further includes: in response to the target processor being unable to obtain the reset information for the cold reset, the target processor generates a warning message and displays the warning message; the warning message is used to indicate that the cold reset is not completed.

[0136] In this embodiment, if the target processor is unable to obtain the reset information for the cold reset, such as the target processor is in a restart state and the BMC configuration is incorrect, etc., a warning message can be generated in the BMC web interface and the warning message can be displayed; the warning message is used to indicate that the cold reset is not completed, and the user can perform a shutdown and then power-on operation on the device based on this warning message to ensure that the user takes corresponding measures in a timely manner for the situation where the cold reset is not completed.

[0137] According to an embodiment of the present disclosure, the present disclosure further provides an electronic device and a readable storage medium. Among them, the electronic device includes the cold reset system described in the present disclosure, and the cold reset system can execute the cold reset method described in the present disclosure.

[0138] Figure 7 FIG. shows a schematic block diagram of an exemplary electronic device 800 that can be used to implement embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, for example, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, for example, personal digital processors, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0139] As Figure 7 shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory ROM 802 or a computer program loaded from a storage unit 808 into a random access memory RAM 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other through a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0140] A plurality of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0141] The computing unit 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 executes the various methods and processes described above, such as a cold reset method. For example, in some embodiments, a cold reset method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the cold reset method described above can be executed. Alternatively, in other embodiments, the computing unit 801 can be configured to execute a cold reset method by any other suitable means (e.g., by means of firmware).

[0142] Various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), systems on a chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a dedicated or general-purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0143] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program codes can be executed entirely on the machine, partially on the machine, as an independent software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0144] In the context of this disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0145] In order to provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0146] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0147] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is generated by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, can also be a server of a distributed system, or a server incorporating a blockchain.

[0148] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. There is no limitation here.

[0149] In addition, the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include at least one such feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise specifically defined.

[0150] As described above, this is only the specific implementation manner of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed in this disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be subject to the protection scope of the claimed rights.

Claims

1. A cold reset method, characterized in that, The method includes: Any processor on the first control board triggers a cold reset, and the target processor on the first control board acquires the reset information of the cold reset; the first control board is the board for all tasks of the control system, and the target processor is the same as or different from the processor that triggers the cold reset; The target processor sends the reset information to the reset processor on the second control board; the second control board is the board for executing image processing tasks; The reset processor resets the retimer on the second control board based on the reset information, and the retimer is connected to the graphics processor on the second control board; Among them, any processor on the first control board triggering a cold reset includes: Any processor on the first control board triggers a cold reset and sends the reset information of the cold reset to the first signal controller on the first control board; The first signal controller stores the reset information in the register in the first signal controller, generates a prompt signal, and sends the prompt signal to the target processor; Among them, the target processor sending the reset information to the reset processor on the second control board includes: The target processor sends the reset information to the reset processor on the second control board through the Universal Serial Bus; Among them, the first control board includes a first processor and a second processor, the first processor is a Central Processing Unit (CPU), the second processor is a Baseboard Management Controller (BMC), and the second processor is the target processor.

2. The method according to claim 1, wherein The target processor on the first control board acquiring the reset information of the cold reset includes: The target processor reads the reset information in the register through the Inter-Integrated Circuit bus in response to the prompt signal.

3. The method according to claim 2, characterized in that, The method further includes: The first signal controller clears the reset information from the register in response to the target processor having read the reset information.

4. The method according to claim 1, characterized in that The processor that triggers the cold reset is the first processor, and the first processor is different from the target processor. Sending the reset information of the cold reset to the first signal controller on the first control board includes: The first processor sends the reset information of the cold reset to the first signal controller through the General-Purpose Input / Output interface.

5. The method according to claim 1, wherein The processor that triggers the cold reset is the second processor, and the second processor is the same as the target processor. Sending the reset information of the cold reset to the first signal controller on the first control board includes: The second processor sends the reset information of the cold reset to the first signal controller through the hardware reset signal.

6. The method according to claim 1, characterized in that, The reset processor resetting the retimer on the second control board based on the reset information includes: The reset processor, in response to the reset information, pulls the enable signal of the retimer down to a first level and raises the enable signal to a second level after a first target duration, so that the retimer completes the reset; the first level is less than the second level.

7. The method according to claim 2, characterized in that, After the target processor reads the reset information from the register through the internal integrated circuit bus in response to the prompt signal, the method further includes: In response to the target processor being unable to read the reset information from the register, the first signal controller sends the reset information to the second signal controller on the third control board; the third control board is a board for signal exchange. The second signal controller resets the second control board based on the reset information.

8. The method according to claim 7, wherein The second signal controller resetting the second control board based on the reset information includes: In response to the reset information, the second signal controller pulls the power enable signal of the second control board down to a third level, and after a second target duration, raises the power enable signal to a fourth level to complete the reset of the second control board; the third level is less than the fourth level.

9. The method according to claim 1, wherein After any processor on the first control board triggers a cold reset, the method further includes: In response to the target processor being unable to obtain the reset information of the cold reset, the target processor generates a warning message and displays the warning message; the warning message is used to indicate that the cold reset is not completed.

10. A cold reset system, characterized in that, The system includes: A first control board, which is a board that controls all tasks of the system and includes at least two processors; any one of the at least two processors is used to trigger a cold reset, and the target processor among the at least two processors is used to obtain the reset information of the cold reset and send the reset information to the reset processor on the second control board, and the target processor is the same as or different from the processor that triggers the cold reset. A second control board, which is a board for performing image processing tasks and includes a reset processor, a retimer, and a graphics processor, and the retimer is connected to the graphics processor on the second control board; the reset processor is used to reset the retimer on the second control board based on the reset information. Wherein, the first control board further includes a first signal controller; any one of the at least two processors is used to trigger a cold reset and send the reset information of the cold reset to the first signal controller on the first control board. The first signal controller is used to store the reset information in a register in the first signal controller, generate a prompt signal, and send the prompt signal to the target processor; wherein, the target processor is further used to: send the reset information to the reset processor on the second control board through a universal serial bus. Wherein, the first control board includes a first processor and a second processor, the first processor is a central processing unit CPU, the second processor is a baseboard management controller BMC, and the second processor is the target processor.

11. The system according to claim 10, wherein The target processor is further used to: In response to the prompt signal, read the reset information from the register through the internal integrated circuit bus.

12. The system according to claim 11, wherein The first signal controller is further used to: In response to the target processor having read the reset information, clear the reset information from the register.

13. The system according to claim 10, wherein The at least two processors include a first processor, and the first processor is configured to send the reset information of the cold reset to the first signal controller through a general-purpose input / output interface.

14. The system according to claim 10, wherein The at least two processors include a second processor, and the second processor is configured to send the reset information of the cold reset to the first signal controller through a hardware reset signal.

15. An electronic device, characterized in that, A cold reset system according to any one of claims 10-14, the cold reset system being capable of performing the cold reset method according to any one of claims 1-9.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are for causing a computer to execute the method according to any one of claims 1-9.

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