Self-repairing method of processor chip, processor chip, medium and equipment

Abstract

The invention discloses a self-repairing method of a processor chip, the processor chip, a medium and equipment. The method comprises the steps that a target redundant PE group is determined according to the position of a fault PE core in a fault function PE block of a processor chip, a PE array of the processor chip is divided into a plurality of self-repairing PE array blocks, each self-repairing PE array block is further divided into a function PE block and at least one redundant PE group, and the fault function PE block and the target redundant PE group belong to the same self-repairing PE array block; an interconnection selection control signal is configured, and the interconnection selection control signal is used for indicating the target redundant PE group to replace the PE group where the fault PE core is located, so that interconnection between the self-repairing PE array block to which the fault function PE block belongs and the adjacent self-repairing PE array block is achieved; the PE group where the redundant PE group and the fault PE core are located comprises PE rows, and / or the PE group where the redundant PE group and the fault PE core are located comprises PE columns.

Description

Technical Field

[0001] The present invention relates to the field of chip PE core repair technology, and more specifically, to a self-repair method of a processor chip, a processor chip, a medium and a device. Background Art

[0002] With the rapid development of deep learning and artificial intelligence (AI) technology, the parameter scale of AI models has become increasingly large. The computing and memory bandwidth resources of traditional AI processors can no longer meet the training and reasoning requirements of AI models with current parameter scales. In order to solve the bottleneck problems of large model training, such as limited computing power and memory bandwidth, a variety of new processor architectures have been proposed by academia and industry. Among them, wafer-level processor chips have a computing power and memory bandwidth far higher than traditional AI chips due to their unique architectural design. This makes them stand out among many new processor architectures and are widely studied by the industry.

[0003] Wafer-level processor is an advanced concept that uses the entire silicon wafer for a single processor. A large number of processor cores are designed and manufactured in a single chip. These cores are evenly arranged in an array and interconnected through a communication network (such as a 2DMesh network) to achieve the purpose of improving computing performance and energy efficiency. Due to process deviations, environmental factors and other factors, wafer-level processors are prone to multiple defects during the manufacturing and packaging process. These defects can cause performance degradation or even failure of certain processor cores, directly leading to a reduction in the yield of wafer-level processors. Chip redundancy design is a method to improve system reliability and fault tolerance. By adding additional hardware components to ensure that when certain components in the chip fail, some redundant replacement strategies can be used to ensure the normal function of the chip; therefore, studying the redundant architecture design of wafer-level processors is of great significance to improving chip yield. Summary of the invention

[0004] In order to improve chip yield, the present invention provides a self-repair method for a processor chip, a processor chip, a medium and a device.

[0005] According to one aspect of the present invention, there is provided a self-repair method for a processor chip, comprising: According to the location of the faulty PE core in the faulty functional PE block of the processor chip, a target redundant PE group is determined, the PE array of the processor chip is divided into a plurality of self-repairing PE array blocks, each self-repairing PE array block is further divided into a functional PE block and at least one redundant PE group, the faulty functional PE block and the target redundant PE group belong to the same self-repairing PE array block; An interconnection selection control signal is configured, and the interconnection selection control signal is used to instruct the target redundant PE group to replace the PE group where the faulty PE core is located, so as to realize the interconnection between the self-repairing PE array block to which the faulty functional PE block belongs and the adjacent self-repairing PE array block; the redundant PE group and the PE group where the faulty PE core is located include PE rows, and / or the redundant PE group and the PE group where the faulty PE core is located include PE columns.

[0006] Optionally, if the redundant PE group includes a PE row, adjacent self-repair PE array blocks in the row direction are interconnected via a first check interconnect structure, and configuring the interconnect selection control signal includes: configuring the interconnect selection control signal of the first check interconnect structure between the self-repair PE array block to which the fault function PE block belongs and the self-repair PE array block adjacent to the row.

[0007] Optionally, each PE core in the functional PE block is provided with a second multiple-selection interconnection structure on the interconnection link of the PE core adjacent to the column direction, and the interconnection selection control signal is configured, further comprising: configuring the interconnection selection control signal of the second multiple-selection interconnection structure of each PE core in the PE group where the faulty PE core is located, so that the PE group where the faulty PE core is located is skipped in the column direction; or, Configuring the interconnection selection control signal also includes: configuring the interconnection selection control signal of the routing module of each PE core in the PE group where the faulty PE core is located, indicating that the routing module is in a fixed routing mode so that the PE group where the faulty PE core is located is skipped in the column direction.

[0008] Optionally, if the redundant PE group includes a PE column, adjacent PE array blocks in the column direction are interconnected via a third check interconnect structure, and configuring the interconnect selection control signal includes: configuring the interconnect selection control signal of the third check interconnect structure between the self-repair PE array block to which the fault function PE block belongs and the repair PE array block of the adjacent group in the column.

[0009] Optionally, each PE core in the functional PE block is provided with a fourth multiple-selection interconnection structure on the interconnection link of the PE core adjacent to the row direction, and the interconnection selection control signal is configured, further comprising: configuring the interconnection selection control signal of the fourth multiple-selection interconnection structure of each PE core in the PE group where the faulty PE core is located, so that the PE group where the faulty PE core is located is skipped in the row direction; or, Configuring the interconnection selection control signal also includes: configuring the interconnection selection control signal of the routing module of each PE core in the PE group where the faulty PE core is located, indicating that the routing module is in a fixed routing mode so that the PE group where the faulty PE core is located is skipped in the row direction.

[0010] Optionally, determining the target redundant PE group according to the location of the faulty PE core in the faulty functional PE block of the processor chip includes: A redundant PE group closest to the faulty PE core is selected from the redundant PE groups of the self-repairing PE array block to which the faulty functional PE block belongs as the target redundant PE group.

[0011] According to another aspect of the present invention, there is provided a processor chip, comprising: a PE array, the PE array being divided into a plurality of self-repairing PE array blocks, each self-repairing PE array block being further divided into a functional PE block and at least one redundant PE group, the faulty functional PE block and the target redundant PE group belonging to the same self-repairing PE array block.

[0012] Optionally, the redundant PE group includes PE rows, and / or the redundant PE group includes PE columns.

[0013] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the method described in any one of the above aspects of the present invention.

[0014] According to yet another aspect of the present invention, an electronic device is provided, wherein the electronic device comprises the processor chip described above in the present invention.

[0015] Therefore, the present invention divides the entire PE array in the wafer-level processor chip into multiple small array blocks; each small array block has an independent redundant structure, and these redundant structures are not shared with other small array blocks. The scope of influence of redundant replacement is effectively controlled. The check logic of switching redundant structures and the strategy of redundant switching are proposed, which can effectively reduce the hardware resources of redundant design and simplify redundant switching control and configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] A more complete understanding of exemplary embodiments of the present invention may be obtained by referring to the following drawings: Figure 1 is a flowchart of a self-repair method for a processor chip provided by an exemplary embodiment of the present invention; Figure 2 is a schematic diagram of a row check logic of a row redundant PE group provided by an exemplary embodiment of the present invention; Figure 3 is a schematic diagram of a check logic provided by an exemplary embodiment of the present invention; Figure 4 It is a schematic diagram of replacement rules for a faulty PE core provided by an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0017] Below, the exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described here.

[0018] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0019] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present invention are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0020] It should also be understood that, in the embodiments of the present invention, “plurality” may refer to two or more than two, and “at least one” may refer to one, two or more than two.

[0021] It should also be understood that any component, data or structure mentioned in the embodiments of the present invention can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0022] In addition, the term "and / or" in the present invention is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects before and after are in an "or" relationship.

[0023] It should also be understood that the description of the various embodiments of the present invention focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0024] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0025] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0026] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0027] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0028] Figure 1 1 is a flow chart of a self-repair method for a processor chip provided in accordance with the first aspect of an embodiment of the present invention. This embodiment can be applied to electronic devices, such as Figure 1As shown, the self-repair method 100 of the processor chip includes the following steps: Step 101, determining a target redundant PE group according to the location of a faulty PE core in a faulty functional PE block of the processor chip, wherein the PE array of the processor chip is divided into a plurality of self-repairing PE array blocks, each of which is further divided into a functional PE block and at least one redundant PE group, and the faulty functional PE block and the target redundant PE group belong to the same self-repairing PE array block; Step 102, configuring an interconnection selection control signal, wherein the interconnection selection control signal is used to instruct the target redundant PE group to replace the PE group where the faulty PE core is located, so as to realize the interconnection between the self-repairing PE array block to which the faulty functional PE block belongs and the adjacent self-repairing PE array block.

[0029] The redundant PE group and the PE group where the faulty PE core is located include PE rows, and / or the redundant PE group and the PE group where the faulty PE core is located include PE columns, that is, the PE group is one or more rows of PEs, or the PE group is one or more columns of PEs.

[0030] Specifically, the present invention proposes an architecture design for row or column redundant replacement, which minimizes resource consumption caused by redundant design while also making the control logic of redundant switching relatively simple.

[0031] Specifically, the entire PE array in the processor chip is divided into multiple self-repairing PE array blocks; each self-repairing PE array block has an independent redundant structure, and these redundant structures will not be shared with other self-repairing PE array blocks, effectively controlling the impact range of redundant replacement. A check logic for switching redundant structures and a redundant switching strategy are designed to effectively reduce the hardware resources of redundant design and simplify redundant switching control and configuration.

[0032] In one embodiment of the present invention, taking a wafer-level processor chip as an example, the specific implementation of the self-repair of the processor chip is as follows: Figure 2As shown, first, the whole wafer processor is divided into multiple groups of self-repair PE array blocks (RA); each self-repair PE array block contains a functional PE block and multiple redundant PE groups, the functional PE block is the array block used by the chip function in the absence of faults, and the redundant PE group is the PE block used as a redundant replacement when there is a faulty PE core in the functional PE block; there are three forms of self-repair PE array blocks, such as: only row redundant PE groups, only column redundant PE groups, and both row redundant PE groups and column redundant PE groups. When there is only a row redundant PE group in the self-repair PE array block, the self-repair arrays adjacent to each other on the left and right need to be interconnected through the check logic (first check interconnect structure), while the self-repair arrays adjacent to each other on the top and bottom can be directly interconnected through PE. Accordingly, configuring the interconnection selection control signal includes: configuring the interconnection selection control signal of the first check interconnect structure between the self-repair PE array block of the faulty functional PE block and the row-adjacent self-repair PE array block. When there is only a column redundant PE group in the self-repair PE array block, the upper and lower adjacent self-repair arrays need to be interconnected through the check logic (third check interconnect structure), while the left and right adjacent self-repair arrays can be directly interconnected through PE. Accordingly, configuring the interconnection selection control signal includes: configuring the interconnection selection control signal of the third check interconnect structure between the self-repair PE array block to which the fault function PE block belongs and the column adjacent group repair PE array block. When both row and column redundant PE groups exist in the self-repair PE array block, the upper and lower adjacent self-repair arrays need to be interconnected through the check logic, and the left and right adjacent self-repair arrays also need to be interconnected through the check logic. Generally, in the row redundant PE group, the number of rows of the redundant PE group can be 1 row or more rows; in the column redundant PE group, the number of columns of the redundant PE group can be 1 column or more columns; but the number of rows / columns will only affect the complexity of the internal connection of the check logic, and has no effect on the redundant architecture solution.

[0033] Since the row redundant PE group design architecture and the column redundant PE group design architecture are symmetrical and similar, the present invention takes the row redundant PE group design as an example, and the number of rows of the row redundant PE group is 1 row, such as Figure 2As shown: the self-repairing PE array block includes 2 groups of row redundant PE groups and 1 group of functional array blocks, and the 2 groups of row redundant PE groups are respectively located above and below the functional array block; the self-repairing PE array blocks adjacent to each other are directly connected through their adjacent PE cores; the self-repairing PE array blocks adjacent to each other on the left and right need to be interconnected with the help of row check logic (i.e., the first check interconnect structure mentioned above); the row check logic adopts a CrossBar-like structure, and the input port in the row check logic can be connected to 3 output ports, namely, the output ports directly opposite to the input port on the left and right and the two output ports adjacent to the output port on the upper and lower sides (for the input ports at the upper and lower boundaries, they can only be connected to two of the output ports); the configuration register is used to store the selection control signal of the row check logic (i.e., the interconnection selection control signal of the first check interconnect structure), so as to control the connection relationship between the input port and the output port of the check logic.

[0034] In one embodiment of the present invention, the check logic can implement the row (or column) replacement function of the faulty PE core row (or column) of the functional array, thereby ensuring that the left-right routing of the functional array is normal. However, since the row where the faulty PE is located needs to be bypassed, the up-down routing also needs to implement the cross-row connection function. Figure 3 Two implementation schemes are given. Taking the row redundant PE group as an example, there are two implementation schemes: PE core bypass scheme A and PE core bypass scheme B.

[0035] 1) PE core bypass solution A: Add PE reselection logic (second reselection interconnection structure) to the interconnection link between the PE core and the upper and lower adjacent PEs to implement the bypass function of the PE core. The control signal of the PE reselection logic (i.e., the interconnection selection control signal of the second reselection interconnection structure) is controlled by the configuration signal. Solution A consumes additional logic resources and routing resources, but can cope with the situation where the router itself has a fault; 2) PE core bypass solution B: Due to the Router module contained in the PE core itself, all Routers in the row where the faulty PE is located can be configured into a fixed routing mode, thereby realizing the bypass function of the PE core. Solution B uses the Router's own function and does not require additional logic resources and routing resources, but cannot handle the situation where the Router itself has a fault. Accordingly, configuring the interconnection selection control signal includes: configuring the interconnection selection control signal of the routing module of each PE core in the PE group where the faulty PE core is located, indicating that the routing module is in a fixed routing mode, so that the PE group where the faulty PE core is located is skipped in the column direction.

[0036] In addition, the check logic of the column redundant PE group is similar to that of the row redundant PE group, and will not be repeated here.

[0037] In one embodiment of the present invention, the replacement rule of rows or columns is as follows: For example, the row redundant PE groups are distributed on the upper and lower sides. When a PE core in a row of the functional array block fails, the redundant replacement direction is selected based on the distance between the failed row and the two redundant PE groups using the proximity principle. The replacement rules for the column redundant PE groups are the same as those for the row redundant PE groups.

[0038] by Figure 4 For example, in the self-repair PE array block 0 (SR-A0), there is a faulty PE core in the 0th row (F-R0) of the functional array block, and the faulty row is closer to the upper-row redundant PE group (R-U0), so the upper row of the faulty PE is selected to replace the faulty row. At this time, the F-R0 row of the self-repair PE array block 1 (SR-A1) is connected to R-U0 through the row check logic. In the self-repair PE array block 1 (SR-A1), there is a faulty PE core in the xth row (F-Rx) of the functional array block, and the faulty row is closer to the lower-row redundant PE group (R-D0), so the lower row of the faulty PE is selected to replace the faulty row. At this time, the F-Rx row of the self-repair PE array block 0 (SR-A0) is connected to R-D0 through the row check logic. In the self-repair PE array block 2 (SR-A2), there are faulty PE cores in both row 0 (F-R0) and row 1 (F-R1) of the functional array block, and both the upper-row redundant PE group (R-U0) and the lower-row redundant PE group (R-D0) need to be used simultaneously; at this time, the F-R0 row of the self-repair PE array block 3 (SR-A3) is connected to R-U0 through the row check logic, and at this time, (F-R1~ F-Rx) of the self-repair PE array block 3 (SR-A3) needs to be connected to (F-R2~ F-Rx, R-D0) through the row check logic.

[0039] In addition, since the faulty PE core needs to be replaced as a whole in the row where it is located, the faulty PE row has bypass capability in the upper and lower directions, that is, direct interconnection between the upper and lower adjacent rows of the faulty row can be achieved; the present invention provides two solutions, PE core bypass solution A and PE core bypass solution B, which can be selected according to actual needs.

[0040] The technical solution provided by the present invention can be applied to processor chips, and can effectively improve the yield of such processor chips. The main application scenarios include wafer-level processor chips, wafer-level processor boards, wafer-level processor servers and clusters; large-array multi-core processor chips, large-array multi-core processor boards, and large-array multi-core processor servers and clusters.

[0041] Therefore, the present invention divides the entire PE array in the processor chip into multiple small array blocks; each small array block has an independent redundant structure, and these redundant structures are not shared with other small array blocks. The scope of influence of redundant replacement is effectively controlled. The check logic of switching redundant structures and the strategy of redundant switching are proposed, which can effectively reduce the hardware resources of redundant design and simplify redundant switching control and configuration.

[0042] In addition, a second aspect of an embodiment of the present invention provides a processor chip, including: a PE array, wherein the PE array is divided into a plurality of self-repairing PE array blocks, each of which is further divided into a functional PE block and at least one redundant PE group.

[0043] The target redundant PE group is used to replace the PE group where the faulty PE core of the functional PE block in the self-repairing PE array block belongs.

[0044] The target redundant PE group is determined according to the location of the failed PE core.

[0045] The self-repairing PE array block of the faulty functional PE block replaces the PE group where the faulty PE core is located with the target redundant PE group according to the configured interconnection selection control signal, thereby realizing interconnection with adjacent self-repairing PE array blocks.

[0046] The redundant PE group and the PE group where the faulty PE core is located include PE rows (ie, row redundancy), and / or the redundant PE group and the PE group where the faulty PE core is located include PE columns (ie, column redundancy).

[0047] If the redundant PE group includes PE rows, the self-repairing PE array blocks adjacent to each other in the row direction are interconnected via a first multiplexing interconnect structure, and the interconnection selection control signal includes an interconnection selection control signal of the first multiplexing interconnect structure.

[0048] Furthermore, in one implementation, each PE core in the functional PE block is provided with a second multiplex interconnection structure on the interconnection link of the PE core adjacent to the column direction, and the interconnection selection control signal also includes the interconnection selection control signal of the second multiplex interconnection structure. In another implementation, the interconnection selection control signal also includes the interconnection selection control signal of the routing module of the PE core. By configuring the interconnection selection control signal of the routing module of each PE core in the PE group where the faulty PE core is located, the routing module is instructed to be in fixed routing mode, so that the PE group where the faulty PE core is located is skipped in the column direction.

[0049] If the redundant PE group includes PE columns, the PE array blocks adjacent to each other in the column direction are interconnected via a third multiplexing interconnect structure, and the interconnection selection control signal includes an interconnection selection control signal of the third multiplexing interconnect structure.

[0050] Furthermore, in one implementation, each PE core in the functional PE block is provided with a fourth multiplex interconnection structure on the interconnection link of the PE core adjacent to the row direction, and the interconnection selection control signal also includes the interconnection selection control signal of the fourth multiplex interconnection structure. In another implementation, the interconnection selection control signal also includes the interconnection selection control signal of the routing module of the PE core. By configuring the interconnection selection control signal of the routing module of each PE core in the PE group where the faulty PE core is located, the routing module is indicated to be in fixed routing mode, so that the PE group where the faulty PE core is located is skipped in the row direction.

[0051] In addition, a third aspect of an embodiment of the present invention provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the method described in any one of the above aspects of the present invention.

[0052] In addition, a fourth aspect of an embodiment of the present invention provides an electronic device, wherein the electronic device includes the above-mentioned processor chip of the present invention.

[0053] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present invention to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A self-repair method for a processor chip, characterized in that: include: Determine a target redundant PE group according to the position of the faulty PE core in the faulty functional PE block of the processor chip, the PE array of the processor chip is divided into a plurality of self-repairing PE array blocks, each self-repairing PE array block is further divided into a functional PE block and at least one redundant PE group, the faulty functional PE block and the target redundant PE group belong to the same self-repairing PE array block; An interconnection selection control signal is configured, wherein the interconnection selection control signal is used to instruct the target redundant PE group to replace the PE group where the faulty PE core is located, so as to realize the interconnection between the self-repairing PE array block to which the faulty functional PE block belongs and the adjacent self-repairing PE array block; the redundant PE group and the PE group where the faulty PE core is located include PE rows, and / or the redundant PE group and the PE group where the faulty PE core is located include PE columns.

2. The method according to claim 1, characterized in that If the redundant PE group includes a PE row, adjacent self-repair PE array blocks in the row direction are interconnected via a first check interconnect structure, and the configuring of the interconnect selection control signal includes: configuring an interconnect selection control signal of the first check interconnect structure between the self-repair PE array block to which the fault function PE block belongs and the self-repair PE array block adjacent to the row.

3. The method according to claim 2, characterized in that Each PE core in the functional PE block is provided with a second check interconnection structure on the interconnection link of the PE core adjacent to the column direction, and the configuration of the interconnection selection control signal further includes: configuring the interconnection selection control signal of the second check interconnection structure of each PE core in the PE group where the faulty PE core is located, so that the PE group where the faulty PE core is located is skipped in the column direction; or, The configuring interconnection selection control signal also includes: configuring the interconnection selection control signal of the routing module of each PE core in the PE group where the faulty PE core is located, indicating that the routing module is in a fixed routing mode so that the PE group where the faulty PE core is located is skipped in the column direction.

4. The method according to claim 1, characterized in that: If the redundant PE group includes a PE column, and adjacent PE array blocks in the column direction are interconnected via a third check interconnect structure, the configuring of the interconnect selection control signal includes: configuring an interconnect selection control signal of the third check interconnect structure between the self-repair PE array block to which the faulty functional PE block belongs and the repair PE array block of the adjacent column group.

5. The method according to claim 4, characterized in that Each PE core in the functional PE block is provided with a fourth reselection interconnection structure on the interconnection link of the PE core adjacent to the row direction, and the configuration of the interconnection selection control signal further includes: configuring the interconnection selection control signal of the fourth reselection interconnection structure of each PE core in the PE group where the faulty PE core is located, so that the PE group where the faulty PE core is located is skipped in the row direction; or, The configuring interconnection selection control signal also includes: configuring the interconnection selection control signal of the routing module of each PE core in the PE group where the faulty PE core is located, indicating that the routing module is in a fixed routing mode so that the PE group where the faulty PE core is located is skipped in the row direction.

6. The method according to any one of claims 1 to 5, characterized in that: The step of determining a target redundant PE group according to the location of a faulty PE core in a faulty functional PE block of the processor chip comprises: A redundant PE group closest to the faulty PE core is selected from the redundant PE groups of the self-repairing PE array block to which the faulty functional PE block belongs as the target redundant PE group.

7. A processor chip, characterized in that: include: The PE array is divided into a plurality of self-repairing PE array blocks, and each self-repairing PE array block is further divided into a functional PE block and at least one redundant PE group.

8. The processor chip according to claim 7, characterized in that: The redundant PE group includes PE rows, and / or the redundant PE group includes PE columns.

9. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and the computer program is used to execute the method according to any one of claims 1 to 6.

10. An electronic device, characterized in that: The electronic device comprises the processor chip of claim 7.

Images