SoC FPGA-based SRIO transmission system and transmission method

Abstract

The invention discloses an SRIO transmission system and transmission method based on an SoC FPGA, belongs to the technical field of data transmission, considers acquisition and transmission of various types of data, adopts an AXI-FULL bus with memory address access to perform data interaction, and performs random data access operation, thereby improving efficiency in a scene requiring frequent reading and writing of different addresses. A PS and PL architecture chip is used to realize an SRIO transmission system, and an FPGA of the PS and PL architecture chip is used to make a PL and PL data interaction unit comprising a big data receiving module, a big data sending module, a data type acquisition module and other modules, a data management and control unit comprising a GPIO control module, a register parameter configuration module and other modules, and an SRIO unit in the SRIO transmission system. According to the SRIO system and the data processing method thereof, an optimized data processing flow is matched, the SRIO system with multiple data interactions, high performance and high reliability is achieved, and particularly when high-speed transmission such as SRIO is processed, the data transmission efficiency of the system can be remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a SRIO transmission system and a transmission method based on SoC FPGA. Background Art

[0002] Most mainstream high-speed transmission systems now use optical communication to exchange data between devices. With the development of technology, the SRIO bus is widely used due to its advantages such as high performance, high bandwidth, and low latency. However, although the existing SRIO transmission system can be used for different types of data transmission, it can usually only collect and transmit one type of data in one data collection, which cannot meet the application scenarios that require simultaneous collection and transmission of multiple types of data. The application in this area is not mature enough. In addition, the current SRIO transmission system based on the ZYNQ architecture uses the AXIS bus and DMA controller when exchanging data between the PL and PS ends. However, the AXIS DMA requires the CPU to start the DMA controller before each transmission. Although it is suitable for streaming data, it cannot handle complex memory-mapped data access, resulting in low overall efficiency, especially in high-speed data transmission scenarios, where system performance is limited. In addition, the current SRIO transmission system does not have the ability to upgrade online, and there is a problem of insufficient system flexibility. Summary of the invention

[0003] The purpose of the present invention is to provide a SoC FPGA-based SRIO transmission system and transmission method to address the above problems, taking into account various types of data acquisition and transmission, using the AXI-FULL bus with memory address access to perform data interaction and random data access operations, thereby improving efficiency in scenarios where frequent reading and writing of different addresses is required. At the same time, the proposed system has the ability to receive large data and can perform online upgrades on local transmission units, thereby improving the flexibility of the system.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions: A SRIO transmission system based on SoC FPGA, comprising a local transmission unit including a PS plus PL architecture chip, wherein the PS plus PL architecture chip comprises a PS unit and a PL unit, wherein the PL unit comprises an SRIO unit implemented by FPGA and connected in sequence, a PL and PS data interaction unit, and a data management and control unit; The PL and PS data interaction unit includes a data acquisition module, a big data sending module, and a big data receiving module, and each module of the PL and PS data interaction unit has an AXI4-Full bus interface; The PS unit includes a CPU processing module, and the CPU processing module is connected to the data management and control unit and the DDR memory module; The PL and PS data interaction unit accesses the DDR memory module through the AXI4-Full bus; the data management and control unit is used to configure and control each module of the PL and PS data interaction unit according to the instructions of the CPU processing module; The big data sending module and the big data receiving module respectively correspond to part of the memory address storage space of the DDR memory module, and are started or closed according to the control; The memory address storage space corresponding to the big data sending module is divided into multiple storage areas, each storage area corresponds to a data type, and the data acquisition module is used to collect data of the corresponding type according to the configuration and control and store it in the corresponding storage area; The big data sending module is used to extract the collected data from the corresponding memory address storage space for caching and cross-clock domain processing according to the configuration and control; The big data receiving module is used to receive the heavy-load data sent by the DSP and store it in the corresponding memory address storage space for the CPU processing module to extract and upgrade the local transmission unit.

[0005] In the above-mentioned SRIO transmission system based on SoC FPGA, the SRIO unit is used to connect external devices, the PL and PS data interaction unit is connected to the SRIO unit, and the data management and control unit is connected to the PL and PS data interaction unit to form a data link of the SRIO transmission system between the external device and the local transmission unit.

[0006] In the above-mentioned SRIO transmission system based on SoC FPGA, the SRIO unit includes an SRIO driver module, an SRIO data sending module, and an SRIO data receiving module; The SRIO driver module is used to deserialize the serial data from the external device and send the processed data in parallel to the SRIO data receiving module, and receive the parallel collected data from the SRIO data sending module and transmit it to the external device after serialization; The SRIO data receiving module is used to receive the parallel data from the SRIO driver module, parse the data, and pass the data to the PL and PS data interaction unit according to the parsing result; The SRIO data sending module is used to send the collected data in the form of SRIO interface protocol communication packets to the SRIO driver module according to the configuration and control of the data management and control unit.

[0007] In the above-mentioned SoC FPGA-based SRIO transmission system, the PL and PS data interaction unit includes a signaling sending module and a signaling receiving module; The signaling sending module is connected to the SRIO data sending module and is used to transmit signaling data to the SRIO unit; The signaling receiving module is connected to the SRIO data receiving module, and is used to receive signaling data from an external device, and store the signaling data in a designated DDR address storage space of a DDR memory module through an AXI4-Full bus.

[0008] In the above-mentioned SoC FPGA-based SRIO transmission system, the data acquisition module includes acquisition modules of multiple different data types, and the acquisition modules of various data types are all connected to the data management and control unit to start the acquisition module of the corresponding data type according to the configuration and control of the data management and control unit to start data acquisition and store it in the corresponding storage area; The data management and control unit configures the big data sending module to extract data from the corresponding storage area.

[0009] In the above-mentioned SRIO transmission system based on SoC FPGA, the data acquisition module includes acquisition modules of at least three data types.

[0010] In the above-mentioned SRIO transmission system based on SoC FPGA, the data management and control unit includes an interrupt processing module, a GPIO control module and a register parameter configuration module; The GPIO control module is used to start or shut down the corresponding module according to the instruction of the CPU processing module; The register parameter configuration module is used to configure each module according to the instructions of the CPU processing module.

[0011] In the above-mentioned SRIO transmission system based on SoC FPGA, the PS plus PL architecture chip adopts ZYNQ chip.

[0012] A data transmission method based on the above-mentioned SoC FPGA-based SRIO transmission system, the method comprising: In response to a collection request from an external device, a signaling receiving module is started; Receive signaling data and store the signaling data to the corresponding storage space of the DDR memory module through the AXI4-Full bus; In response to the completion of the signaling data transmission, an interrupt signal between the PL unit and the PS unit is triggered to notify the CPU processing module; The CPU processing module reads signaling data from the corresponding storage space of the DDR memory module and parses parameter information and signaling requests; According to the parameter information, the register parameter configuration module sends configuration parameters to each module of the PS unit, and according to the signaling request, the GPIO control module starts one or more corresponding acquisition modules to collect data and stores it in the corresponding storage area of ​​the memory address storage space corresponding to the large data sending module, and each acquisition module corresponds to a data type; The corresponding type of acquisition module collects data and stores it in the memory address storage space corresponding to the big data sending module; In response to the end of acquisition, an interrupt signal of a corresponding type of acquisition module and a PS unit is triggered to notify the CPU processing module; The CPU processing module starts the big data sending module. The big data sending module reads the collected data from the corresponding storage area according to the configuration and caches it in the FIFO cache for cross-time domain processing, and then sends it to the SRIO data sending module. The SRIO data sending module returns the collected data to the external device through the SRIO driver module.

[0013] In the above-mentioned data transmission method of the SRIO transmission system based on SoC FPGA, the method includes: receiving signaling data regarding overloaded data information; According to the heavy data information, the big data receiving module is started by controlling the GPIO control module, and each module of the PS unit including the big data receiving module is configured by the parameter configuration module; Receive the heavy-load data and transmit the heavy-load data to the memory address storage space corresponding to the big data receiving module through the AXI4-Full bus; In response to the completion of the transmission, the CPU processing module is notified in the form of an interrupt; The CPU processing module reads the memory address storage space data corresponding to the big data receiving module and upgrades the local transmission unit.

[0014] After receiving the data, the signaling receiving module, big data receiving module, data acquisition module and other modules tell the CPU in the form of an interrupt. The CPU passes the interrupt clearing operation through the GPIO control module, so that these modules can prepare for the next data collection and reception.

[0015] The advantages of the present invention are: This solution uses PS plus PL architecture chips to implement the SRIO transmission system. The FPGA (field programmable gate array) of the PS plus PL architecture chip is used to make a PL and PL data interaction unit in the SRIO transmission system, including modules such as the big data receiving module, the big data sending module, and the data type acquisition module. It also includes a data management and control unit for modules such as the GPIO control module and the register parameter configuration module, as well as an SRIO unit. With the optimized data processing flow, a high-performance, high-reliability SRIO system with multiple data interactions is realized. Especially when processing high-speed transmission such as SRIO, the data transmission efficiency of the system can be significantly improved. This solution uses the AXI4-Full bus interface for each module in the PL and PS data interaction unit. The data access to the DDR memory mapping on the PS side is completed through the AXI4-FULL bus. The data at the specified address can be read and written according to the address. There is no DMA module, and the CPU does not need to be started. The transmission speed of various data interactions is improved, thereby improving the performance and reliability of the system. This solution provides a data acquisition module with multiple data type acquisition modules and cooperates with the GPIO control module. The GPIO control module starts the acquisition module of the corresponding data type in the data acquisition module to perform data acquisition. The system can flexibly collect multiple types of data according to needs, and the provided big data sending module provides a cache of multiple types of data for the collection of multiple data, so that the system can realize the transmission and collection of multiple types of data at the same time, rather than being limited to a single data type each time, thereby improving the data collection and transmission efficiency of the application site; This solution provides a big data receiving module with an AXI4-Full bus interface, which can efficiently receive and store heavy-loaded data. After receiving a large amount of heavy-loaded data sent by the DSP unit, it notifies the CPU processing module through an interrupt to perform data processing and online upgrade of the PS plus PL architecture chip, thereby improving the flexibility of the system and filling a gap in the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The system architecture block diagram of the SRIO transmission system based on SoC FPGA of the present invention; Figure 2 A schematic diagram of the partitioning of the DDR memory module of the SRIO transmission system based on SoC FPGA of the present invention; Figure 3 A flow chart of data collection and transmission in a system of a SRIO transmission system based on SoC FPGA of the present invention; Figure 4 The present invention is an online upgrade flow chart of a local transmission unit in a SRIO transmission system based on SoC FPGA.

[0017] Figure numerals: local transmission unit 1; PS unit 2; CPU processing module 21; PL unit 3; SRIO unit 4; SRIO driver module 41; SRIO data sending module 42; SRIO data receiving module 43; PL and PS data interaction unit 5; data acquisition module 51; big data sending module 52; big data receiving module 53; signaling sending module 54; signaling receiving module 55; data management and control unit 6; register parameter configuration module 61; interrupt processing module 62; GPIO control module 63; DDR memory module 7; external device 8; optical module 81; DSP unit 82. DETAILED DESCRIPTION

[0018] The present invention provides a SRIO transmission system based on SoC FPGA. SoC FPGA refers to an FPGA field programmable gate array that integrates the characteristics of a system-on-chip (SoC). Based on SoC FPGA, various systems with various functions can be implemented. This solution uses a ZYNQ chip including a PS unit 2 and a PL unit 3 to implement the SRIO transmission system. The PS unit 2 provides a CPU processing module 21, and the PL unit 3 provides an FPGA, such as Figure 1 As shown, this embodiment uses FPGA to implement a series of modules, thereby realizing a local transmission unit 1 of an SRIO transmission system. The local transmission unit 1 is connected to an external device 8. Specifically, the local transmission unit 1 is connected to a DSP unit 82 via an optical module 81.

[0019] The local transmission unit 1 adopts a series of modules implemented by FPGA, including: SRIO unit 4, PL and PS data interaction unit 5, data management and control unit 6.

[0020] The SRIO unit 4 includes an SRIO driving module 41 , an SRIO data sending module 42 , and an SRIO data receiving module 43 .

[0021] The PL and PS data interaction unit 5 includes a data acquisition module 51, a signaling sending module 54, a big data sending module 52, a signaling receiving module 55, and a big data receiving module 53, and each module uses an AXI4-Full bus interface.

[0022] The data management and control unit 6 is used to configure and control the modules of the PL and PS data interaction unit 5 according to the instructions of the CPU processing module 21, and transmit data access between the PL unit 3 and the PS unit 2 through the AXI4-Full protocol, including an interrupt processing module 62, a GPIO control module 63, and a register parameter configuration module 61.

[0023] The optical module 81 receives the serial data from the DSP unit 82 and sends it to the SRIO driver module 41 of the local transmission unit 1 .

[0024] The SRIO driver module 41 receives serial data from the DSP unit 82, deserializes the data, and sends the processed parallel data to the SRIO data receiving module 43; and receives parallel data from the SRIO data sending module 42 and the SRIO data receiving module 43 response packet data, serializes the data, and sends it to the DSP unit 82 through the optical module 81.

[0025] The SRIO data sending module 42 parses the control and configuration information of the register parameter configuration module 61 and the GPIO control module 63 , and sends the data to the SRIO driver module 41 in the form of a SRIO interface protocol HELLO packet.

[0026] The SRIO data receiving module 43 is used to receive parallel data from the SRIO driver module 41, parse the data, pass the data to the corresponding PL and PS data interaction unit 5 according to the parsing result, complete the SRIO response packet assembly, and transmit the SRIO response packet data to the SRIO driver module 41.

[0027] like Figure 2 As shown, the big data transmission module 52 and the big data receiving module 53 respectively correspond to part of the memory address storage space of the DDR memory module 7, and are started or closed according to the control of the CPU processing module 21. The memory address storage space of the DDR memory module 7 corresponding to the big data transmission module 52 is divided into a plurality of storage areas, each storage area corresponds to a data type, and the data acquisition module 51 is used to collect data of the corresponding type according to the configuration and control and store it in the corresponding storage area.

[0028] The data acquisition module 51 includes acquisition modules of multiple different data types, each of which corresponds to a data type and can be used to acquire various types of data with different bit widths and formats. Figure 1 Three data types are given, including data type 1 acquisition module, data type 2 acquisition module, and data type 3 acquisition module. When put into use, more acquisition modules 51 with different data types can be used. The data acquisition module 51 collects different types of data according to requirements. The CPU processing module 21 parses the 128-byte signaling from the DSP unit to determine the data type requested by the DSP unit, and then starts and controls the acquisition module of the corresponding data type through the control register parameter configuration module 61 and the GPIO control module 63.

[0029] The big data sending module 52 is used to extract the collected data from the corresponding memory address storage space for caching and cross-clock domain processing according to configuration and control.

[0030] The register parameter configuration module 61 transmits the configuration parameters sent by the PS unit 2 to the SRIO data sending module 42, the SRIO data receiving module 43 and the PL and PS data interaction unit 5 through the AXI4-Lite bus.

[0031] The GPIO control module 63 is used to transmit the relevant control information and trigger information sent by the PS unit 2 to the SRIO data sending module 42 , the SRIO data receiving module 43 , and the PL and PS data interaction unit 5 .

[0032] The interrupt processing module 62 interrupts the PS unit 2 for the PL unit 3. When the corresponding PL and PS data interaction unit 5 triggers an interrupt signal, it enters the corresponding function according to the interrupt ID and performs the next operation.

[0033] Data access between PL unit 3 and PS unit 2 and DDR memory module is transmitted through AXI4-Full protocol, and data at specified address can be read and written according to the address without CPU starting DMA module process.

[0034] The specific working process of this system includes two parts: 1. Data collection process Figure 3 As shown: The SRIO data receiving module 43 receives the DOORBELL doorbell packet from the external DSP unit 82 through the optical module 81, parses the information bit of the doorbell packet, and when it is obtained that the DOORBELL doorbell packet is followed by signaling data, the signaling receiving module 55 is started, and the signaling data begins to be received. The size of the signaling data is a fixed 128-byte data. When the SRIO data receiving module 43 parses and obtains that the information bit of the DOORBELL doorbell packet is the end of data reception, and the signaling receiving module 55 has transmitted the signaling data to the designated DDR address for storing the signaling data through the AXI4-Full bus, the interrupt signal connecting the PL unit 3 and the PS unit 2 is triggered, so that the CPU processing module 21 knows that the signaling data sent by the DSP unit 82 has been received, and waits for the CPU processing module 21 to perform the next step of processing.

[0035] The CPU processing module 21 performs data analysis by reading the data in the memory address storing the 128-byte signaling data, obtains the parameter information such as the data type, data size, data packet format, transmission rate, etc. to be collected, and sends the parameter information through the register parameter configuration module 61 through the AXI4-Lite bus, and starts the collection module of the corresponding data type to collect data through the GPIO control module 63. After the collection module of the corresponding data type collects the data of the specified size, it triggers the interrupt signal connected to the PS end of the data type collection module, telling the CPU processing module 21 that the collection is completed.

[0036] The CPU processing module 21 starts and controls the SRIO data sending module 42 and the big data sending module 52 through the GPIO control module 63 and the register parameter configuration module 61. The AXI4-Full bus reads data from the DDR memory address storing the corresponding data type through 61, and transmits the data to the big data sending module 52 through 61.

[0037] After receiving the data, the large data sending module 52 caches the data into the FIFO cache within the module for data caching and cross-clock domain processing. When the FIFO cache pool contains data that satisfies an NWRITE packet, data transmission is triggered and the data is sent to the SRIO data sending module 42.

[0038] The SRIO data transmission module 42 generates a DOORBELL doorbell packet with data start and data end information bits at the beginning and end of the data according to the NWRITE packet, and transmits the data packet to the SRIO driver module 41. The SRIO data transmission module 42 flexibly configures and sends the data packet according to the data format of the NWRITE packet, SWRITE packet and DOORBELL doorbell packet according to the type of data packet obtained by parsing the control information of the register parameter configuration module 61, until the data is sent after the data size configured by the register parameter configuration module 61 is completed, and a DOORBELL doorbell packet with an end information bit is generated to tell the DSP unit that the data has ended. The SRIO driver module 41 serializes the parallel data sent by the SRIO data transmission module 42, and finally transmits the data to the external optical module; the external optical module transmits the data to the DSP unit through the optical fiber line.

[0039] In the above data transmission process, since the PL unit 3 has a large data sending module 52 and a data acquisition module 51 corresponding to acquisition modules of various data types, and both the data acquisition module 51 and the large data sending module 52 have an AXI4-Full bus interface, the DDR memory module 7 can be accessed through the AXI4-Full bus. Therefore, data access between the PL unit 3 and the PS unit 2 can be transmitted through the AXI4-Full protocol, and the large data sending module 52 directly reads data from the corresponding memory address storage space and performs caching and cross-clock domain processing. Therefore, multiple types of data collection can be performed synchronously, and data transmission efficiency can be guaranteed at the same time.

[0040] 2. Online upgrade process Figure 4 Shown Before the DSP unit 82 sends a large amount of overloaded data, it first sends a packet of signaling data. Through this method, the CPU processing module 21 obtains parameter information such as the size of the overloaded data to be received in advance. The CPU processing module 21 controls the big data receiving module 53 through the parameter configuration module and the GPIO control module 63. When the SRIO data receiving module 43 receives the DOORBELL doorbell packet and parses it to obtain information indicating that the FPGA needs to receive a large amount of data, the big data receiving module 53 is started to prepare to receive a large amount of overloaded data. The data is transmitted to the DDR memory address corresponding to the big data receiving module 53 through the AXI4-Full bus. When the big data receiving module 53 receives the size of the overloaded data required to be received, it tells the CPU processing module 21 that the reception has been completed in the form of an interrupt. After receiving the interrupt response sent by the big data receiving module 53, the CPU directly reads the DDR memory address corresponding to the big data receiving module 53, reads the data, and performs an online upgrade of the local transmission unit 1, so that the online rapid upgrade of the local transmission unit 1 can be achieved.

[0041] The following is an example of the SRIO transmission system of this solution using the industrial automation scenario: In the field of industrial automation, it is necessary to process a variety of sensor data, such as video stream data from visual sensors, pressure data from pressure sensors, and temperature data from temperature sensors, in order to achieve precise machine control and monitoring. In the traditional field of industrial automation, these data are collected and uploaded to external devices by local acquisition control modules. This solution uses the SRIO technology through the SRIO transmission system proposed above to achieve rapid acquisition and transmission of the above data. Each sensor corresponds to a specific acquisition module. Here, the visual sensor corresponds to type 3 acquisition module, the pressure sensor corresponds to type 2 acquisition module, and the temperature sensor corresponds to type 1 acquisition module.

[0042] The DSP unit 82 sends the signaling data for acquiring the above three types of data to the local transmission unit 1, and the signaling data is stored in the corresponding storage space of the DDR memory module 7. After receiving the notification that the signaling data has been transmitted, the CPU processing module 21 directly reads the signaling data from the corresponding storage space of the DDR memory module 7, parses the signaling data, determines the type and size of the data to be collected, and controls the type 1 acquisition module, the type 2 acquisition module, and the type 3 acquisition module through the GPIO control module 63 and the register parameter configuration module 61 to collect data and store them in the type 1 data storage space, the type 2 data storage space, and the type 3 data storage space of the memory address storage space corresponding to the big data sending module. After the CPU processing module 21 learns that the collection is completed through the interrupt processing module 62, it starts the big data sending module 52, and configures the big data sending module 52 through the register parameter configuration module 61 to extract and cache the collected data from the corresponding storage space, and perform cross-time domain processing, and after integrating it into a communication packet, it is sent to the external device through the SRIO sending module 42 and the SRIO driver module 41 to complete data collection and transmission, thereby realizing the rapid and efficient simultaneous collection and transmission of the three types of sensor data.

[0043] The applications in other fields are similar, such as medical imaging, and will not be elaborated here.

[0044] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

[0045] Although this article uses more terms such as local transmission unit 1; PS unit 2; CPU processing module 21; PL unit 3; SRIO unit 4; SRIO driver module 41; SRIO data sending module 42; SRIO data receiving module 43; PL and PS data interaction unit 5; data acquisition module 51; big data sending module 52; big data receiving module 53; signaling sending module 54; signaling receiving module 55; data management and control unit 6; register parameter configuration module 61; interrupt processing module 62; GPIO control module 63; DDR memory module 7; external device 8; optical module 81; DSP unit 82, it does not exclude the possibility of using other terms. These terms are used only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional restrictions is contrary to the spirit of the present invention.

Claims

1. An SRIO transmission system based on SoC FPGA, comprising a local transmission unit (1) including a PS plus PL architecture chip, wherein the PS plus PL architecture chip comprises a PS unit (2) and a PL unit (3), characterized in that: The PL unit (3) comprises an SRIO unit (4) implemented by FPGA and connected in sequence, a PL and PS data interaction unit (5), and a data management and control unit (6); The PL and PS data interaction unit (5) comprises a data acquisition module (51), a large data transmission module (52), and a large data reception module (53), and each module of the PL and PS data interaction unit (5) has an AXI4-Full bus interface; The PS unit (2) comprises a CPU processing module (21), and the CPU processing module (21) is connected to the data management and control unit (6) and the DDR memory module (7); The PL and PS data interaction unit (5) accesses the DDR memory module (7) via the AXI4-Full bus; The data management and control unit (6) is used to configure and control each module of the PL and PS data interaction unit (5) according to the instructions of the CPU processing module (21); The big data sending module (52) and the big data receiving module (53) respectively correspond to part of the memory address storage space of the DDR memory module (7), and are started or shut down according to the control; The memory address storage space corresponding to the big data transmission module (52) is divided into a plurality of storage areas, each storage area corresponds to a data type, and the data acquisition module (51) is used to acquire data of a corresponding type according to configuration and control and store it in a corresponding storage area; The big data transmission module (52) is used to extract the collected data from the corresponding memory address storage space for caching and cross-clock domain processing according to configuration and control; The big data receiving module (53) is used to receive the heavy-load data sent by the DSP and store it in the corresponding memory address storage space.

2. The SRIO transmission system based on SoC FPGA according to claim 1, characterized in that: The SRIO unit (4) is used to connect to an external device (8), the PL and PS data interaction unit (5) is connected to the SRIO unit (4), and the data management and control unit (6) is connected to the PL and PS data interaction unit (5) to form a data link of the SRIO transmission system between the external device (8) and the local transmission unit (1).

3. The SRIO transmission system based on SoC FPGA according to claim 2, characterized in that: The SRIO unit (4) comprises an SRIO driving module (41), an SRIO data sending module (42), and an SRIO data receiving module (43); The SRIO driver module (41) is used to perform deserialization processing on serial data from the external device (8), and send the processed data in parallel to the SRIO data receiving module (43), and receive the parallel collected data from the SRIO data sending module (42), perform serialization processing on the data, and then transmit it to the external device (8); An SRIO data receiving module (43) is used to receive parallel data from the SRIO driving module (41), parse the data, and transmit the data to the PL and PS data interaction unit (5) according to the parsing result; The SRIO data sending module (42) is used to send the collected data in the form of SRIO interface protocol communication packets to the SRIO driving module (41) according to the configuration and control of the data management and control unit (6).

4. The SRIO transmission system based on SoC FPGA according to claim 3, characterized in that: The PL and PS data interaction unit (5) further comprises a signaling sending module (54) and a signaling receiving module (55); The signaling sending module (54) is connected to the SRIO data sending module (42) and is used to transmit signaling data to the SRIO unit (4); The signaling receiving module (55) is connected to the SRIO data receiving module (43) and is used to receive signaling data from an external device (8) and store the signaling data in a designated DDR address storage space of a DDR memory module (7) via an AXI4-Full bus.

5. The SRIO transmission system based on SoC FPGA according to claim 4, characterized in that: The data acquisition module (51) includes a plurality of acquisition modules of different data types, and the acquisition modules of various data types are all connected to the data management and control unit (6), so that the acquisition module of the corresponding data type is started to start data acquisition according to the configuration and control of the data management and control unit (6), and the data is stored in the corresponding storage area; The data management and control unit (6) configures a large data transmission module (52) to extract data from a corresponding storage area.

6. The SRIO transmission system based on SoC FPGA according to claim 4, characterized in that: The data acquisition module (51) includes acquisition modules for at least three data types.

7. The SRIO transmission system based on SoC FPGA according to claim 4, characterized in that: The data management and control unit (6) comprises an interrupt processing module (62), a GPIO control module (63) and a register parameter configuration module (61); The GPIO control module (63) is used to start or shut down the corresponding module according to the instruction of the CPU processing module (21); The register parameter configuration module (61) is used to configure each module according to the instructions of the CPU processing module (21).

8. The SRIO transmission system based on SoC FPGA according to any one of claims 1 to 6, characterized in that: The PS plus PL architecture chip adopts ZYNQ chip.

9. A data transmission method based on the SoC FPGA-based SRIO transmission system according to any one of claims 1 to 7, characterized in that: The method includes: In response to a collection request from an external device (8), a signaling receiving module (55) is started; Receive signaling data, and store the signaling data into the corresponding storage space of the DDR memory module (7) via the AXI4-Full bus; In response to the completion of the signaling data transmission, an interrupt signal is triggered to notify the CPU processing module (21); The CPU processing module (21) reads signaling data from the corresponding storage space of the DDR memory module (7) and parses parameter information and signaling requests; Sending configuration parameters to each module of the PS unit (2) through a register parameter configuration module (61) according to the parameter information, starting one or more corresponding acquisition modules through a GPIO control module (63) to collect data according to a signaling request and storing the data in a storage area corresponding to a memory address storage space corresponding to a large data transmission module (52), wherein each acquisition module corresponds to a data type; In response to the end of the acquisition, an interrupt signal is triggered to notify the CPU processing module (21); The CPU processing module (21) starts the big data transmission module (52), which reads the collected data from the corresponding storage area according to the configuration and caches it in the FIFO cache for cross-time domain processing, and then sends it to the SRIO data transmission module (42). The SRIO data transmission module (42) returns the collected data to the external device (8) through the SRIO area module.

10. The data transmission method according to claim 9, characterized in that: The method includes: receiving signaling data regarding overloaded data information; Controlling the start of the big data receiving module (53) through the GPIO control module (63) according to the heavy data information, and configuring each module of the PS unit (2) including the big data receiving module (53) through the parameter configuration module; Receiving the heavy-load data, and transmitting the heavy-load data to the memory address storage space corresponding to the large data receiving module (53) via the AXI4-Full bus; In response to the completion of the transmission, the CPU processing module is notified in the form of an interrupt (21); The CPU processing module (21) reads the memory address storage space data corresponding to the big data receiving module (53) and performs an upgrade of the local transmission unit (1).

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