An SRIO Transmission System and Transmission Method Based on SoC FPGA

Abstract

The present invention discloses an SRIO transmission system and a transmission method based on an SoC FPGA, belonging to the technical field of data transmission. Considering various types of data acquisition and transmission, the AXI-FULL bus, which is a way with memory address access, is adopted for data interaction, and random data access operations are performed, so as to improve the efficiency in scenarios where different addresses need to be frequently read and written; an SRIO transmission system is implemented using a PS+PL architecture chip. The FPGA of the PS+PL architecture chip is used in the SRIO transmission system to make a PL-to-PL data interaction unit including modules such as a large data receiving module, a large data sending module, and a data type acquisition module, a data management and control unit including modules such as a GPIO control module and a register parameter configuration module, and an SRIO unit. With an optimized data processing flow, a high-performance and highly reliable SRIO system with multiple data interactions is realized. Especially when processing high-speed transmissions such as SRIO, the data transmission efficiency of the system can be significantly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and particularly relates to an SRIO transmission system and a transmission method based on an SoC FPGA. Background Art

[0002] Most of the current mainstream high-speed transmission systems use optical communication to perform data interaction between devices. With the development of technology, the SRIO bus is widely used due to its advantages such as high performance, high bandwidth, and low latency. However, although the existing SRIO transmission systems can be used for different types of data transmission, in one data acquisition, usually only one type of data can be acquired and transmitted, which cannot meet the application scenarios that require simultaneous acquisition and transmission of multiple types of data, and the application in this aspect is not yet mature. And currently, for the SRIO transmission system based on the ZYNQ architecture, when performing data interaction between the PL side and the PS side, the AXIS bus and the DMA controller are used. However, the AXIS DMA needs the CPU to start the DMA controller before each transmission. Although it is suitable for streaming data, it cannot handle complex memory-mapped data access, resulting in low overall efficiency, especially in high-speed data transmission scenarios, the system performance is limited. In addition, the current SRIO transmission systems do not have the ability of online upgrade, and there is a problem of insufficient system flexibility. Summary of the Invention

[0003] The object of the present invention is to provide an SRIO transmission system and a transmission method based on an SoC FPGA for the above problems. Considering the acquisition and transmission of multiple types of data, the AXI-FULL bus, which is a way with memory address access, is adopted for data interaction, and random data access operations are performed, so as to improve the efficiency in scenarios that require frequent reading and writing of different addresses. At the same time, the proposed system has the ability to receive large data, can perform online upgrade on the local transmission unit, and improves the flexibility of the system.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] An SRIO transmission system based on an SoC FPGA includes a local transmission unit comprising a PS + PL architecture chip. The PS + PL architecture chip includes a PS unit and a PL unit. The PL unit includes an SRIO unit, a PL-PS data interaction unit, and a data management and control unit, which are implemented by an FPGA and are connected in sequence.

[0006] The PL-PS data interaction unit includes a data acquisition module, a large data sending module, and a large data receiving module, and each module of the PL-PS data interaction unit has an AXI4-Full bus interface.

[0007] The described PS unit includes a CPU processing module, and the CPU processing module is connected to the data management and control unit and the DDR memory module;

[0008] The PL and PS data interaction unit accesses the DDR memory module through the AXI4-Full bus; the data management and control unit is used to configure and control each module of the PL and PS data interaction unit according to the instructions of the CPU processing module;

[0009] The big data sending module and the big data receiving module respectively correspond to partial memory address storage spaces of the DDR memory module, and are started or shut down according to control;

[0010] The memory address storage space corresponding to the big data sending module is divided into multiple storage areas, each storage area corresponds to a data type, and the data acquisition module is used to acquire corresponding type of data according to configuration and control and store it into the corresponding storage area;

[0011] The big data sending module is used to extract the acquired data from the corresponding memory address storage space according to configuration and control for caching and cross-clock domain processing;

[0012] The big data receiving module is used to receive the overloaded data sent by the DSP, and store it into the corresponding memory address storage space for the CPU processing module to extract and upgrade the local transmission unit.

[0013] In the above SRIO transmission system based on SoC FPGA, the SRIO unit is used to connect to an external device, the PL and PS data interaction unit is connected to the SRIO unit, and the data management and control unit is connected to the PL and PS data interaction unit to form a data link of the SRIO transmission system between the external device and the local transmission unit.

[0014] In the above SRIO transmission system based on SoC FPGA, the SRIO unit includes an SRIO driver module, an SRIO data sending module, and an SRIO data receiving module;

[0015] The SRIO driver module is used to deserialize the serial data from an external device, and send the processed data in parallel to the SRIO data receiving module, and receive the parallel acquired data of the SRIO data sending module and perform serialization processing on it and then transmit it to the external device;

[0016] The SRIO data receiving module is used to receive the parallel data from the SRIO driver module, parse the data, and transfer the data to the PL and PS data interaction unit according to the parsing result;

[0017] The SRIO data sending module is used to form the collected data into communication packets in the form of the SRIO interface protocol according to the configuration and control of the data management and control unit, and send them to the SRIO driver module.

[0018] In the above SRIO transmission system based on SoC FPGA, the PL-PS data interaction unit includes a signaling sending module and a signaling receiving module;

[0019] The signaling sending module is connected to the SRIO data sending module and is used to transmit signaling data to the SRIO unit;

[0020] The signaling receiving module is connected to the SRIO data receiving module and is used to receive signaling data from external devices, and store the signaling data in the specified DDR address storage space of the DDR memory module through the AXI4-Full bus.

[0021] In the above SRIO transmission system based on SoC FPGA, the data acquisition module includes acquisition modules of various different data types, and the acquisition modules of various data types are all connected to the data management and control unit to start data acquisition of the corresponding data type according to the configuration and control of the data management and control unit, and store it in the corresponding storage area;

[0022] The data management and control unit configures the big data sending module to extract the data in the corresponding storage area.

[0023] In the above SRIO transmission system based on SoC FPGA, the data acquisition module includes at least three types of data acquisition modules.

[0024] In the above SRIO transmission system based on SoC FPGA, the data management and control unit includes an interrupt processing module, a GPIO control module, and a register parameter configuration module;

[0025] The GPIO control module is used to start or close the corresponding module according to the instructions of the CPU processing module;

[0026] The register parameter configuration module is used to configure each module according to the instructions of the CPU processing module.

[0027] In the above SRIO transmission system based on SoC FPGA, the PS+PL architecture chip uses a ZYNQ chip.

[0028] A data transmission method based on the above SRIO transmission system based on SoC FPGA, the method includes:

[0029] Start the signaling receiving module in response to the acquisition request of an external device;

[0030] Receive signaling data and store the signaling data in the corresponding storage space of the DDR memory module through the AXI4-Full bus;

[0031] In response to the end of the signaling data transfer, trigger an interrupt signal between the PL unit and the PS unit to notify the CPU processing module;

[0032] The CPU processing module reads the signaling data from the corresponding storage space of the DDR memory module and parses the parameter information and signaling requests;

[0033] According to the parameter information, send configuration parameters to each module of the PS unit through the register parameter configuration module, and according to the signaling request, start one or more corresponding acquisition modules through the GPIO control module to collect data and store it in the corresponding storage area of the memory address storage space of the big data sending module. Each acquisition module corresponds to a data type;

[0034] The corresponding type of acquisition module collects data and stores it in the corresponding memory address storage space of the big data sending module;

[0035] In response to the end of the acquisition, trigger an interrupt signal between the corresponding type of acquisition module and the PS unit to notify the CPU processing module;

[0036] The CPU processing module starts the big data sending module. The big data sending module reads the acquisition data from the corresponding storage area according to the configuration, caches it in the FIFO cache for cross-time-domain processing, and then sends it to the SRIO data sending module. The SRIO data sending module returns the acquisition data to the external device through the SRIO driver module.

[0037] In the above data transmission method of the SRIO transmission system based on SoC FPGA, the method includes:

[0038] Receive signaling data regarding overloaded data information;

[0039] According to the overloaded data information, control the big data receiving module to start through the GPIO control module, and configure each module of the PS unit including the big data receiving module through the parameter configuration module;

[0040] Receive overloaded data and transfer the overloaded data to the corresponding memory address storage space of the big data receiving module through the AXI4-Full bus;

[0041] In response to the completion of the transfer, notify the CPU processing module in the form of an interrupt;

[0042] The CPU processing module upgrades the local transmission unit by reading the data in the memory address storage space corresponding to the large data receiving module.

[0043] After receiving data, modules such as the signaling receiving module, large data receiving module, and data acquisition module tell the CPU in the form of an interrupt. Then, the CPU passes the operation of clearing the interrupt through the GPIO control module, enabling these modules to prepare for the next data acquisition and reception.

[0044] The advantages of the present invention are as follows:

[0045] This solution uses a PS + PL architecture chip to implement an SRIO transmission system. The FPGA (Field Programmable Gate Array) of the PS + PL architecture chip is used in the SRIO transmission system to create a PL - PL data interaction unit including modules such as a large data receiving module, a large data sending module, and a data type acquisition module, a data management and control unit including modules such as a GPIO control module and a register parameter configuration module, and an SRIO unit. With an optimized data processing flow, a high - performance and highly reliable SRIO system with multiple data interactions is realized. Especially when processing high - speed transmissions such as SRIO, the data transmission efficiency of the system can be significantly improved.

[0046] This solution uses the AXI4 - Full bus interface for each module in the PL - PS data interaction unit. Through the AXI4 - FULL bus, data access to the DDR memory map on the ps side is completed. Data at a specified address can be read and written according to the address. There is no DMA module and no need for the CPU to start, which improves the transmission speed of multiple data interactions and thus improves the performance and reliability of the system.

[0047] This solution provides a data acquisition module with multiple data type acquisition modules and cooperates with the GPIO control module. The GPIO control module starts the corresponding data type acquisition module in the data acquisition module to perform data acquisition. The system can flexibly acquire various types of data according to requirements. Moreover, the provided large data sending module provides a cache for various types of data for the acquisition of multiple data, enabling the system to realize the transmission and acquisition of multiple types of data simultaneously, rather than being limited to a single data type each time, thereby improving the data acquisition and transmission efficiency at the application site.

[0048] This solution provides a large data receiving module with an AXI4 - Full bus interface, which can efficiently receive and store heavy - load data. After receiving a large amount of heavy - load data sent by the DSP unit, it notifies the CPU processing module to perform data processing and the online upgrade of the PS + PL architecture chip in the form of an interrupt, improving the flexibility of the system and filling the market gap. Description of the Drawings

[0049] Figure 1 This is the system architecture block diagram of the SRIO transmission system based on SoC FPGA of the present invention;

[0050] Figure 2 This is the partition schematic diagram of the DDR memory module of the system of the SRIO transmission system based on SoC FPGA of the present invention;

[0051] Figure 3 This is the data acquisition and transmission flow chart in the system of the SRIO transmission system based on SoC FPGA of the present invention;

[0052] Figure 4 This is the online upgrade flow chart of the local transmission unit in the system of the SRIO transmission system based on SoC FPGA of the present invention.

[0053] Reference numerals: local transmission unit 1; PS unit 2; CPU processing module 21; PL unit 3; SRIO unit 4; SRIO driver module 41; SRIO data sending module 42; SRIO data receiving module 43; PL-PS data interaction unit 5; data acquisition module 51; big data sending module 52; big data receiving module 53; signaling sending module 54; signaling receiving module 55; data management and control unit 6; register parameter configuration module 61; interrupt processing module 62; GPIO control module 63; DDR memory module 7; external device 8; optical module 81; DSP unit 82. Detailed implementation manners

[0054] The present invention provides an SRIO transmission system based on SoC FPGA. SoC FPGA refers to a field programmable gate array of FPGA integrated with system-on-chip (SoC) characteristics. Based on SoC FPGA, various systems with various functions can be realized. This solution uses a ZYNQ chip including two parts, a PS unit 2 and a PL unit 3, to implement the SRIO transmission system. The PS unit 2 provides a CPU processing module 21, and the PL unit 3 provides an FPGA. As Figure 1 shown, in this embodiment, the FPGA is used to implement a series of modules, and then a local transmission unit 1 of an SRIO transmission system is implemented. The local transmission unit 1 is connected to an external device 8. Specifically, the local transmission unit 1 is connected to a DSP unit 82 through an optical module 81.

[0055] A series of modules implemented by the local transmission unit 1 using an FPGA include: an SRIO unit 4, a PL-PS data interaction unit 5, and a data management and control unit 6.

[0056] The SRIO unit 4 includes an SRIO driver module 41, an SRIO data sending module 42, and an SRIO data receiving module 43.

[0057] The PL and PS data interaction unit 5 includes a data acquisition module 51, a signaling sending module 54, a big data sending module 52, a signaling receiving module 55, and a big data receiving module 53. The AXI4-Full bus interface is used inside each module.

[0058] The data management and control unit 6 is used to configure and control each module of the PL and PS data interaction unit 5 according to the instructions of the CPU processing module 21, and transmit data access between the PL unit 3 and the PS unit 2 through the AXI4-Full protocol, including an interrupt processing module 62, a GPIO control module 63, and a register parameter configuration module 61.

[0059] The optical module 81 receives serial data from the DSP unit 82 and sends it to the SRIO driver module 41 of the local transmission unit 1.

[0060] The SRIO driver module 41 receives serial data from the DSP unit 82, performs deserialization processing on the data, and sends the processed parallel data to the SRIO data receiving module 43; and receives parallel data of response packet data from the SRIO data sending module 42 and the SRIO data receiving module 43, performs data serialization, and sends it to the DSP unit 82 through the optical module 81.

[0061] The SRIO data sending module 42 parses the control and configuration information of the register parameter configuration module 61 and the GPIO control module 63, and forms the data into the form of a HELLO packet of the SRIO interface protocol and sends it to the SRIO driver module 41.

[0062] The SRIO data receiving module 43 is used to receive parallel data from the SRIO driver module 41, parse the data, transfer the data to the corresponding PL and PS data interaction unit 5 according to the parsing result, complete the packet assembly of the SRIO response packet, and transmit the SRIO response packet data to the SRIO driver module 41.

[0063] As Figure 2 shown, the big data sending module 52 and the big data receiving module 53 respectively correspond to partial memory address storage spaces of the DDR memory module 7, and are started or closed under the control of the CPU processing module 21. The memory address storage space of the DDR memory module 7 corresponding to the big data sending module 52 is divided into multiple storage areas, and each storage area corresponds to a data type. The data acquisition module 51 is used to collect corresponding type of data according to the configuration and control and store it in the corresponding storage area.

[0064] The data acquisition module 51 includes acquisition modules for various different data types. Each acquisition module corresponds to one data type and can be used to acquire various types of data with different bit widths and formats. Figure 1 Three data types are given in Figure 1 , including the data type 1 acquisition module, the data type 2 acquisition module, and the data type 3 acquisition module. More acquisition modules 51 of different data types can be used when put into use. The data acquisition module 51 acquires different types of data according to requirements. The CPU processing module 21 determines the data type requested by the DSP unit by parsing the 128-byte signaling from the DSP unit, and then starts and controls the corresponding data type acquisition module through the control register parameter configuration module 61 and the GPIO control module 63.

[0065] The big data sending module 52 is used to extract the acquired data from the corresponding memory address storage space for caching and cross-clock domain processing according to the configuration and control.

[0066] The register parameter configuration module 61 transfers the configuration parameters issued by the PS unit 2 to the SRIO data sending module 42, the SRIO data receiving module 43, and the PL and PS data interaction unit 5 through the AXI4-Lite bus.

[0067] The GPIO control module 63 is used to transfer the relevant control information and trigger information issued by the PS unit 2 to the SRIO data sending module 42, the SRIO data receiving module 43, and the PL and PS data interaction unit 5.

[0068] The interrupt processing module 62 interrupts the PS unit 2 by the PL unit 3. When the corresponding PL and PS data interaction unit 5 triggers an interrupt signal, it enters the corresponding function according to the interrupt ID for the next operation.

[0069] Data access between the PL unit 3, the PS unit 2, and the DDR memory module is transmitted through the AXI4-Full protocol. Data at the specified address can be read and written according to the address without the need for the CPU to start the DMA module process.

[0070] The specific working process of this system includes two parts:

[0071] 1. The data acquisition process is as Figure 3 shown:

[0072] The SRIO data receiving module 43 receives the DOORBELL packet from the external DSP unit 82 through the optical module 81, parses the information bits of the DOORBELL packet. When it is obtained that the data following the DOORBELL packet is signaling data, the signaling receiving module 55 is started, and the signaling data starts to be received. The size of the signaling data is fixed at 128 bytes. When the SRIO data receiving module 43 parses and obtains that the information bits of the DOORBELL packet are for the end of data reception, and the signaling receiving module 55 has transmitted the signaling data to the DDR address specified for storing the signaling data through the AXI4-Full bus, an interrupt signal connecting the PL unit 3 and the PS unit 2 is triggered, so that the CPU processing module 21 knows that the signaling data sent by the DSP unit 82 has been received at this time, and waits for the CPU processing module 21 to perform the next processing.

[0073] The CPU processing module 21 reads the data in the memory address storing 128-byte signaling data, performs data analysis, and obtains parameter information such as the data type, data size, data packet format, and transmission rate that need to be collected. The parameter information is sent down through the AXI4-Lite bus by the register parameter configuration module 61, and at the same time, the acquisition module corresponding to the data type is started through the GPIO control module 63 to perform data acquisition. After the acquisition module corresponding to the data type has acquired the specified size of data, an interrupt signal connecting the acquisition module of this data type and the PS side is triggered to tell the CPU processing module 21 that the acquisition is complete.

[0074] The CPU processing module 21 jointly starts to control the SRIO data sending module 42 and the large data sending module 52 through the GPIO control module 63 and the register parameter configuration module 61. The AXI4-Full bus reads the data from the DDR memory address storing the corresponding data type through 61 and transmits it to the large data sending module 52 through 61.

[0075] After receiving the data, the large data sending module 52 caches the data into the FIFO cache in the module for data caching and cross-clock domain processing. When the FIFO cache pool stores data sufficient for one NWRITE packet, data transmission is triggered, and the data is sent to the SRIO data sending module 42.

[0076] The SRIO data sending module 42 packages the data into NWRITE packets, and generates DOORBELL packets with data start and data end information bits at the beginning and end of the data respectively, and transmits the data packets to the SRIO driver module 41. Among them, the SRIO data sending module 42 flexibly configures and sends according to the data formats of NWRITE packets, SWRITE packets and DOORBELL packets according to the type of data packets parsed from the control information of the register parameter configuration module 61. Until the data size configured by the register parameter configuration module 61 is sent, a DOORBELL packet with an end information bit is generated to tell the DSP unit the end of data sending. The SRIO driver module 41 serializes the parallel data sent by the SRIO data sending module 42, and finally transmits the data to the external optical module; the external optical module transmits the data to the DSP unit through the optical fiber cable.

[0077] In the above data transmission process, since the PL unit 3 has a large data sending module 52 and a data acquisition module 51 corresponding to the acquisition modules of various data types, and both the data acquisition module 51 and the large data sending module 52 have AXI4-Full bus interfaces and can access the DDR memory module 7 through the AXI4-Full bus. Therefore, the data access between the PL unit 3 and the PS unit 2 can be transmitted through the AXI4-Full protocol, and the large data sending module 52 directly reads data from the corresponding memory address storage space, caches and performs cross-clock domain processing. Therefore, multiple types of data acquisitions can be synchronized, and at the same time, the data transmission efficiency can be guaranteed.

[0078] 2. The online upgrade process is as Figure 4 shown

[0079] Before the DSP unit 82 sends a large amount of overloaded data, it first sends a packet of signaling data. By this method, the CPU processing module 21 can obtain parameter information such as the amount of overloaded data to be received in advance. The CPU processing module 21 controls the large data receiving module 53 through the parameter configuration module and the GPIO control module 63. When the SRIO data receiving module 43 receives the DOORBELL packet and parses it to obtain information indicating that the FPGA needs to receive a large amount of data, it starts the large data receiving module 53 to prepare to receive a large amount of overloaded data. The data is transmitted to the corresponding DDR memory address of the large data receiving module 53 through the AXI4-Full bus. When the large data receiving module 53 receives the amount of overloaded data to be received, it tells the CPU processing module 21 that the reception is complete in the form of an interruption. After receiving the interruption response sent by the large data receiving module 53, the CPU directly reads the corresponding DDR memory address of the large data receiving module 53, reads out the data, and performs the online upgrade of the local transmission unit 1. In this way, the online rapid upgrade of the local transmission unit 1 can be realized.

[0080] The following is an exemplary description of the SRIO transmission system of this solution in the scenario of the industrial automation field:

[0081] In the industrial automation field, it is necessary to process various sensor data, such as the video stream data of visual sensors, the pressure data of pressure sensors, and the temperature data of temperature sensors, to achieve precise machine control and monitoring. In the traditional industrial automation field, this data is collected and controlled by the local acquisition control module and uploaded to external devices. Through the SRIO transmission system proposed above, this solution uses SRIO technology to achieve the rapid acquisition and transmission of the foregoing data. Each sensor corresponds to a specific acquisition module. Here, the visual sensor corresponds to the type 3 acquisition module, the pressure sensor corresponds to the type 2 acquisition module, and the temperature sensor corresponds to the type 1 acquisition module.

[0082] The DSP unit 82 sends signaling data that needs to obtain the foregoing three types of data to the local transmission unit 1, and the signaling data is stored in the corresponding storage space of the DDR memory module 7. After the CPU processing module 21 receives the notification that the signaling data transmission is completed, it directly reads the signaling data from the corresponding storage space of the DDR memory module 7, parses the signaling data, determines information such as the data types and sizes that need to be collected, and controls the type 1 acquisition module, type 2 acquisition module, and type 3 acquisition module to collect data through the GPIO control module 63 and the register parameter configuration module 61, and stores them in the type 1 data storage space, type 2 data storage space, and type 3 data storage space corresponding to the memory address storage space of the big data sending module respectively. After the CPU processing module 21 learns through the interrupt processing module 62 that the acquisition is completed, it starts the big data sending module 52, and configures the big data sending module 52 through the register parameter configuration module 61 to extract and cache the acquired data from the corresponding storage space, and perform cross-time domain processing. After integrating them into communication packets, they are sent to external devices through the SRIO sending module 42 and the SRIO driving module 41 to complete data acquisition and transmission, realizing the fast and efficient simultaneous acquisition and transmission of three types of sensor data.

[0083] The application in other fields is similar, such as the medical imaging field, etc., which will not be elaborated here.

[0084] The specific embodiments described in this article are only examples to illustrate the spirit of the present invention. Those skilled in the art of the present invention can make various modifications or supplements to the described specific embodiments or use similar methods for substitution, but will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

[0085] Although terms such as local transmission unit 1; PS unit 2; CPU processing module 21; PL unit 3; SRIO unit 4; SRIO driving module 41; SRIO data sending module 42; SRIO data receiving module 43; PL and PS data interaction unit 5; data acquisition module 51; big data sending module 52; big data receiving module 53; signaling sending module 54; signaling receiving module 55; data management and control unit 6; register parameter configuration module 61; interrupt processing module 62; GPIO control module 63; DDR memory module 7; external device 8; optical module 81; DSP unit 82 are used more in this article, the possibility of using other terms is not excluded. Using these terms is only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional limitation is contrary to the spirit of the present invention.

Claims

1. An SRIO transmission system based on an SoC FPGA, including a local transmission unit (1) containing a PS + PL architecture chip, where the PS + PL architecture chip includes a PS unit (2) and a PL unit (3), characterized in that, The described PL unit (3) includes an SRIO unit (4), a PL-PS data interaction unit (5), and a data management and control unit (6) that are implemented using an FPGA and are connected in sequence; The described PL-PS data interaction unit (5) includes a data acquisition module (51), a large data sending module (52), and a large data receiving module (53), and each module of the PL-PS data interaction unit (5) has an AXI4-Full bus interface; The described PS unit (2) includes a CPU processing module (21), and the CPU processing module (21) is connected to the data management and control unit (6) and the DDR memory module (7); The PL-PS data interaction unit (5) accesses the DDR memory module (7) through the AXI4-Full bus; The data management and control unit (6) is used to configure and control each module of the PL-PS data interaction unit (5) according to the instructions of the CPU processing module (21); The large data sending module (52) and the large data receiving module (53) respectively correspond to partial memory address storage spaces of the DDR memory module (7), and are started or shut down according to control; The memory address storage space corresponding to the large data sending module (52) is divided into multiple storage areas, each storage area corresponding to a data type, and the data acquisition module (51) is used to acquire corresponding type of data according to configuration and control and store it into the corresponding storage area; The large data sending module (52) is used to extract the acquired data from the corresponding memory address storage space according to configuration and control for caching and cross-clock domain processing; The large data receiving module (53) is used to receive the reload data sent by the DSP and store it into the corresponding memory address storage space; The described data management and control unit (6) includes an interrupt processing module (62), a GPIO control module (63), and a register parameter configuration module (61); The GPIO control module (63) is used to start or shut down the corresponding module according to the instructions of the CPU processing module (21); The register parameter configuration module (61) is used to configure each module according to the instructions of the CPU processing module (21).

2. The SRIO transmission system based on SoC FPGA according to claim 1, wherein The SRIO unit (4) is used to connect to an external device (8), the PL-PS data interaction unit (5) is connected to the SRIO unit (4), and the data management and control unit (6) is connected to the PL-PS data interaction unit (5) to form a data link of the SRIO transmission system between the external device (8) and the local transmission unit (1).

3. The SRIO transmission system based on SoC FPGA according to claim 2, characterized in that, The described SRIO unit (4) includes an SRIO driver module (41), an SRIO data sending module (42), and an SRIO data receiving module (43); The SRIO driver module (41) is used to deserialize the serial data from the external device (8), and parallelly send the processed data to the SRIO data receiving module (43), and receive the parallel acquired data of the SRIO data sending module (42) and serialize it before transmitting it to the external device (8); The SRIO data receiving module (43) is used to receive parallel data from the SRIO driving module (41), parse the data, and transfer the data to the PL and PS data interaction unit (5) according to the parsing result; The SRIO data sending module (42) is used to form the collected data into a communication packet in the form of an SRIO interface protocol according to the configuration and control of the data management and control unit (6) and send it to the SRIO driving module (41).

4. The SRIO transmission system based on SoC FPGA according to claim 3, wherein The PL and PS data interaction unit (5) further includes a signaling sending module (54) and a signaling receiving module (55); The signaling sending module (54) is connected to the SRIO data sending module (42) and is used to transmit signaling data to the SRIO unit (4); The signaling receiving module (55) is connected to the SRIO data receiving module (43) and is used to receive signaling data from an external device (8) and store the signaling data in a specified DDR address storage space of the DDR memory module (7) through the AXI4-Full bus.

5. The SRIO transmission system based on SoC FPGA according to claim 4, characterized in that, The data acquisition module (51) includes acquisition modules of various different data types, and the acquisition modules of various data types are all connected to the data management and control unit (6) to start data acquisition of the corresponding data type according to the configuration and control of the data management and control unit (6) and store it in the corresponding storage area; The data management and control unit (6) configures the big data sending module (52) to extract data from the corresponding storage area.

6. The SRIO transmission system based on SoC FPGA according to claim 4, characterized in that, The data acquisition module (51) includes at least three types of data acquisition modules.

7. The SRIO transmission system based on SoC FPGA according to any one of claims 1-6, characterized in that The PS plus PL architecture chip uses a ZYNQ chip.

8. A data transmission method for a SRIO transmission system based on the SoC FPGA according to any one of claims 1-7, characterized in that, The method includes: Starting the signaling receiving module (55) in response to an acquisition request from an external device (8); Receiving signaling data and storing the signaling data in a corresponding storage space of the DDR memory module (7) through the AXI4-Full bus; Triggering an interrupt signal to notify the CPU processing module (21) in response to the end of the transfer of the signaling data; The CPU processing module (21) reads the signaling data from a corresponding storage space of the DDR memory module (7) and parses the parameter information and the signaling request; Sending configuration parameters to each module of the PS unit (2) through the register parameter configuration module (61) according to the parameter information, and starting one or more corresponding acquisition modules for data acquisition according to the signaling request through the GPIO control module (63) and storing the data in a corresponding storage area of a corresponding memory address storage space of the big data sending module (52), and each acquisition module corresponds to one data type; Triggering an interrupt signal to notify the CPU processing module (21) in response to the end of the acquisition; The CPU processing module (21) starts the big data sending module (52). The big data sending module (52) reads the collected data from the corresponding storage area according to the configuration, caches it in the FIFO buffer for cross-time-domain processing, and then sends it to the SRIO data sending module (42). The SRIO data sending module (42) returns the collected data to the external device (8) through the SRIO area module; Receive signaling data regarding the overloaded data information; According to the overloaded data information, control the start of the big data receiving module (53) through the GPIO control module (63), and configure each module in the PL unit (3) through the register parameter configuration module (61); Receive the overloaded data, and transfer the overloaded data to the memory address storage space corresponding to the big data receiving module (53) through the AXI4-Full bus; In response to the completion of the transfer, notify the CPU processing module (21) in the form of an interrupt; The CPU processing module (21) reads the data in the memory address storage space corresponding to the big data receiving module (53) and upgrades the local transfer unit (1).

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