Verification system, verification method and program product of single-photon distance measurement chip
By designing multiple functional verification environment layers and adopting UVM verification environments, the existing Verilog verification platform has solved the problems of poor reusability and low efficiency in single-photon ranging chip verification, achieving efficient and stable chip verification, shortening the design and development cycle.
Patent Information
- Application Number
- CN202510096398.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-05-13
AI Technical Summary
The existing Verilog verification platform has problems such as poor reusability and inefficiency in the verification of single-photon ranging chips, which is difficult to fully cover all practical application scenarios, resulting in inefficient verification and prolonged design and development cycle.
It provides a verification system for a single photon ranging chip, including testing components, chip verification environment layer, chip verification objects and verification interfaces for each functional module. Through the design of multiple functional verification environment layers, the reuse of functional-level verification is achieved, the duplication of work during the verification process is reduced, and the UVM verification environment is adopted to improve random performance and coverage.
It effectively reduces duplicate work during the verification process, improves verification efficiency and code stability and correctness, shortens chip verification time, and reduces design and development costs.
Smart Images
Figure CN119990005A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of single-photon ranging chips, and in particular to a verification system, a verification method and a program product of a single-photon ranging chip. Background Art
[0002] With the continuous advancement of semiconductor process technology, chip manufacturing has reached an unprecedented height, but this has also led to a significant increase in tape-out costs. In order to effectively control costs, reducing the number of chip tape-outs before mass production has become a key strategy. At the same time, the rapid development of the semiconductor industry has led to a sharp increase in the complexity of chip systems, the increasing diversification of digital circuit functions, and the internal logic combinations have become more complex. This trend has directly led to the verification of chips becoming more arduous and complex, and the verification requirements have also increased, running through the entire design process from project establishment to tape-out.
[0003] In this context, it is particularly important to build a verification platform that is highly reliable, highly reusable, and easy to integrate upwards. Such a platform can significantly improve verification efficiency and ensure the accuracy and stability of chip design.
[0004] In particular, for highly complex SOCs such as single-photon ranging chips, the core of their quality assessment lies in the reliability and accuracy of the output distance information. Since single-photon ranging chips face complex and changing scenarios in actual applications, the completeness of verification has become the key to ensuring chip quality. However, the existing Verilog verification platform has obvious deficiencies in randomness and reusability, making it difficult to fully cover all actual application scenarios, and the verification efficiency is low, which easily brings a heavy workload to the verification personnel, thereby affecting the entire chip design and development cycle.
[0005] More specifically, the single-photon ranging chip integrates a CPU core and multiple functional modules, such as data sampling and collection, distance calculation and other IPs. In the verification process, random verification at the IP level is far from enough. Verifiers also need to start from the system level and comprehensively examine the overall functions of the chip and the collaboration capabilities between various IP modules to ensure that the entire system can operate correctly. However, the existing Verilog verification platform performs poorly in this regard. Its poor reusability and low efficiency are particularly prominent when verifying complex systems, which can easily lead to redundancy in verification work and increased error rates. Summary of the invention
[0006] The purpose of the embodiments of the present application is to provide a verification system, a verification method and a program product for a single-photon ranging chip, so as to solve the problems of poor reusability and low efficiency of existing verification schemes for single-photon ranging chips.
[0007] A verification system for a single-photon ranging chip provided in an embodiment of the present application includes a test component, a chip verification environment layer, a chip verification object, and verification interfaces of various functional modules of the chip verification object;
[0008] The test component is used to configure the chip verification environment layer and start the chip verification environment layer;
[0009] The chip verification environment layer includes a plurality of functional verification environment layers, wherein each functional verification environment layer is connected to a verification interface of a corresponding functional module.
[0010] In the above technical scheme, the chip verification environment layer includes multiple functional verification environment layers. In the verification of the single-photon ranging chip, the functional-level verification is reasonably reused to the chip system-level verification platform, which effectively reduces the duplication of work in the verification process and ensures the stability and correctness of the verification code; while ensuring the completeness of the verification, it increases the flexibility and reusability of the verification environment, improves the verification efficiency of the single-photon ranging chip, shortens the chip verification time, and reduces the chip design and development cost.
[0011] In some optional implementations, the functional verification environment layer includes: a stimulus generation component, a configuration drive component, a monitoring sampling component, a reference model component, and a scoring comparison component.
[0012] In the above technical solution, the functional-level verification builds a standardized and unified UVM verification environment, which has good random performance, can cover the actual usage scenarios of the chip to the greatest extent, increase the completeness of verification, minimize bugs before tape-out, reduce tape-out risks, and reduce the cost of a chip from design to mass production.
[0013] Among them, the stimulus generation component is a bridge for transferring data between the sequence (which is a class used to generate test stimuli in UVM) and the configuration driver component. It manages the sequence and is responsible for arbitrating between multiple sequences to determine which sequence's data is transferred at a certain moment. The stimulus generation component carries the sequence, and the sequence can only send transaction data to the configuration driver component when it is mounted on the stimulus generation component, and then pass it to the design under test (DUT). The stimulus generation component can also obtain a response (RSP) object from the configuration driver component to check whether the data communication is normal. The stimulus generation component is a uvm_component, which always exists during the operation of the verification platform. It is similar to a "router" and plays a key role in the entire stimulus link.
[0014] The main task of the configuration driver component is to convert the transaction data received from the stimulus generation component into an interface signal that the DUT can understand. It is responsible for sending the information in the transaction data (such as data, address, control signal, etc.) to the interface of the DUT according to specific protocols or timing requirements. The configuration driver component is one of the components in the verification platform that directly interacts with the design under test (DUT). It usually works closely with the stimulus generation component to complete the sending of the stimulus.
[0015] The monitoring sampling component is used to observe the boundary or internal signals of the DUT, and organize the observed data and send it to other verification platform components, such as the scoring and comparison components or checkers. It can monitor bus signals, clock signals, etc., check whether the bus timing complies with the protocol, and collect bus information. The monitoring sampling component always maintains the PASSIVE mode, that is, it does not drive the DUT. It can interact with other verification components (such as the scoring and comparison components) to support more complex verification requirements.
[0016] The Scoring Comparison component is used to check the integrity and consistency of data in the system. It compares the data from the monitoring sampling component with the expected reference data to verify whether the behavior of the DUT is as expected. The Scoring Comparison component is an important tool for automatic comparison and verification. It can help verification engineers quickly discover potential problems in the DUT.
[0017] A reference model component is a model used for verification that describes the expected behavior of a design. It is compared to the DUT to verify that the DUT meets specifications and requirements. Reference model components can also be used to verify the correctness of the test environment. A reference model component is an abstract model that simulates the behavior of a design. It is typically written in a high-level hardware description language such as SystemVerilog and has the ability to automate verification. The accuracy and reliability of the reference model component is critical to the verification process.
[0018] In some optional embodiments, the verification system is used for functional level verification testing:
[0019] The stimulus generation component is used to send the randomly generated test stimulus to the configuration driver component;
[0020] The configuration driver component is used to send the test stimulus to the corresponding verification interface according to the corresponding protocol or timing requirements;
[0021] The monitoring sampling component is used to monitor the input and output of the functional module verification object;
[0022] The reference model component is used to receive the input of the functional module verification object and simulate the expected output of the functional module verification object;
[0023] The scoring comparison component is used to compare the output of the functional module verification object with the simulation output to obtain a comparison result.
[0024] In some optional implementations, when the verification system is used for chip-level verification testing:
[0025] The stimulus generation component and the configuration drive component are turned off, and the chip verification object directly obtains the test stimulus generated according to the timing requirements of the chip design and drives the chip verification object to work; the monitoring sampling component is used to monitor the input and output of the functional module verification object; the reference model component is used to receive the input of the functional module verification object and simulate the expected output of the functional module verification object; the scoring comparison component is used to compare the output of the functional module verification object with the simulated output to obtain a comparison result.
[0026] In some optional implementations, the output end of the test component is connected to the input end of the stimulus generating component, the output end of the stimulus generating component is connected to the input end of the configuration driving component, and the output end of the configuration driving component is connected to the verification interface.
[0027] In some optional embodiments, the monitoring sampling component includes: an input monitoring sampling component and an output monitoring sampling component.
[0028] In some optional implementations, the verification interface is connected to the input end of the input monitoring sampling component, and the output end of the input monitoring sampling component is connected to the input end of the reference model component;
[0029] The output end of the reference model component is connected to the first input end of the scoring comparison component, the second input end of the scoring comparison component is connected to the output end of the output monitoring sampling component, and the input end of the output monitoring sampling component is connected to the verification interface.
[0030] A verification method for a single-photon ranging chip provided in an embodiment of the present application is applied to a verification system for a single-photon ranging chip as described above, and the method comprises:
[0031] When performing chip-level verification testing, turn off the stimulus generation components and configuration drive components of each functional verification environment layer;
[0032] The chip verification object directly obtains the test stimulus generated according to the timing requirements of the chip design and drives the chip verification object to work;
[0033] For each functional module verification object, perform the following steps:
[0034] The monitoring function module verifies the input and output of the object;
[0035] Receive input of the functional module verification object and simulate the expected output of the functional module verification object;
[0036] Compare the output of the functional module verification object with the simulation output to obtain a comparison result.
[0037] In the above technical solution, after closing the stimulus generation components and configuration drive components of each functional verification environment layer, the chip verification object directly obtains the test stimulus generated according to the timing requirements of the chip design, so that the functional-level verification is reasonably reused to the chip system-level verification platform, effectively reducing the duplication of work in the verification process and ensuring the stability and correctness of the verification code; while ensuring the completeness of the verification, the flexibility and reusability of the verification environment are increased, the verification efficiency of the single-photon ranging chip is improved, the chip verification time is shortened, and the chip design and development cost is reduced.
[0038] In some optional embodiments, the method further comprises:
[0039] In the case of functional level verification testing, the stimulus generation component and configuration drive component of the functional verification environment layer are turned on;
[0040] Generate test stimuli randomly and send them to the corresponding verification interface according to the corresponding protocol or timing requirements;
[0041] Monitor the input and output of the function module verification object; receive the input of the function module verification object and simulate the expected output of the function module verification object; compare the output of the function module verification object with the simulated output to obtain a comparison result.
[0042] A computer program product provided in an embodiment of the present application includes a computer program / instruction, which implements the steps of any of the above methods when executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0044] Figure 1 A schematic diagram of a verification system for a single-photon ranging chip provided in an embodiment of the present application;
[0045] Figure 2 A schematic diagram of a functional verification environment layer provided for an embodiment of the present application;
[0046] Figure 3 A flowchart of the chip-level verification test method provided in the embodiment of the present application;
[0047] Figure 4 A flowchart of the functional level verification test method steps provided in the embodiment of the present application;
[0048] Figure 5 A possible structural diagram of an electronic device provided in an embodiment of the present application.
[0049] icon:
[0050] 51 - processor, 52 - memory, 53 - communication interface, 54 - communication bus. DETAILED DESCRIPTION
[0051] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.
[0052] Please refer to Figure 1 , Figure 1 A schematic diagram of a verification system for a single-photon ranging chip provided in an embodiment of the present application, the verification system comprising a test component test, a chip verification environment layer system_env, a chip verification object system_dut, and verification interfaces of each functional module of the chip verification object system_dut; wherein the test component test is used to configure the chip verification environment layer system_env, and start the chip verification environment layer system_env; the chip verification environment layer system_env comprises multiple functional verification environment layers ip_env, wherein each functional verification environment layer ip_env is connected to the verification interface of the corresponding functional module.
[0053] Among them, the data stimulus drive of the verification system comes from the light information in the environment, the system operation parameter configuration and program code come from the system's peripheral host device, the peripheral host device sends the system parameter configuration and program code as the master end of the communication protocol, the corresponding slave end of the system configures the corresponding system parameters after receiving, and stores the program code in the system memory in bytes. The CPU core accesses the memory, executes the code, controls the operation of each functional module according to the program code, executes the main program and interrupt service program, and collaborates to complete the entire ranging process. The peripheral host device can access the optical signal data collected during the ranging process and the distance information obtained after the ranging is completed by reading the system memory.
[0054] In an embodiment of the present application, the chip verification environment layer system_env includes multiple functional verification environment layers ip_env. In the verification of the single-photon ranging chip, the functional-level verification is reasonably reused to the chip system-level verification platform, effectively reducing the repetitive work in the verification process and ensuring the stability and correctness of the verification code; while ensuring the completeness of the verification, the flexibility and reusability of the verification environment are increased, the verification efficiency of the single-photon ranging chip is improved, the chip verification time is shortened, and the chip design and development cost is reduced.
[0055] Please refer to Figure 2 , Figure 2 A schematic diagram of the functional verification environment layer ip_env provided in an embodiment of the present application, wherein the functional verification environment layer ip_env includes: a stimulus generation component, a configuration drive component, a monitoring sampling component, a reference model component and a scoring comparison component.
[0056] In the embodiments of the present application, a standardized and unified UVM verification environment is established for functional-level verification, which has good random performance, can cover the actual usage scenarios of the chip to the greatest extent, increase the completeness of verification, minimize bugs before tape-out, reduce tape-out risks, and reduce the cost of a chip from design to mass production.
[0057] Among them, the stimulus generation component is a bridge for transferring data between the sequence (which is a class used to generate test stimuli in UVM) and the configuration driver component. It manages the sequence and is responsible for arbitrating between multiple sequences to determine which sequence's data is transferred at a certain moment. The stimulus generation component carries the sequence, and the sequence can only send transaction data to the configuration driver component when it is mounted on the stimulus generation component, and then pass it to the design under test (DUT). The stimulus generation component can also obtain a response (RSP) object from the configuration driver component to check whether the data communication is normal. The stimulus generation component is a uvm_component, which always exists during the operation of the verification platform. It is similar to a "router" and plays a key role in the entire stimulus link.
[0058] The main task of the configuration driver component is to convert the transaction data received from the stimulus generation component into an interface signal that the DUT can understand. It is responsible for sending the information in the transaction data (such as data, address, control signal, etc.) to the interface of the DUT according to specific protocols or timing requirements. The configuration driver component is one of the components in the verification platform that directly interacts with the design under test (DUT). It usually works closely with the stimulus generation component to complete the sending of the stimulus.
[0059] The monitoring sampling component is used to observe the boundary or internal signals of the DUT, and organize the observed data and send it to other verification platform components, such as the scoring and comparison components or checkers. It can monitor bus signals, clock signals, etc., check whether the bus timing complies with the protocol, and collect bus information. The monitoring sampling component always maintains the PASSIVE mode, that is, it does not drive the DUT. It can interact with other verification components (such as the scoring and comparison components) to support more complex verification requirements.
[0060] The Scoring Comparison component is used to check the integrity and consistency of data in the system. It compares the data from the monitoring sampling component with the expected reference data to verify whether the behavior of the DUT is as expected. The Scoring Comparison component is an important tool for automatic comparison and verification. It can help verification engineers quickly discover potential problems in the DUT.
[0061] A reference model component is a model used for verification that describes the expected behavior of a design. It is compared to the DUT to verify that the DUT meets specifications and requirements. Reference model components can also be used to verify the correctness of the test environment. A reference model component is an abstract model that simulates the behavior of a design. It is typically written in a high-level hardware description language such as SystemVerilog and has the ability to automate verification. The accuracy and reliability of the reference model component is critical to the verification process.
[0062] In some optional embodiments, when the verification system is used for functional-level verification testing: the stimulus generation component is used to send the randomly generated test stimulus to the configuration drive component; the configuration drive component is used to send the test stimulus to the corresponding verification interface in accordance with the corresponding protocol or timing requirements; the monitoring sampling component is used to monitor the input and output of the functional module verification object ip_dut; the reference model component is used to receive the input of the functional module verification object ip_dut, and simulate the expected output of the functional module verification object ip_dut; the scoring comparison component is used to compare the output of the functional module verification object ip_dut with the simulated output to obtain a comparison result.
[0063] In some optional embodiments, when the verification system is used for chip-level verification testing: the stimulus generation component and the configuration drive component are turned off, the chip verification object system_dut directly obtains the test stimulus generated according to the timing requirements of the chip design and drives the chip verification object system_dut to work; the monitoring sampling component is used to monitor the input and output of the functional module verification object ip_dut; the reference model component is used to receive the input of the functional module verification object ip_dut and simulate the expected output of the functional module verification object ip_dut; the scoring comparison component is used to compare the output of the functional module verification object ip_dut with the simulated output to obtain a comparison result.
[0064] Among them, the chip verification object system_dut directly obtains the test stimulus generated according to the timing requirements of the chip design and drives the chip verification object system_dut to work, that is: simulate the optical signal stimulus or the behavior of the peripheral host device during the simulation process, drive the design to be tested according to the chip design document during the chip system-level verification, and give data signal stimulus, system configuration parameters and program code input during simulation to simulate the real application scenario of the chip. The program code input in the system-level verification environment of the single-photon ranging chip is compiled into byte form in advance by the external compiler software and loaded into the chip system memory. The data stimulus is generated by the test component test and the sequence constraint model. When the CPU core calls each functional module to work, the entire system is driven from the interface according to the timing requirements of the chip design.
[0065] In some optional implementations, the output end of the test component test is connected to the input end of the stimulus generating component, the output end of the stimulus generating component is connected to the input end of the configuration driving component, and the output end of the configuration driving component is connected to the verification interface.
[0066] In some optional embodiments, the monitoring sampling component includes: an input monitoring sampling component and an output monitoring sampling component.
[0067] In some optional embodiments, the verification interface is connected to the input end of the input monitoring sampling component, and the output end of the input monitoring sampling component is connected to the input end of the reference model component; the output end of the reference model component is connected to the first input end of the scoring comparison component, the second input end of the scoring comparison component is connected to the output end of the output monitoring sampling component, and the input end of the output monitoring sampling component is connected to the verification interface.
[0068] Please refer to Figure 3 , Figure 3 The chip-level verification test method step flow chart provided in the embodiment of the present application is applied to a verification system of a single-photon ranging chip as described above, and the method includes:
[0069] Step 11: When performing chip-level verification testing, turn off the stimulus generation components and configuration drive components of each functional verification environment layer;
[0070] Step 12: The chip verification object directly obtains the test stimulus generated according to the timing requirements of the chip design, and drives the chip verification object to work;
[0071] Step 13, for each functional module verification object, perform the following steps: monitor the input and output of the functional module verification object; receive the input of the functional module verification object and simulate the expected output of the functional module verification object; compare the output of the functional module verification object with the simulated output to obtain a comparison result.
[0072] In the embodiment of the present application, after closing the stimulus generation components and configuration drive components of each functional verification environment layer, the chip verification object directly obtains the test stimulus generated according to the timing requirements of the chip design, so that the functional-level verification is reasonably reused to the chip system-level verification platform, effectively reducing the repetitive work in the verification process and ensuring the stability and correctness of the verification code; while ensuring the completeness of the verification, the flexibility and reusability of the verification environment are increased, the verification efficiency of the single-photon ranging chip is improved, the chip verification time is shortened, and the chip design and development cost is reduced.
[0073] Please refer to Figure 4 , Figure 4 The functional level verification test method step flow chart provided in the embodiment of the present application is applied to a verification system of a single photon ranging chip as described above, and the method includes:
[0074] Step 21: In the case of a functional level verification test, the stimulus generation component and the configuration drive component of the functional verification environment layer are turned on;
[0075] Step 22: randomly generate a test stimulus, and send the test stimulus to the corresponding verification interface according to the corresponding protocol or timing requirements;
[0076] Step 23, the monitoring function module verifies the input and output of the object;
[0077] Step 24: receiving the input of the functional module verification object and simulating the expected output of the functional module verification object;
[0078] Step 25: Compare the output of the functional module verification object with the simulation output to obtain a comparison result.
[0079] A computer program product provided in an embodiment of the present application includes a computer program / instruction, which implements the steps of any of the above methods when executed by a processor.
[0080] Figure 5 A possible structure of an electronic device provided in an embodiment of the present application is shown. Figure 5 The electronic device includes: a processor 51, a memory 52 and a communication interface 53. These components are interconnected and communicate with each other through a communication bus 54 and / or other forms of connection mechanisms (not shown).
[0081] The memory 52 includes one or more (only one is shown in the figure), which may be, but not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The processor 51 and other possible components may access the memory 52, and read and / or write data therein.
[0082] The processor 51 includes one or more (only one is shown in the figure), which can be an integrated circuit chip with signal processing capabilities. The above-mentioned processor 51 can be a general-purpose processor, including a central processing unit (CPU), a micro control unit (MCU), a network processor (NP) or other conventional processors; it can also be a dedicated processor, including a neural network processor (NPU), a graphics processor (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. In addition, when there are multiple processors 51, some of them can be general-purpose processors and the other part can be dedicated processors.
[0083] The communication interface 53 includes one or more (only one is shown in the figure), which can be used to communicate directly or indirectly with other devices to exchange data. The communication interface 53 can include an interface for wired and / or wireless communication.
[0084] One or more computer program instructions may be stored in the memory 52 , and the processor 51 may read and execute these computer program instructions to implement the method provided in the embodiment of the present application.
[0085] Understandably, Figure 5 The structure shown is for illustration only. The electronic device may also include Figure 5 More or fewer components as shown, or with Figure 5 Different structures are shown. Figure 5 The components shown in the figure can be implemented by hardware, software or a combination thereof. The electronic device may be a physical device, such as a PC, a laptop, a tablet computer, a mobile phone, a server, an embedded device, etc., or a virtual device, such as a virtual machine, a virtualized container, etc. Moreover, the electronic device is not limited to a single device, but may also be a combination of multiple devices or a cluster consisting of a large number of devices.
[0086] A computer program product provided in an embodiment of the present application includes a computer program / instruction, which implements the steps of any of the above methods when executed by a processor.
[0087] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.
[0088] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0089] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
[0090] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0091] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A verification system for a single-photon ranging chip, characterized in that: It includes test components, chip verification environment layer, chip verification object and verification interface of each functional module of chip verification object; The test component is used to configure the chip verification environment layer and start the chip verification environment layer; The chip verification environment layer includes a plurality of function verification environment layers, wherein each of the function verification environment layers is connected to a verification interface of a corresponding function module.
2. The verification system according to claim 1, characterized in that: The functional verification environment layer includes: a stimulus generation component, a configuration drive component, a monitoring sampling component, a reference model component and a scoring comparison component.
3. The verification system according to claim 2, characterized in that: The verification system is used for functional level verification testing when: The stimulus generation component is used to send the randomly generated test stimulus to the configuration drive component; The configuration drive component is used to send the test stimulus to the corresponding verification interface according to the corresponding protocol or timing requirements; The monitoring sampling component is used to monitor the input and output of the functional module verification object; The reference model component is used to receive input of the functional module verification object and simulate the expected output of the functional module verification object; The scoring comparison component is used to compare the output of the functional module verification object with the simulation output to obtain a comparison result.
4. The verification system according to claim 2, characterized in that: When the verification system is used for chip-level verification testing: The stimulus generation component and the configuration drive component are turned off, and the chip verification object directly obtains the test stimulus generated according to the timing requirements of the chip design and drives the chip verification object to work; The monitoring sampling component is used to monitor the input and output of the functional module verification object; The reference model component is used to receive input of the functional module verification object and simulate the expected output of the functional module verification object; The scoring comparison component is used to compare the output of the functional module verification object with the simulation output to obtain a comparison result.
5. The verification system according to claim 2, characterized in that: The output end of the test component is connected to the input end of the stimulus generating component, the output end of the stimulus generating component is connected to the input end of the configuration driving component, and the output end of the configuration driving component is connected to the verification interface.
6. The verification system according to claim 2, characterized in that: The monitoring sampling component includes: an input monitoring sampling component and an output monitoring sampling component.
7. The verification system according to claim 6, characterized in that: The verification interface is connected to the input end of the input monitoring sampling component, and the output end of the input monitoring sampling component is connected to the input end of the reference model component; The output end of the reference model component is connected to the first input end of the scoring comparison component, the second input end of the scoring comparison component is connected to the output end of the output monitoring sampling component, and the input end of the output monitoring sampling component is connected to the verification interface.
8. A verification method for a single-photon ranging chip, characterized in that: A verification system for a single-photon ranging chip as described in any one of claims 1 to 7, the method comprising: When performing chip-level verification testing, turn off the stimulus generation components and configuration drive components of each functional verification environment layer; The chip verification object directly obtains the test stimulus generated according to the timing requirements of the chip design, and drives the chip verification object to work; For each functional module verification object, perform the following steps: The monitoring function module verifies the input and output of the object; Receive input of the functional module verification object and simulate the expected output of the functional module verification object; Compare the output of the functional module verification object with the simulation output to obtain a comparison result.
9. The method according to claim 8, characterized in that Also includes: In the case of functional level verification testing, the stimulus generation component and configuration drive component of the functional verification environment layer are turned on; Generate test stimuli randomly and send them to the corresponding verification interface according to the corresponding protocol or timing requirements; The monitoring function module verifies the input and output of the object; Receive input of the functional module verification object and simulate the expected output of the functional module verification object; Compare the output of the functional module verification object with the simulation output to obtain a comparison result.
10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 8 to 9 are implemented.