Software and hardware co-simulation chip verification method, system and device and storage medium

Abstract

The invention relates to a software and hardware co-simulation chip verification method, system and device and a storage medium, and relates to the field of software and hardware co-simulation. The method is based on a hyperSemu system comprising an hsComple and an hsRun and an FPGA (Field Programmable Gate Array) comprising a DUT (Device Under Test) and a Transactor. The method comprises the following steps of: writing an RTL (Real Time Language) design code of a chip; compiling the RTL design code by utilizing hsCompile to obtain a DB file; downloading the DB file to an FPGA (Field Programmable Gate Array) through hsRun so as to carry out hardware simulation; according to the DUT and the Transactor, a Hybrid server program and a Hybrid client program are written, and the Hybrid client program comprises a simulator program and a Linux system; and performing software simulation in the Linux system according to the DUT and the simulator program. The technical effect of the invention is that the efficiency and speed of chip simulation verification are improved.

Description

Technical Field

[0001] The present application relates to the field of software-hardware co-simulation, and in particular to a method, system, device and storage medium for software-hardware co-simulation verification of a chip. Background Art

[0002] The existing chip design stage usually adopts pure hardware simulation or software simulation. Hardware simulation requires real physical devices such as FPGA external disk, network port, UART for debugging. Compared with software simulation, hardware-based simulation is faster and can provide performance closer to real hardware. However, it has low flexibility when debugging and modifying hardware logic. It requires a lot of manpower and financial resources in the verification stage. The scale of hardware that can be simulated is also limited by its own scale. The simulation cost increases with scale at a much higher rate than the software method. Software simulation does not require real physical devices, but the software simulation speed lags behind the hardware-based simulation speed.

[0003] Therefore, the speed of chip verification using only hardware simulation or software simulation will be limited, making it difficult to meet the demand for rapid product launch. Summary of the invention

[0004] In order to improve the efficiency of chip simulation and verification, the present application provides a method for software and hardware collaborative simulation and verification of a chip.

[0005] In a first aspect, the present application provides a method for hardware-software co-simulation verification of a chip, the method is based on a hyperSemu system including hsCompile and hsRun and an FPGA including a DUT and a Transactor, and adopts the following technical solution: Write the RTL design code for the chip; Compile the RTL design code using hsCompile to obtain a DB file; Downloading the DB file to the FPGA through the hsRun to perform hardware simulation; Writing a Hybrid server program and a Hybrid client program according to the DUT and the Transactor, wherein the Hybrid client program includes a simulator program and a Linux system; Software simulation is performed in the Linux system according to the DUT and the simulator program.

[0006] Through the above technical solution, the whole solution verification system is integrated with hardware and software at the same time, in which the RTL level simulation of the hardware is in the simulator, and the software simulates another transaction level reference model, etc. The hardware-software co-simulation combines software simulation and hardware simulation. In the development stage, it can not only develop and debug hardware, but also develop and debug software in advance. Through this hybrid debugging and simulation, designers can verify the whole system with lower cost and higher performance, which can greatly reduce the large amount of time spent on the chip in the design verification stage, and provide a good solution for accelerating the rapid listing of products.

[0007] In a specific implementation scheme, after writing the Hybridserver program and the Hybridclient program according to the DUT and the Transactor, it also includes: A Testbench program is written and used to access the FPGA through the Hybrid Server and the hsRun to obtain a waveform file.

[0008] Through the above technical scheme, the software-hardware collaborative simulation of the present application combines software simulation and hardware simulation. In the development stage, not only the hardware can be developed and debugged, but also the software can be developed and debugged in advance. Through this hybrid debugging and simulation, the designer can verify the entire system with lower cost and higher performance.

[0009] In a specific implementation scheme, performing software simulation according to the DUT and the simulator program in the Linux system includes: Design the app and driver based on the DUT; Compiling the Linux system, the app and the driver to obtain a Linux executable program, wherein the Linux executable program includes an executable Image file, an app executable program and a driver executable program; Compiling the simulator program to obtain a simulator executable program; Using the simulator executable program to start the Image file and then enter the Linux system; The driver is loaded in the Linux system, and the app is run to perform software simulation.

[0010] Through the above technical solution, the hybrid client uses the simulator to access the DUT and Transactor of the underlying hardware, realizing software and hardware co-simulation and improving the speed of chip verification.

[0011] In a specific implementation scheme, compiling the simulator program to obtain a simulator executable program includes: Develop the simulator program according to the DUT to obtain a target simulator program; Compile the target simulator program to obtain a simulator executable program.

[0012] Through the above technical solution, the Hybrid client uses a simulator to simulate the ARM or RISC-V software SoC, adds the software part of the simulator, and accesses the underlying hardware DUT and Transactor in the SoC software system by simulating the functions required by the SoC, thereby realizing hardware-software co-simulation and improving the speed of chip verification.

[0013] In a specific implementation manner, after running the app according to the app executable program and the driver executable program to perform software simulation, the method further includes: Recording debugging information of the app, the driver, the hybrid server program, and the simulator program; Software and hardware debugging is performed according to the debugging information and the waveform file.

[0014] In a specific implementation scheme, the performing software and hardware debugging according to the debugging information and the waveform file includes: Get the expected simulation effect; Analyzing the debugging information and the waveform file to obtain an actual simulation effect; Software and hardware debugging is performed by comparing the expected simulation effect with the actual simulation effect.

[0015] In a specific implementation scheme, the software and hardware debugging by comparing the expected simulation effect with the actual simulation effect includes: comparing the actual simulation effect with the expected simulation effect; If the actual simulation effect meets the expected simulation effect, no software or hardware debugging is required; Otherwise, it is necessary to improve the design and perform software and hardware debugging.

[0016] Through the above technical solution, hardware-software co-simulation combines software simulation and hardware simulation. In the development phase, not only can the hardware be developed and debugged, but the software can also be developed and debugged in advance. Through this hybrid debugging and simulation, designers can verify the entire system with lower cost and higher performance.

[0017] In a second aspect, the present application provides a software-hardware co-simulation verification chip system, which is used to implement the software-hardware co-simulation verification chip method, and adopts the following technical solution: the system includes: RTL design code writing module, used to write the RTL design code of the chip; A design code compiling module, used to compile the RTL design code using the hsCompile to obtain a DB file; A hardware simulation module, used for downloading the DB file to the FPGA through the hsRun to perform hardware simulation; A software program writing module, used for writing a Hybrid server program and a Hybrid client program according to the DUT and the Transactor, wherein the Hybrid client program includes a simulator program and a Linux system; A software simulation module is used to perform software simulation in the Linux system according to the DUT and the simulator program.

[0018] In a third aspect, the present application provides a computer device, which adopts the following technical solution: it includes a memory and a processor, and the memory stores a computer program that can be loaded and executed by the processor such as the above-mentioned software and hardware collaborative simulation and verification chip method.

[0019] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solution: storing a computer program that can be loaded by a processor and execute the above-mentioned software-hardware collaborative simulation verification chip method.

[0020] In summary, this application has the following beneficial technical effects: (1) The present application integrates hardware and software into a whole solution verification system, wherein the RTL level simulation of the hardware is in the simulator, and the software simulates another transaction level reference model, etc. The hardware-software co-simulation combines software simulation and hardware simulation. In the development stage, it can not only develop and debug the hardware, but also develop and debug the software in advance. Through this hybrid debugging and simulation, the designer can verify the whole system with lower cost and higher performance, which can greatly reduce the large amount of time spent on the chip in the design verification stage, and provide a good solution for accelerating the rapid launch of products.

[0021] (2) The hybrid client of this application uses a simulator to simulate the ARM or RISC-V software SoC, adds the software part of the simulator, and accesses the DUT and Transactor of the underlying hardware in the SoC software system by simulating the functions required by the SoC, thereby realizing hardware-software co-simulation and improving the speed of chip verification.

[0022] (3) The host supports viewing the signal waveform of the hardware DUT, the signals of the software and DUT in the host are connected, and each module of the software part and the hardware can be debugged simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is the architecture diagram of the hardware-software collaborative simulation system.

[0024] Figure 2 It is a flowchart of a method for hardware-software collaborative simulation and verification of a chip in an embodiment of the present application.

[0025] Figure 3 It is a structural block diagram of a software and hardware collaborative simulation verification chip method in an embodiment of the present application.

[0026] Figure numerals: 301, RTL design code writing module; 302, design code compilation module; 303, hardware simulation module; 304, software program writing module; 305, software simulation module. DETAILED DESCRIPTION

[0027] The following is combined with Figure 1-Figure 3 This application is described in further detail.

[0028] The embodiment of the present application discloses a method for software-hardware collaborative simulation and verification of a chip, which is used to improve the efficiency of chip simulation and verification.

[0029] The existing chip design stage usually adopts pure hardware simulation or software simulation. Hardware simulation requires real physical devices such as FPGA external disk, network port, UART for debugging. Compared with software simulation, hardware-based simulation is faster and can provide performance closer to real hardware. However, it has low flexibility when debugging and modifying hardware logic. It requires a lot of manpower and financial resources in the verification stage. The scale of hardware that can be simulated is also limited by its own scale. The simulation cost increases with scale at a much higher rate than the software method. Software simulation does not require real physical devices, but the software simulation speed lags behind the hardware-based simulation speed.

[0030] The speed of chip verification using only hardware simulation or software simulation will be limited, making it difficult to achieve the demand for rapid product launch.

[0031] Therefore, the present application proposes a method for co-simulating and verifying a chip by using software and hardware, and utilizes this method to improve the efficiency of chip simulation and verification.

[0032] Before describing the specific method, it is necessary to first describe the structure of the chip verification system, such as Figure 1 As shown: The structure of the chip verification system includes the bottom FPGA end and the host. The bottom layer is the self-developed FPGA hardware development board, which runs the newly developed RTL code. These RTL codes include AXI4 protocol, various DUTs (for example, common peripherals such as UART DUT can be supported in theory) and Transactor, which are connected to the host through the PCIe interface and SCE-MI protocol. The host is mainly divided into five parts: (1) hsCompile is used to compile RTL code to generate DB files. It is a general editing, compiling and synthesis software.

[0033] (2) hsRun downloads the DB file to the FPGA, performs some control on the FPGA, connects to the Hybrid server at the top and PCIe at the bottom, and plays the role of protocol encapsulation, control and data conversion.

[0034] (3) Testbench is a test program for the FPGA DUT. It generates stimulus and instantiates the DUT. The test of each DUT requires different development.

[0035] (4) The Hybrid server is connected to the simulator and encapsulates the support for different devices (different devices require the development of corresponding deivce support). It actually accesses the hardware through hsRun. The running process will generate the signal waveform file corresponding to the Testbench.

[0036] (5) The hybrid client uses an emulator (Qemu) to simulate an ARM or RISC-V software SoC. The Linux system (client) runs in the emulator. The device driver and app corresponding to the DUT can be executed in Linux. The driver and app here access the DUT and Transactor in the underlying FPGA hardware. Different drivers and apps need to be developed for different DUTs and Transactors.

[0037] like Figure 2 As shown, the method is based on a hyperSemu system including hsCompile and hsRun and an FPGA including a DUT and a Transactor, and the method includes: S10, write the RTL design code of the chip.

[0038] Specifically, the newly developed RTL code runs in the self-developed FPGA hardware development board in this application, so to perform chip simulation verification, it is necessary to first write the chip's RTL logic design code and input it into the verification system.

[0039] S20, using hsCompile to compile the RTL design code to obtain a DB file.

[0040] Specifically, hsCompile is a general editing, compiling and synthesis software. hsCompile is used to compile RTL code to generate DB files. DB files are binary databases generated by the simulation tool after compiling the RTL code. They store information such as the code hierarchy, signal connections, and optimized simulation models.

[0041] S30, download the DB file to the FPGA through hsRun for hardware simulation.

[0042] Specifically, the compiled DB file is downloaded to the FPGA through hsRun and run, so that the RTL logic design code of the chip is converted into a DB file and downloaded to the FPGA for hardware simulation, thereby realizing chip verification.

[0043] S40, write a Hybrid server program and a Hybrid client program according to the DUT and the Transactor, the Hybrid client program includes a simulator program and a Linux system.

[0044] Specifically, the Hybrid server program and the Hybrid client program can be developed differently according to different DUTs and Transactors. After running the Hybrid server startup script run.bat and starting the pre-written Hybrid server in the host through the script, the Hybrid Server will provide an inter-process communication interface for the Hybrid client to connect to. This connection is used for communication and data exchange between the Client and Server. The Hybridclient program includes a simulator program and a Linux (Guest) system.

[0045] S50, performing software simulation in the Linux system according to the DUT and the simulator program.

[0046] Specifically, a simulator program is developed based on the DUT in the Linux system, and by simulating the functions required by the SoC, the DUT and Transactor of the underlying hardware are accessed in the SoC software system for software simulation.

[0047] This application integrates hardware and software into a whole solution verification system, in which the RTL level simulation of the hardware is in the simulator, and the software simulates another transaction level reference model, etc. Software and hardware co-simulation combines software simulation and hardware simulation. In the development stage, not only can the hardware be developed and debugged, but also the software can be developed and debugged in advance. Through this hybrid debugging and simulation, designers can verify the entire system with lower cost and higher performance, which can greatly reduce the large amount of time spent on the chip in the design verification stage, and provide a good solution for accelerating the rapid listing of products.

[0048] In one embodiment, in order to improve the efficiency of chip simulation verification, after writing the Hybrid server program and the Hybrid client program according to the DUT and the Transactor, the following steps may be performed: Write a Testbench program and use it to access the FPGA through the Hybrid Server and hsRun to obtain waveform files. Specifically, Testbench is a test program for the FPGA DUT that generates stimulus and instantiates the DUT. Different development is required for the test of each DUT. The Hybrid server actually accesses the hardware through hsRun, so the Testbench program accesses the FPGA through the Hybrid Server and hsRun to obtain waveform files.

[0049] The hardware-software co-simulation of this application combines software simulation and hardware simulation. During the development phase, not only can the hardware be developed and debugged, but the software can also be developed and debugged in advance. Through this hybrid debugging and simulation, the designer can verify the entire system with lower cost and higher performance.

[0050] In one embodiment, in order to improve the efficiency of chip simulation verification, the following steps can be specifically performed in the Linux system according to the DUT and the simulator program to perform software simulation: First, design the app and driver according to the DUT. Specifically, the app is the application program and the driver is the driver. Different DUTs and Transactors in the FPGA correspond to different apps and drivers, so you must first design the corresponding app and the corresponding driver according to different DUTs and Transactors.

[0051] Then, a Linux executable program is compiled according to the Linux system, app and driver. The Linux executable program includes an executable Image file, an app executable program and a driver executable program. Specifically, the Linux system, app and driver are compiled by cross-compilation, and a Linux executable program is compiled in the host. The Linux executable program includes a Linux executable program zImage, an executable Image file, an app executable program, a driver executable program, an application uart_test, a driver hb_uart.ko, a file system rootfs.cpio, a device tree file dt-arm.dtb, etc.

[0052] Next, compile the simulator program to obtain the simulator executable program, use the simulator executable program to start the Image file and enter the Linux system. Specifically, execute the compilation script run-client-arm.sh buile_qemu in Windows or Linux to compile the simulator program to obtain the simulator executable program, use the simulator executable program to start the Image file and enter the Linux system for software simulation.

[0053] Finally, the driver is loaded in the Linux system and the app is run for software simulation. Specifically, the compiled app executable program and driver executable program are transferred to the Linux system, and then the driver is loaded and the app is run for software simulation to test and debug the functions of the DUT and Transactor.

[0054] In this application, the Hybrid client uses a simulator to access the DUT and Transactor of the underlying hardware to achieve hardware-software co-simulation and improve the speed of chip verification.

[0055] In one embodiment, in order to improve the efficiency of chip simulation verification, the step of compiling the simulator program to obtain the simulator executable program can be performed as follows: First, the target simulator program is obtained according to the DUT development simulator program. Specifically, a customized part is added to the simulator program. Different DUTs require different functional development, such as SoC program development and peripheral program development to simulate the functions required by SoC.

[0056] Next, compile the target simulator program to obtain the simulator executable program. Specifically, after development is completed, execute the compilation script run-client-arm.sh buile_qemu in Windows or Linux to compile the target simulator program and generate a customized simulator executable program.

[0057] The hybrid client of this application uses a simulator to simulate the ARM or RISC-V software SoC, adds the software part of the simulator, and accesses the DUT and Transactor of the underlying hardware in the SoC software system by simulating the functions required by the SoC, thereby realizing hardware-software co-simulation and improving the speed of chip verification.

[0058] In one embodiment, in order to improve the efficiency of chip simulation verification, after running the app according to the app executable program and the driver executable program to perform software simulation, the following steps may be further performed: First, record the debugging information of the app, driver, hybrid server program, and simulator program. Specifically, record and view the debugging information such as logs of the app, driver, hybrid server program, and simulator program.

[0059] Next, perform software and hardware debugging based on the debugging information and waveform files. Specifically, use the generated waveform file probe.vcd containing the signals in the DUT to view the waveform and timing analysis of the DUT signal, and perform software and hardware debugging based on the debugging information and waveform files.

[0060] In one embodiment, in order to improve the efficiency of chip simulation verification, the step of performing software and hardware debugging according to the debugging information and the waveform file can be specifically performed as follows: First, obtain the expected simulation effect, specifically, obtain the expected simulation effect of the functions of the software simulator and the hardware DUT and Transactor.

[0061] Then, the debugging information and waveform files are analyzed to obtain the actual simulation effect, and the software and hardware debugging is performed by comparing the expected simulation effect with the actual simulation effect. Specifically, the waveform file probe.vcd containing the signal in the DUT is used to view the waveform and timing analysis of the DUT signal, and the debugging information such as the log of the app, driver, hybrid server program, and simulator program is analyzed to obtain the actual simulation effect, and the software and hardware debugging is performed by comparing the expected simulation effect with the actual simulation effect.

[0062] In one embodiment, in order to improve the efficiency of chip simulation verification, software and hardware debugging can be performed by comparing the expected simulation effect with the actual simulation effect. The following steps can be specifically performed: The actual simulation effect is compared with the expected simulation effect. Specifically, the actual simulation effect is compared to see if it is consistent with the expected simulation effect.

[0063] If the actual simulation effect is consistent with the expected simulation effect, there is no need to perform software and hardware debugging. Specifically, if the actual simulation effect is consistent with the expected simulation effect, it means that the software and hardware can meet the needs of chip verification and there is no need to perform software and hardware debugging.

[0064] Otherwise, it is necessary to improve the design and perform software and hardware debugging. Specifically, if the actual simulation effect does not meet the expected simulation effect, it means that the software and hardware cannot meet the needs of chip verification, and it is necessary to improve the design code, such as the design code of app, hybrid server, simulator, DUT and other parts, and perform software and hardware debugging.

[0065] The hardware-software co-simulation of this application combines software simulation and hardware simulation. During the development phase, not only can the hardware be developed and debugged, but the software can also be developed and debugged in advance. Through this hybrid debugging and simulation, the designer can verify the entire system with lower cost and higher performance.

[0066] Based on the above method, the embodiment of the present application also discloses a software-hardware co-simulation verification chip system, which is used to implement a software-hardware co-simulation verification chip method, such as Figure 3 The system includes the following modules: An RTL design code writing module 301 is used to write the RTL design code of the chip; The design code compiling module 302 is used to compile the RTL design code using hsCompile to obtain a DB file; The hardware simulation module 303 is used to download the DB file to the FPGA through hsRun to perform hardware simulation; A software program writing module 304 is used to write a Hybrid server program and a Hybrid client program according to the DUT and the Transactor, wherein the Hybrid client program includes a simulator program and a Linux system; The software simulation module 305 is used to perform software simulation according to the DUT and the simulator program in the Linux system.

[0067] In one embodiment, the software simulation module 305 is specifically used to design the app and driver according to the DUT; Compile the Linux system, app and driver to obtain a Linux executable program, which includes an executable Image file, an app executable program and a driver executable program; compile the simulator program to obtain a simulator executable program; use the simulator executable program to start the Image file and then enter the Linux system; load the driver in the Linux system and run the app for software simulation.

[0068] In one embodiment, the software simulation module 305 is specifically used to obtain a target simulator program according to a DUT development simulator program; and compile the target simulator program to obtain a simulator executable program.

[0069] The embodiment of the present application also discloses a computer device.

[0070] Specifically, the computer device includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and execute the above-mentioned method of software-hardware collaborative simulation verification chip.

[0071] The embodiment of the present application also discloses a computer-readable storage medium.

[0072] Specifically, the computer-readable storage medium stores a computer program that can be loaded by a processor and execute a method such as the above-mentioned software and hardware collaborative simulation verification chip. The computer-readable storage medium includes, for example: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0073] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A method for verifying a chip by co-simulating software and hardware, characterized in that: The method is based on a hyperSemu system including hsCompile and hsRun and an FPGA including a DUT and a Transactor, and the method includes: Write the RTL design code for the chip; Compile the RTL design code using the hsCompile to obtain a DB file; Downloading the DB file to the FPGA through the hsRun to perform hardware simulation; Writing a Hybrid server program and a Hybrid client program according to the DUT and the Transactor, wherein the Hybrid client program includes a simulator program and a Linux system; Software simulation is performed in the Linux system according to the DUT and the simulator program.

2. The method according to claim 1, characterized in that: After writing the Hybrid server program and the Hybrid client program according to the DUT and the Transactor, the method further includes: A Testbench program is written and used to access the FPGA through the Hybrid Server and the hsRun to obtain a waveform file.

3. The method according to claim 2, characterized in that: The performing software simulation according to the DUT and the simulator program in the Linux system comprises: Design the app and driver based on the DUT; Compiling the Linux system, the app and the driver to obtain a Linux executable program, wherein the Linux executable program includes an executable Image file, an app executable program and a driver executable program; Compiling the simulator program to obtain a simulator executable program; Using the simulator executable program to start the Image file and then enter the Linux system; The driver is loaded in the Linux system, and the app is run to perform software simulation.

4. The method according to claim 3, characterized in that: The compiling of the simulator program to obtain a simulator executable program comprises: Develop the simulator program according to the DUT to obtain a target simulator program; Compile the target simulator program to obtain a simulator executable program.

5. The method according to claim 3, characterized in that: After running the app according to the app executable program and the driver executable program to perform software simulation, the method further includes: Recording debugging information of the app, the driver, the hybrid server program, and the simulator program; Software and hardware debugging is performed according to the debugging information and the waveform file.

6. The method according to claim 5, characterized in that: The software and hardware debugging according to the debugging information and the waveform file includes: Get the expected simulation effect; Analyzing the debugging information and the waveform file to obtain an actual simulation effect; Software and hardware debugging is performed by comparing the expected simulation effect with the actual simulation effect.

7. The method according to claim 6, characterized in that: The software and hardware debugging by comparing the expected simulation effect with the actual simulation effect includes: comparing the actual simulation effect with the expected simulation effect; If the actual simulation effect meets the expected simulation effect, no software or hardware debugging is required; Otherwise, it is necessary to improve the design and perform software and hardware debugging.

8. A software-hardware co-simulation verification chip system, used to implement the software-hardware co-simulation verification chip method of claim 1, characterized in that: The system comprises: An RTL design code writing module (301) is used to write the RTL design code of the chip; A design code compiling module (302), used to compile the RTL design code using the hsCompile to obtain a DB file; A hardware simulation module (303) is used to download the DB file to the FPGA through the hsRun to perform hardware simulation; A software program writing module (304) is used to write a Hybrid server program and a Hybrid client program according to the DUT and the Transactor, wherein the Hybrid client program includes a simulator program and a Linux system; A software simulation module (305) is used to perform software simulation in the Linux system according to the DUT and the simulator program.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executes the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 7.

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