Parameter determination method and preparation method of thin film transistor and display panel

Abstract

The invention relates to a parameter determination method and a preparation method of a thin film transistor and a display panel, and the parameter determination method comprises the steps: obtaining design parameters of the thin film transistor, the design parameters comprising at least one of threshold voltage, channel width, channel length, a ratio of the channel width to the channel length, and a preparation process coefficient; determining target parameter information according to the design parameters and a design relational expression corresponding to the thin film transistor; the design relational expression represents the incidence relation among the threshold voltage, the channel width, the channel length, the ratio of the channel width to the channel length and the preparation process coefficient. By using the parameter determination method of the thin film transistor provided by the invention, the target that each thin film transistor simultaneously meets the circuit working requirement can be realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a parameter determination method and a preparation method of a thin film transistor and a display panel. Background Art

[0002] Thin Film Transistor (TFT) has attracted more and more attention due to its excellent electrical and mechanical properties. The display matrix driving circuit layer of the Active Matrix / Organic Light Emitting Diode (AMOLD) panel is composed of a series of TFTs with different structures and different functional requirements.

[0003] In order to improve the display requirements of AMOLD, it is necessary to ensure that different TFTs can meet the circuit working requirements at the same time. However, it is difficult to achieve the goal of each TFT device meeting the circuit working requirements at the same time through process and TFT size design adjustment adopted by traditional technology. Summary of the invention

[0004] Based on this, it is necessary to provide a method for determining parameters of a thin film transistor, a preparation method and a display panel in order to address the above technical issues.

[0005] In a first aspect, an embodiment of the present application provides a method for determining parameter information of a thin film transistor, the method comprising:

[0006] Acquiring design parameters of the thin film transistor; the design parameters include at least one of a threshold voltage, a channel width, a channel length, a ratio of the channel width to the channel length, and a manufacturing process coefficient;

[0007] The target parameter information is determined according to the design relationship corresponding to the design parameters and the thin film transistor; the design relationship represents the correlation between the threshold voltage, the channel width, the channel length, the ratio of the channel width and the channel length and the manufacturing process coefficient.

[0008] In one embodiment, the method further comprises:

[0009] Determine a design relationship according to the type of thin film transistor; the design relationship corresponding to different types of thin film transistors includes different coefficient groups, and the coefficient group includes multiple different coefficients;

[0010] Optionally, the design relationship includes a first relationship, a second relationship and a third relationship, the first relationship is used to express the correlation between the threshold voltage, the manufacturing process coefficient, the channel length, and the ratio of the channel width to the channel length, the second relationship is used to express the correlation between the channel length and the ratio of the channel width to the channel length, and the third relationship is used to express the correlation between the channel width, the channel length, and the ratio of the channel width to the channel length.

[0011] In one embodiment, the target parameter information is determined according to the design parameter and the design relationship corresponding to the thin film transistor, including:

[0012] Input the channel width and channel length in the design parameters into the design relationship to calculate, and output the change information between the threshold voltage and the manufacturing process coefficient;

[0013] Optionally, the manufacturing process coefficient in the design parameters is input into the design relationship for calculation, and the change information between the threshold voltage, the channel width and the channel length is output;

[0014] Optionally, the manufacturing process coefficient in the design parameters is input into the design relationship for calculation, and the change information between the threshold voltage and the ratio of the channel width to the channel length is output.

[0015] Optionally, the target parameter information is determined according to the design parameter and the design relationship corresponding to the thin film transistor, including:

[0016] The threshold voltage, the ratio of the channel width to the channel length and the manufacturing process coefficient in the design parameters are input into the design relationship for calculation, and the channel width and the channel length are output.

[0017] In a second aspect, an embodiment of the present application provides a method for preparing a thin film transistor, the method comprising:

[0018] A thin film transistor is prepared according to the channel width and the channel length; the channel width and the channel length are calculated according to the method for determining the parameter information of the thin film transistor provided in the first aspect above.

[0019] In one embodiment, a thin film transistor is prepared according to a channel width and a channel length, comprising:

[0020] providing a substrate;

[0021] Forming a first metal layer on one side of the substrate; forming an oxide semiconductor layer on the side of the first metal layer facing away from the substrate; forming a second metal layer on the side of the oxide semiconductor layer facing away from the substrate; determining the size of the overlapping area between the oxide semiconductor layer and the second metal layer according to the channel width and the channel length;

[0022] forming three electrodes of the thin film transistor on a side of the oxide semiconductor layer facing away from the substrate;

[0023] Optionally, forming a first metal layer on one side of the substrate; forming an oxide semiconductor layer on a side of the first metal layer facing away from the substrate; and forming a second metal layer on a side of the oxide semiconductor layer facing away from the substrate, comprising:

[0024] A first metal layer is formed on one side of the substrate; a first insulating layer and a second insulating layer are sequentially formed on a side of the first metal layer facing away from the substrate;

[0025] forming an oxide semiconductor layer on a side of the second insulating layer facing away from the substrate;

[0026] A third insulating layer is formed on a side of the oxide semiconductor layer facing away from the substrate, and a second metal layer is formed on a side of the third insulating layer facing away from the substrate.

[0027] In one embodiment, three electrodes of a thin film transistor are formed on a side of the oxide semiconductor layer facing away from the substrate, including:

[0028] A first source electrode of the thin film transistor is formed on a side of the oxide semiconductor layer facing away from the substrate, and the first source electrode and the oxide semiconductor layer are electrically connected to the first metal layer through a via hole;

[0029] forming a first drain electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, wherein the first drain electrode is electrically connected to the oxide semiconductor layer;

[0030] forming a first gate of a thin film transistor on a side of the second metal layer facing away from the substrate, wherein the first gate is electrically connected to the second metal layer;

[0031] Optionally, the side of the oxide semiconductor layer facing away from the substrate forms three electrodes of the thin film transistor, and further includes:

[0032] A fourth insulating layer is formed on a side of the first source, the first gate and the first drain close to the substrate.

[0033] Optionally, three electrodes of a thin film transistor are formed on a side of the oxide semiconductor layer facing away from the substrate, and further comprising:

[0034] A second source electrode of the thin film transistor is formed on a side of the oxide semiconductor layer facing away from the substrate, the second source electrode is electrically connected to the oxide semiconductor layer, and the second source electrode is electrically connected to the first metal layer through a via hole;

[0035] A second gate of the thin film transistor is formed on a side of the second metal layer facing away from the substrate; the second gate is electrically connected to the second metal layer, and the second gate is electrically connected to the second source;

[0036] forming a second drain electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, wherein the second drain electrode is electrically connected to the oxide semiconductor layer;

[0037] Optionally, forming a first insulating layer and a second insulating layer in sequence on a side of the first metal layer facing away from the substrate includes:

[0038] forming a first insulating layer on a side of the first metal layer facing away from the substrate;

[0039] forming a third metal layer on a side of the first insulating layer facing away from the substrate;

[0040] A second insulating layer is formed on a side of the third metal layer away from the substrate.

[0041] In one embodiment, a thin film transistor is prepared according to a channel width and a channel length, comprising:

[0042] providing a substrate;

[0043] forming a third metal layer on one side of the substrate; forming an oxide semiconductor layer on a side of the third metal layer facing away from the substrate; forming a second metal layer on a side of the oxide semiconductor layer facing away from the substrate; determining the size of the overlapping region between the oxide semiconductor layer and the second metal layer according to the channel width and the channel length;

[0044] forming three electrodes of the thin film transistor on a side of the oxide semiconductor layer facing away from the substrate;

[0045] Optionally, three electrodes of a thin film transistor are formed on a side of the oxide semiconductor layer facing away from the substrate, including:

[0046] forming a third source electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, wherein the third source electrode is electrically connected to the oxide semiconductor layer;

[0047] forming a third drain electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, wherein the third drain electrode is electrically connected to the oxide semiconductor layer;

[0048] A third gate of the thin film transistor is formed on a side of the second metal layer away from the substrate. The third gate is electrically connected to the second metal layer and is electrically connected to the third metal layer through a via hole.

[0049] In a third aspect, an embodiment of the present application provides a thin film transistor, which is manufactured using the method for manufacturing a thin film transistor provided in the second aspect.

[0050] In a fourth aspect, an embodiment of the present application provides a display panel, which includes a plurality of thin film transistors provided in the third aspect.

[0051] In a fifth aspect, an embodiment of the present application provides a display device, comprising a display panel as provided in the fourth aspect above.

[0052] The embodiment of the present application provides a method for determining parameters of a thin film transistor, a preparation method and a display panel. The method for determining parameter information of a thin film transistor includes obtaining design parameters of the thin film transistor; the design parameters include at least one of a threshold voltage, a channel width, a channel length and a preparation process coefficient; according to the design parameters and the design relationship corresponding to the thin film transistor, the target parameter information is determined; the design relationship represents the correlation between the threshold voltage, the channel width, the channel length and the preparation process coefficient. The method provided by the present application can determine the preparation process coefficient and size of the thin film transistor, that is, the correlation between the channel width and the channel length, through the design relationship corresponding to the thin film transistor, so that the size of the thin film transistor can be adjusted according to the different preparation process coefficients so that the thin film transistor can meet the circuit working requirements. Corresponding to different types of thin film transistors, there are corresponding design relationships, and corresponding to different types of thin film transistors, the size that can meet the circuit working requirements can be determined according to the corresponding relationship, so that different types of thin film transistors can meet the circuit working requirements, and then the display panel can meet the circuit working requirements and improve the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For different technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 A schematic flow chart of the steps of a method for determining parameter information of a thin film transistor provided by an embodiment;

[0055] Figure 2 A schematic flow chart of steps of a method for determining parameter information of a thin film transistor provided in another embodiment;

[0056] Figure 3 A schematic flow chart of steps of a method for preparing a thin film transistor provided in an embodiment;

[0057] Figure 4 A schematic flow chart of steps of a method for preparing a thin film transistor provided in another embodiment;

[0058] Figure 5 A schematic flow chart of steps of a method for preparing a thin film transistor provided in another embodiment;

[0059] Figure 6 A schematic flow chart of steps of a method for preparing a thin film transistor provided in another embodiment;

[0060] Figure 7 A schematic flow chart of steps of a method for preparing a thin film transistor provided in another embodiment;

[0061] Figure 8 A schematic flow chart of steps of a method for preparing a thin film transistor provided in another embodiment;

[0062] Fig. 9 A schematic flow chart of steps of a method for preparing a thin film transistor provided in another embodiment;

[0063] Fig.10 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment;

[0064] Fig.11 A schematic diagram of the dimensions of the overlapping region between the oxide semiconductor layer and the second metal layer provided in one embodiment. DETAILED DESCRIPTION

[0065] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0066] The technical solution of the present application and how the technical solution of the present application solves the technical problem are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0067] It should be understood that although the terms "first", "second", etc. may be used herein to describe various objects, they do not represent any order, quantity or importance, but are only used to distinguish different components. These terms are only used to distinguish one object from another object. For example, without departing from the scope of this application, a first object may be referred to as a second object, and similarly, a second object may be referred to as a first object. "Include" or "comprising" and similar words mean that the objects or objects that appear before the word cover the objects or objects listed after the word and their equivalents, without excluding other objects or objects.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0069] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0070] Thin Film Transistor (TFT) has attracted more and more attention for its excellent electrical and mechanical properties. The display matrix driving circuit layer of the active matrix organic light emitting diode panel (Active Matrix / Organic Light Emitting Diode, AMOLD) is composed of a series of TFTs with different structures and different functional requirements. In order to improve the display requirements of AMOLD, it is necessary to ensure that different TFTs can meet the circuit working requirements at the same time. The TFT sizes required by different products are different. In traditional technology, under the same set of process, it is difficult to achieve the goal of each TFT device meeting the circuit working requirements at the same time through a single process and TFT size design adjustment. Different types of TFTs need to be designed with different sizes and process adjustments.

[0071] In view of this, the embodiment of the present application provides a method for determining parameter information of a thin film transistor, a preparation method and a display panel. The method for determining parameter information of a thin film transistor includes obtaining design parameters of the thin film transistor; the design parameters include at least one of a threshold voltage, a channel width, a channel length and a preparation process coefficient; according to the design parameters and the design relationship corresponding to the thin film transistor, the target parameter information is determined; the design relationship represents the correlation between the threshold voltage, the channel width, the channel length and the preparation process coefficient. Using the method provided by the present application, the preparation process coefficient and size of the thin film transistor, that is, the correlation between the channel width and the channel length, can be determined by the design relationship corresponding to the thin film transistor, so that the size of the thin film transistor can be adjusted according to the different preparation process coefficients, so that the thin film transistor can meet the circuit working requirements. Corresponding to different types of thin film transistors, there are corresponding design relationships, and corresponding to different types of thin film transistors, the size that can meet the circuit working requirements can be determined according to the corresponding relationship, so that different types of thin film transistors can meet the circuit working requirements, and then the display panel can meet the circuit working requirements and improve the display effect of the display panel.

[0072] See also Figure 1The present application embodiment provides a method for determining parameter information of a thin film transistor, and the present embodiment uses the method applied to a computer device as an example. In the present embodiment, the steps of the method include:

[0073] Step 100, obtaining design parameters of the thin film transistor; the design parameters include at least one of a threshold voltage, a channel width, a channel length, a ratio of the channel width to the channel length, and a manufacturing process coefficient.

[0074] The design parameters of thin film transistors refer to the parameters required to ensure that thin film transistors can work normally during the design process of thin film transistors, as well as the parameters required when preparing thin film transistors. Design parameters may include threshold voltage, channel width, channel length, the ratio of channel width to channel length, and manufacturing process coefficients. The threshold voltage refers to the voltage that needs to be applied to the gate when a clear conductive channel begins to form between the source and drain of the thin film transistor. The channel length refers to the actual length of the conductive channel between the source and drain in the thin film transistor structure. The channel width refers to the lateral width dimension occupied by the conductive channel perpendicular to the direction of carrier flow. The manufacturing process coefficient refers to the condition coefficient corresponding to the manufacturing process used when preparing thin film transistors. Different manufacturing process coefficients represent different manufacturing processes.

[0075] The design parameters of the thin film transistor can be pre-set by the user according to the actual application. The design parameters of the thin film transistor can be input by the user, and the computer device obtains it in response to the user's input. The design parameters of the thin film transistor can also be pre-stored in the memory of the computer device, and the computer device directly obtains it from the memory. The design parameters of the thin film transistor obtained by the computer device can be any one of the threshold voltage, channel width, channel length, the ratio of channel width to channel length, and the manufacturing process coefficient, or any two or any three of the threshold voltage, channel width, channel length, the ratio of channel width to channel length, and the manufacturing process coefficient. This embodiment does not limit the specific method of obtaining the design parameters of the thin film transistor, as long as its function can be achieved.

[0076] Step 110, determining target parameter information according to the design parameters and the design relationship corresponding to the thin film transistor; the design relationship represents the correlation between the threshold voltage, the channel width, the channel length, the ratio of the channel width to the channel length, and the manufacturing process coefficient.

[0077] The design relationship corresponding to the thin film transistor can be established based on the threshold voltage, channel width, channel length, ratio of channel width to channel length and manufacturing process coefficient of the thin film transistor, and is used to characterize the relationship between the threshold voltage, channel width, channel length, ratio of channel width to channel length and manufacturing process coefficient of the thin film transistor. The design relationship corresponding to the thin film transistor can be preset by the user and stored in the memory of the computer device.

[0078] After obtaining the design parameters of the thin film transistor, the computer device obtains the corresponding design relationship from the memory, and the target parameter information can be determined according to the design parameters and the corresponding design relationship. The target parameter information can be the value of other design parameters in addition to the obtained design parameters, or the association relationship between other design parameters in addition to the obtained design parameters. This embodiment does not limit the determined target parameter information.

[0079] The present application provides a method for determining parameter information of a thin film transistor, which obtains design parameters of the thin film transistor; the design parameters include at least one of a threshold voltage, a channel width, a channel length, a ratio of a channel width to a channel length, and a manufacturing process coefficient; the target parameter information is determined according to the device relationship between the design parameters and the thin film transistor; the design relationship represents the correlation between the threshold voltage, the channel width, the channel length, the ratio of the channel width to the channel length, and the manufacturing process coefficient. In this way, the manufacturing process coefficient and size of the thin film transistor, that is, the correlation between the channel width and the channel length, can be determined by the design relationship corresponding to the thin film transistor, so that the size of the thin film transistor can be adjusted according to the different manufacturing process coefficients, so that the thin film transistor can meet the circuit working requirements. Different types of thin film transistors have corresponding design relationships, and the corresponding different types of thin film transistors can determine the size that can meet the circuit working requirements according to the corresponding relationship, so that different types of thin film transistors can meet the circuit working requirements, and then the display panel can meet the circuit working requirements and improve the display effect of the display panel.

[0080] In one embodiment, the design relationship includes a first relationship, a second relationship and a third relationship. The first relationship is used to express the correlation between the threshold voltage, the manufacturing process coefficient, the channel length, and the ratio of the channel width to the channel length. The second relationship is used to express the correlation between the channel length and the ratio of the channel width to the channel length. The third relationship is used to express the correlation between the channel width, the channel length, and the ratio of the channel width to the channel length.

[0081] The design equations corresponding to the thin film transistor include a first equation established based on the threshold voltage, the manufacturing process coefficient, the channel length, and the ratio of the channel width to the channel length, a second equation established based on the channel length and the ratio of the channel width to the channel length, and a third equation established based on the channel width, the channel length, and the ratio of the channel width to the channel length. That is, after obtaining the design parameters, the computer device inputs the design parameters into the first equation, the second equation, and the third equation, and by solving the first equation, the second equation, and the third equation, the target parameter information can be determined.

[0082] In this embodiment, it is described that the design relational expression includes a first relational expression, a second relational expression and a third relational expression, and the target parameter information can be determined more accurately through the first relational expression, the second relational expression and the third relational expression.

[0083] In one embodiment, the method for determining parameter information of a thin film transistor further includes:

[0084] The design relationship is determined according to the type of thin film transistor; the design relationship corresponding to different types of thin film transistors includes different coefficient groups, and the coefficient group includes a plurality of different coefficients.

[0085] Different types of thin film transistors correspond to different design equations. After obtaining the design parameters of the thin film transistor, the computer device first determines the type of the thin film transistor, and then searches for the corresponding design equation according to the type of the thin film transistor.

[0086] The types of thin film transistors may include thin film transistors with top gate (TG) structures, thin film transistors with bottom gate (BG) structures, and thin film transistors with dual gate (DG) structures. The design relationship corresponding to the thin film transistor includes a coefficient group, and the coefficient group includes multiple different coefficients. The design relationship of different types of thin film transistors includes different coefficient groups.

[0087] In an optional embodiment, for a thin film transistor with a TG structure, the design relationship can be expressed as:

[0088]

[0089] in, represents the threshold voltage of the thin film transistor with TG structure, A represents the manufacturing process coefficient of the thin film transistor with TG structure, represents the channel length of the TG structure thin film transistor, represents the channel width of the TG structure thin film transistor, It represents the ratio of the channel width to the channel length of the TG structure thin film transistor. - is a coefficient group of a thin film transistor of TG structure. Specifically, It can be 13.7, can be 2.336, It can be 0.5, It can be 3.3, It can be -0.025, It can be 4.7, It can be 0.2, can be 0.8327, can be 4.0882, It can be 0.8. Due to fluctuations in the actual process, the actual channel width W of the TG structure thin film transistor in the actual product is TG The actual channel length L TG Can be located in W TG ±0.2um and L TG Within ±0.2um range.

[0090] In an optional embodiment, for a thin film transistor with a BG structure, the design relationship can be expressed as:

[0091]

[0092] in, represents the threshold voltage of the thin film transistor with BG structure, A represents the manufacturing process coefficient of the thin film transistor with BG structure, represents the channel length of the BG structure thin film transistor, represents the channel width of the BG structure thin film transistor, It represents the ratio of the channel width to the channel length of the BG structure thin film transistor. - is a coefficient group of a thin film transistor of a BG structure. Specifically, It can be 20.9, can be 2.633, It can be 0.3, It can be 8.7, can be -0.0075, It can be 6.2, It can be 0.18, can be 0.2877, can be 5.7964, It can be 0.8. Due to fluctuations in the actual process, the actual channel width W of the BG structure thin film transistor in the actual product is BG The actual channel length L BG Can be located in W BG±0.2um and L BG Within ±0.2um range.

[0093] In an optional embodiment, for a DG structure thin film transistor, the design relationship can be expressed as:

[0094]

[0095] in, represents the threshold voltage of the DG structure thin film transistor, A represents the manufacturing process coefficient of the DG structure thin film transistor, represents the channel length of the DG structure thin film transistor, represents the channel width of the DG structure thin film transistor, It represents the ratio of the channel width to the channel length of the DG structure thin film transistor. - is a coefficient group of a thin film transistor of a DG structure. Specifically, can be 6.73, can be 0.9277, It can be 0.5, It can be 5.8, can be -0.0025, It can be 7.8, It can be 0.04, It can be 1.4708, can be 6.7063, It can be 0.8. Due to fluctuations in the actual process, the actual channel width W of the DG structure thin film transistor in the actual product is DG The actual channel length L DG Can be located in W DG ±0.2um and L DG Within ±0.2um range.

[0096] In this embodiment, different design relationships corresponding to different types of thin film transistors are described. In this way, for different types of thin film transistors in a display panel, the corresponding design relationships can be used to determine the sizes of different types of thin film transistors that meet the circuit working requirements under the same preparation process, thereby ensuring that the different types of thin film transistors in the prepared display panel can meet the circuit working requirements, thereby improving the display effect of the display panel including the different types of thin film transistors.

[0097] See also Figure 2 In one embodiment, a method for determining target parameter information according to a design relationship between a design parameter and a thin film transistor includes:

[0098] Step 200: Input the channel width and channel length in the design parameters into the design relationship to perform calculations, and output the change information between the threshold voltage and the manufacturing process coefficient.

[0099] When the design parameters obtained by the computer device are the channel width and channel length of the thin film transistor, the ratio of the channel width to the channel length can be determined based on the channel length and the channel width. By inputting the channel width, the channel length, and the ratio of the channel width to the channel length into the design relationship for calculation, the change information between the threshold voltage and the manufacturing process coefficient can be obtained. In other words, the threshold voltage of the thin film transistor under different manufacturing processes can be determined.

[0100] In this embodiment, the change information between the threshold voltage of the thin film transistor and the manufacturing process coefficient can be determined through the relationship corresponding to the thin film transistor. This makes it convenient for the user to set the threshold voltage of the thin film transistor according to the manufacturing process, or to select the corresponding manufacturing process according to the threshold voltage of the thin film transistor, thereby ensuring that the thin film transistor can meet the circuit working requirements.

[0101] Please continue to see Figure 2 In one embodiment, another implementation method of determining target parameter information according to a design relationship between a design parameter and a thin film transistor includes the following steps:

[0102] Step 210: Input the manufacturing process coefficients in the design parameters into the design relationship for calculation, and output the change information between the threshold voltage, the channel width and the channel length.

[0103] When the design parameters obtained by the computer equipment are the manufacturing process coefficients of the thin film transistor, the manufacturing process coefficients are input into the design relationship for calculation, and the change information between the threshold voltage, channel width and channel length can be obtained. In other words, the correlation between the threshold voltage and the channel width and channel length under the same manufacturing process can be determined, that is, the channel width and channel length corresponding to different threshold voltages.

[0104] In this embodiment, the change information between the threshold voltage and the channel width and channel length in the thin film transistor can be determined through the relationship corresponding to the thin film transistor. This makes it convenient for the user to set the channel length and channel width of the thin film transistor according to the threshold voltage, or determine the corresponding threshold voltage according to the channel length and channel width of the thin film transistor, thereby ensuring that the thin film transistor can meet the circuit operation requirements.

[0105] Please continue to see Figure 2 In one embodiment, another implementation method of determining target parameter information according to a design relationship between a design parameter and a thin film transistor includes the following steps:

[0106] Step 220: Input the manufacturing process coefficient in the design parameters into the design relationship to perform calculation, and output the change information between the threshold voltage and the ratio of the channel width to the channel length.

[0107] When the design parameters obtained by the computer equipment are the manufacturing process coefficients of the thin film transistor, the manufacturing process coefficients are input into the design relationship for calculation, and the change information between the threshold voltage and the ratio of the channel width to the channel length can be obtained. That is to say, the correlation between the threshold voltage and the ratio of the channel width to the channel length under the same manufacturing process can be determined, that is, the ratio of the channel width to the channel length corresponding to different threshold voltages.

[0108] In this embodiment, the change information between the threshold voltage and the ratio of the channel width and the channel length in the thin film transistor can be determined through the relationship corresponding to the thin film transistor. This makes it convenient for the user to set the ratio of the channel length and the channel width of the thin film transistor according to the threshold voltage, or to determine the corresponding threshold voltage according to the ratio of the channel length and the channel width of the thin film transistor, thereby ensuring that the thin film transistor can meet the circuit working requirements.

[0109] Please continue to see Figure 2 In one embodiment, another implementation method of determining target parameter information according to a design relationship between a design parameter and a thin film transistor includes:

[0110] Step 230: Input the threshold voltage, the ratio of the channel width to the channel length, and the manufacturing process coefficient in the design parameters into the design relationship for calculation, and output the channel width and the channel length.

[0111] When the design parameters acquired by the computer device are the threshold voltage, the ratio of the channel width to the channel length, and the manufacturing process coefficient of the thin film transistor, the threshold voltage, the ratio of the channel width to the channel length, and the manufacturing process coefficient are input into the design relationship for calculation, and the channel width and channel length of the thin film transistor can be obtained. In other words, the channel width and channel length of the thin film transistor can be determined under the set threshold voltage, manufacturing process coefficient, channel width, and channel length.

[0112] In this embodiment, the channel width and channel length can be calculated through the design relationship corresponding to the thin film transistor. For different types of thin film transistors, the corresponding design relationship can be used to determine the channel width and channel length of different types of thin film transistors under the same preparation process while reaching the threshold voltage, thereby ensuring that different types of thin film transistors can meet circuit operating requirements.

[0113] In an optional embodiment, the values ​​of the design parameters corresponding to the design relationships corresponding to different types of thin film transistors may be shown in the following table:

[0114]

[0115]

[0116]

[0117]

[0118] In an optional embodiment, the design parameters of the thin film transistor in the display panel can be determined through experiments as shown in the following table:

[0119]

[0120] It can be seen from the above table that for the DG structure TFTs in the display panel, the threshold voltages of the two TFTs under the same preparation process are quite different. If the threshold voltages of the two TFTs are required to be the same, one of the TFTs will exceed the circuit working requirements.

[0121]

[0122] By using the design relationship corresponding to the thin film transistor provided in this application and determining the target parameter information, the threshold voltages of the two DG structure TFTs are pulled to the same level, so that the two DG structure TFTs can meet the circuit operation requirements at the same time under the same preparation process.

[0123] The present invention provides a method for manufacturing a thin film transistor, the method comprising:

[0124] A thin film transistor is prepared according to the channel width and the channel length; the channel width and the channel length are calculated according to the method for determining the parameter information of the thin film transistor provided in the above embodiment.

[0125] When preparing thin film transistors in a display panel, different types of thin film transistors can be prepared according to the channel width and channel length calculated in the above embodiment. This embodiment does not limit the specific method for preparing the thin film transistor, as long as its function can be achieved.

[0126] The channel width and channel length in the method for preparing a thin film transistor provided in this embodiment are calculated using the method for determining the parameters of the thin film transistor provided in the above embodiment. The preparation method has all the beneficial effects of the method for determining the parameters of the thin film transistor provided in the above embodiment, which will not be repeated here.

[0127] See also Figure 3In one embodiment, a method for preparing a thin film transistor according to a channel width and a channel length is provided, and the steps of the method include:

[0128] Step 300: Provide a substrate.

[0129] The substrate may be a substrate made of an inorganic material, a substrate made of an organic material, or a composite substrate in which a substrate made of an inorganic material and a substrate made of an organic material are stacked.

[0130] Step 310, forming a first metal layer on one side of the substrate; forming an oxide semiconductor layer on the side of the first metal layer facing away from the substrate; forming a second metal layer on the side of the oxide semiconductor layer facing away from the substrate; determining the size of the overlapping area between the oxide semiconductor layer and the second metal layer according to the channel width and the channel length.

[0131] A first metal layer is formed on one side of the substrate. The first metal layer may be formed by patterning through a photolithography process. The material of the first metal layer may be molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu). The first metal layer may be a single layer or multiple layers made of any one or more alloys of the above materials. This embodiment does not limit the material and number of layers of the first metal layer.

[0132] An oxide semiconductor layer is formed on the side of the first metal layer facing away from the substrate. The oxide semiconductor layer may be formed by forming an oxide semiconductor material into a film and then patterning it. The material of the oxide semiconductor layer may be a material containing at least one oxide of indium (In), gallium (Ga), zinc (Zn), tin (Sn) or hafnium (Hf). Specifically, the oxide semiconductor layer may include tin zinc oxide (TZO), gallium tin oxide (TGO), indium tin zinc oxide (ITZO), indium tin gallium oxide (TZO) indium tin gallium oxide (ITGO) or indium tin zinc gallium oxide (ITZGO). This embodiment does not limit the material of the oxide semiconductor layer.

[0133] A second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate. The second metal layer may be the same as or different from the first metal layer. The description of the second metal layer may refer to the specific description of the first metal layer above, and will not be repeated here.

[0134] During the preparation of the oxide semiconductor layer and the second metal layer, the size of the overlapping area between the oxide semiconductor layer and the second metal layer is determined based on the calculated channel width and channel length. The length of the overlapping area in the first direction is the channel length, and the width in the second direction is the channel width. The first direction and the second direction are perpendicular to each other.

[0135] Step 320 : forming three electrodes of the thin film transistor on a side of the oxide semiconductor layer facing away from the substrate.

[0136] The three electrodes of the thin film transistor, namely the gate, the drain and the source, are formed on the side of the oxide semiconductor layer away from the substrate. A thin film transistor can be formed by the prepared first metal layer, the oxide semiconductor layer, the second metal layer and the three electrodes of the thin film transistor.

[0137] In an optional embodiment, a fourth metal layer is formed on a side of the oxide semiconductor layer facing away from the substrate, and the fourth metal layer is etched to form three electrodes of the thin film transistor.

[0138] In this embodiment, a first metal layer is formed on one side of the substrate; an oxide semiconductor layer is formed on the side of the first metal layer facing away from the substrate; a second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate; the size of the overlapping area of ​​the oxide semiconductor layer and the second metal layer is determined according to the channel width and channel length; and three electrodes of the thin film transistor are formed on the side of the oxide semiconductor layer facing away from the substrate. In this way, the thin film transistor prepared by the calculated channel width and channel length can ensure that the thin film transistor meets the circuit working requirements, thereby ensuring that the different types of thin film transistors included meet the circuit working requirements, and further improving the display effect of the display panel including different types of thin film transistors.

[0139] In one embodiment, Figure 4 As shown, a method for implementing the method involves forming a first metal layer on one side of a substrate; forming an oxide semiconductor layer on a side of the first metal layer away from the substrate; and forming a second metal layer on a side of the oxide semiconductor layer away from the substrate. The steps of the method include:

[0140] Step 400: forming a first metal layer on one side of a substrate; and sequentially forming a first insulating layer and a second insulating layer on a side of the first metal layer facing away from the substrate.

[0141] After forming a first metal layer on one side of the substrate, two insulating layers are formed in sequence on the side of the first metal layer away from the substrate, namely, a first insulating layer and a second insulating layer. The first insulating layer may be one or more inorganic layers. The first insulating layer may be one or more layers of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), and a silicon oxynitride layer (SiON) formed by chemical vapor deposition (CVD) technology. The second insulating layer may be the same as or different from the first insulating layer, and the description of the second insulating layer may refer to the specific description of the first insulating layer. The first insulating layer may be a capacitor insulating layer, and the second insulating layer may be a gate insulating layer. Specifically, the thickness of the capacitor insulating layer may be 1300A, and the thickness of the gate insulating layer may be 1400A or 3000A.

[0142] Step 410 , forming an oxide semiconductor layer on a side of the second insulating layer facing away from the substrate.

[0143] Step 420 , forming a third insulating layer on a side of the oxide semiconductor layer facing away from the substrate, and forming a second metal layer on a side of the third insulating layer facing away from the substrate.

[0144] An oxide semiconductor layer is sequentially formed on the side of the second insulating layer facing away from the substrate, and a third insulating layer is formed by film formation using CVD technology on the side of the oxide semiconductor layer facing away from the substrate. A second metal layer is formed by patterning through a photolithography process on the side of the third insulating layer facing away from the substrate. The third insulating layer and the first insulating layer may be the same or different. The third insulating layer is a gate insulating layer. The description of the third insulating layer can refer to the specific description of the first insulating layer in the above embodiment, and will not be repeated here.

[0145] In this embodiment, a first metal layer is formed on one side of the substrate; a first insulating layer and a second insulating layer are formed on the side of the first metal layer facing away from the substrate; an oxide semiconductor layer is formed on the side of the second insulating layer facing away from the substrate; a third insulating layer is formed on the side of the oxide semiconductor layer facing away from the substrate, and a second metal layer is formed on the side of the third insulating layer facing away from the substrate. In this embodiment, the first insulating layer and the second insulating layer are formed between the first metal layer and the oxide semiconductor layer, and the third insulating layer is formed between the oxide semiconductor layer and the second metal layer, so that the prepared thin film transistor can work normally.

[0146] In one embodiment, Figure 5 As shown, a method for implementing three electrodes of a thin film transistor is formed on a side of the oxide semiconductor layer away from the substrate, and the steps of the method include:

[0147] Step 500: forming a first source electrode of a thin film transistor on a side of the oxide semiconductor layer facing away from the substrate, and the first source electrode and the oxide semiconductor layer are electrically connected to the first metal layer through a via hole.

[0148] A first source electrode of the thin film transistor is formed on a side of the oxide semiconductor layer and the second metal layer facing away from the substrate, and the first source electrode is electrically connected to the oxide semiconductor layer and the first metal layer through a via hole, that is, the first source electrode is connected to the oxide semiconductor layer through a via hole provided on the third insulating layer, and the first source electrode is electrically connected to the first metal layer through via holes on the third insulating layer, the first insulating layer, and the second insulating layer, so that the first source electrode and the first metal layer have the same potential.

[0149] Step 510: forming a first drain electrode of the thin film transistor on a side of the oxide semiconductor layer facing away from the substrate, wherein the first drain electrode is electrically connected to the oxide semiconductor layer.

[0150] A first drain electrode of the thin film transistor is formed on the side of the oxide semiconductor layer and the second metal layer away from the substrate, and the first drain electrode is electrically connected to the oxide semiconductor layer through a via hole on the third insulating layer. The first drain electrode and the first source electrode are located in the same layer.

[0151] Step 520: forming a first gate of a thin film transistor on a side of the second metal layer facing away from the substrate, wherein the first gate is electrically connected to the second metal layer.

[0152] A first gate of a thin film transistor is formed on a side of the second metal layer away from the substrate, the first gate being electrically connected to the second metal layer and being located in the same layer as the first source and the first drain.

[0153] In one embodiment, after the second metal layer is formed on a layer of the oxide semiconductor layer away from the substrate, a fourth insulating layer is formed on the side of the second metal layer away from the substrate. In other words, a fourth insulating layer is formed on the side of the first source, the first gate and the first drain close to the substrate. The fourth insulating layer may be an interlayer insulating layer. Specifically, the thickness of the interlayer insulating layer may be 5500A. In this case, the first source of the thin film transistor is formed on the side of the fourth insulating layer away from the substrate, and vias are provided on the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer. The first source is electrically connected to the first metal layer through the vias provided on the fourth insulating layer, the third insulating layer, the first insulating layer and the second insulating layer. The first drain is electrically connected to the oxide semiconductor layer through the vias on the fourth insulating layer and the third insulating layer. The first gate is electrically connected to the second metal layer by passing through the vias on the fourth insulating layer.

[0154] In this embodiment, a first source electrode of a thin film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the first source electrode and the oxide semiconductor layer are electrically connected to the first metal layer through a via hole; a first drain electrode of the thin film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the first drain electrode is electrically connected to the oxide semiconductor layer; a first gate electrode of the thin film transistor is formed on the side of the second metal layer away from the substrate, and the first gate electrode is electrically connected to the second metal layer. In this way, a TG structure thin film transistor can be formed, and different potential electric fields are applied to the first gate electrode of the TG structure thin film transistor to control the opening and closing of the thin film transistor.

[0155] In one embodiment, Figure 6 As shown, a method for implementing three electrodes of a thin film transistor is formed on a side of the oxide semiconductor layer away from the substrate, and the steps of the method include:

[0156] Step 600: forming a second source electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, wherein the second source electrode is electrically connected to the oxide semiconductor layer.

[0157] A second source electrode of the thin film transistor is formed on a side of the oxide semiconductor layer and the second metal layer away from the base, the second source electrode is electrically connected to the oxide semiconductor layer through a via hole provided on the third insulating layer, and the second source electrode is electrically connected to the first metal layer through a via hole provided on the third insulating layer, the second insulating layer and the first insulating layer.

[0158] Step 610, forming a second gate of the thin film transistor on a side of the second metal layer away from the substrate; the second source is electrically connected to the first metal layer through the via hole, and is electrically connected to the second metal layer through the second gate.

[0159] A second gate of the thin film transistor is formed on the side of the second metal layer away from the substrate, the second gate is electrically connected to the second metal layer, and the second gate is electrically connected to the second source, so that the second source, the first metal layer, and the second metal layer have the same potential. The second gate and the second source are located in the same layer.

[0160] Step 620 , forming a second drain of the thin film transistor on a side of the oxide semiconductor layer facing away from the substrate.

[0161] A second drain electrode of the thin film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the second drain electrode is electrically connected to the oxide semiconductor layer through a via hole on the third insulating layer. The second drain electrode and the second source electrode are located in the same layer.

[0162] In one embodiment, after forming a second metal layer on a layer of the oxide semiconductor layer away from the substrate, a fourth insulating layer is formed on the side of the second metal layer away from the substrate. In other words, a fourth insulating layer is formed on the side of the first source, the first gate, and the first drain close to the substrate. In this case, a second source of the thin film transistor is formed on the side of the fourth insulating layer away from the substrate, and vias are provided on the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer. The second source is electrically connected to the first metal layer through the vias provided on the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer. The second drain is electrically connected to the oxide semiconductor layer through the vias on the fourth insulating layer and the third insulating layer. The second gate is electrically connected to the second metal layer by passing through the vias on the fourth insulating layer.

[0163] In this embodiment, a second source electrode of the thin film transistor is formed on the side of the oxide semiconductor layer away from the substrate, the second source electrode is electrically connected to the oxide semiconductor layer, and the second source electrode is electrically connected to the first metal layer through a via hole; a second gate electrode of the thin film transistor is formed on the side of the second metal layer away from the substrate, the second gate electrode is electrically connected to the second metal layer, and the second gate electrode is electrically connected to the second source electrode; a second drain electrode of the thin film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the second drain electrode is electrically connected to the oxide semiconductor layer. In this way, a thin film transistor with a BG structure can be formed, and different potential electric fields are applied through the second gate electrode of the thin film transistor with the BG structure to control the opening and closing of the thin film transistor.

[0164] In one embodiment, Figure 7 As shown, an implementation method involves sequentially forming a first insulating layer and a second insulating layer on a side of a first metal layer away from a substrate, and the steps of the implementation method include:

[0165] Step 700: forming a first insulating layer on a side of the first metal layer facing away from the substrate.

[0166] Step 710 , forming a third metal layer on a side of the first insulating layer facing away from the substrate.

[0167] Step 720 , forming a second insulating layer on a side of the third metal layer facing away from the substrate.

[0168] The third metal layer may be the same as or different from the first metal layer. The description of the material and structure of the third insulating layer can refer to the specific description of the material and structure of the first metal layer in the above embodiment, which will not be repeated here. After forming the first insulating layer on the side of the first metal layer away from the substrate, the third metal layer is patterned by a photolithography process on the side of the first insulating layer away from the substrate. After forming the third metal layer, a second insulating layer is formed on the side of the third metal layer away from the substrate.

[0169] In this embodiment, a first insulating layer is formed on the side of the first metal layer facing away from the substrate, and a third metal layer is formed on the side of the first insulating layer facing away from the substrate; a second insulating layer is formed on the side of the third metal layer facing away from the substrate, so that the first metal layer, the second metal layer and the oxide are isolated from the semiconductor layer by the first insulating layer and the second insulating layer, thereby ensuring the normal operation of the prepared thin film transistor.

[0170] In one embodiment, Figure 8 As shown, another implementation method of preparing a thin film transistor according to a channel width and a channel length is involved, and the steps of the implementation method include:

[0171] Step 800: Provide a substrate.

[0172] Step 810, forming a third metal layer on one side of the substrate; forming an oxide semiconductor layer on the side of the third metal layer facing away from the substrate; forming a second metal layer on the side of the oxide semiconductor layer facing away from the substrate; determining the size of the overlapping area between the oxide semiconductor layer and the second metal layer according to the channel width and the channel length.

[0173] The description of the materials and structures of the substrate, the third metal layer, the oxide semiconductor layer, and the second metal layer may refer to the specific description of the above embodiments, and will not be repeated here.

[0174] A third metal layer is formed on one side of the substrate by patterning through a photolithography process, and an oxide semiconductor layer is formed on the side of the third metal layer facing away from the substrate; and a second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate. According to the channel width and channel length calculated in the above embodiment, the size of the overlapping area between the oxide semiconductor layer and the second metal layer can be determined. The length of the overlapping area in the first direction is the channel length, and the width in the second direction is the channel width.

[0175] In an optional embodiment, a second insulating layer is formed between the third metal layer and the oxide semiconductor layer, and a third insulating layer is formed between the oxide semiconductor layer and the second metal layer.

[0176] Step 820 , forming three electrodes of the thin film transistor on a side of the oxide semiconductor layer facing away from the substrate.

[0177] The three electrodes of the thin film transistor, namely the gate, the drain and the source, are formed on the side of the oxide semiconductor layer away from the substrate. A thin film transistor can be formed by the prepared third metal layer, the oxide semiconductor layer, the second metal layer and the three electrodes of the thin film transistor.

[0178] In an optional embodiment, a fourth metal layer is formed on a side of the oxide semiconductor layer facing away from the substrate, and the fourth metal layer is etched to form three electrodes of the thin film transistor.

[0179] In this embodiment, a third metal layer is formed on one side of the substrate; an oxide semiconductor layer is formed on the side of the third metal layer facing away from the substrate; a second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate; the size of the overlapping area between the oxide semiconductor layer and the second metal layer is determined according to the channel width and the channel length; and three electrodes of the thin film transistor are formed on the side of the oxide semiconductor layer facing away from the substrate. In this way, the thin film transistor prepared by the calculated channel width and channel length can ensure that the thin film transistor meets the circuit working requirements, thereby ensuring that the different types of thin film transistors included meet the circuit working requirements, and further improving the display effect of the display panel including different types of thin film transistors.

[0180] In one embodiment, Fig. 9 As shown, a method for implementing three electrodes of a thin film transistor is formed on a side of the oxide semiconductor layer away from the substrate, and the steps of the method include:

[0181] Step 900: forming a third source electrode of the thin film transistor on a side of the oxide semiconductor layer facing away from the substrate, wherein the third source electrode is electrically connected to the oxide semiconductor layer.

[0182] A fourth metal layer is formed on the side of the oxide semiconductor layer away from the substrate, and the fourth metal layer is etched to form a third source electrode of the thin film transistor. The third source electrode is electrically connected to the oxide semiconductor layer.

[0183] In an optional embodiment, a second insulating layer is formed between the third metal layer and the oxide semiconductor layer, a third insulating layer is formed between the oxide semiconductor layer and the second metal layer, and a fourth insulating layer is formed on a side of the second metal layer away from the substrate. The third source is electrically connected to the oxide semiconductor layer through vias on the fourth insulating layer and the third insulating layer.

[0184] Step 910: forming a third drain electrode of the thin film transistor on a side of the oxide semiconductor layer facing away from the substrate, wherein the third drain electrode is electrically connected to the oxide semiconductor layer.

[0185] A fourth metal layer is formed on a side of the oxide semiconductor layer facing away from the substrate. The fourth metal layer is etched to form a third drain electrode of the thin film transistor. The third drain electrode is electrically connected to the oxide semiconductor layer.

[0186] In an optional embodiment, a second insulating layer is formed between the third metal layer and the oxide semiconductor layer, a third insulating layer is formed between the oxide semiconductor layer and the second metal layer, and a fourth insulating layer is formed on a side of the second metal layer away from the substrate. The third drain is electrically connected to the oxide semiconductor layer through via holes on the fourth insulating layer and the third insulating layer.

[0187] Step 920: forming a third gate of the thin film transistor on a side of the second metal layer facing away from the substrate, wherein the third gate is electrically connected to the second metal layer, and the third gate is electrically connected to the third metal layer through a via hole.

[0188] A fourth metal layer is formed on a side of the second metal layer facing away from the substrate, and the fourth metal layer is etched to form a third gate of the thin film transistor.

[0189] In an optional embodiment, a second insulating layer is formed between the third metal layer and the oxide semiconductor layer, a third insulating layer is formed between the oxide semiconductor layer and the second metal layer, and a fourth insulating layer is formed on a side of the second metal layer away from the substrate. The third gate is electrically connected to the second metal layer through a via hole on the fourth insulating layer, and the third gate is electrically connected to the third metal layer through via holes on the fourth insulating layer, the third insulating layer, and the second insulating layer.

[0190] In this embodiment, a third source of the thin film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the third source is electrically connected to the oxide semiconductor layer; a third drain of the thin film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the third drain is electrically connected to the oxide semiconductor layer; a third gate of the thin film transistor is formed on the side of the second metal layer away from the substrate, and the third gate is electrically connected to the second metal layer, and the third gate is electrically connected to the third metal layer through a via hole. In this way, a DG structure thin film transistor can be formed, and different potential electric fields are applied to the third gate of the DG structure thin film transistor to control the opening and closing of the thin film transistor.

[0191] In an optional embodiment, one or more inorganic layers of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), i.e., a first inorganic layer, are formed between the substrate and the first metal layer. At least one buffer layer and at least one protective layer formed of a polyimide material are formed between the substrate and the first inorganic layer.

[0192] It should be understood that, although the various steps in the flowchart in the figure are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0193] An embodiment of the present application provides a thin film transistor, which is manufactured by using the method for manufacturing a thin film transistor provided in the above embodiment.

[0194] The thin film transistor provided in this embodiment is manufactured by the method for manufacturing the thin film transistor provided in the above embodiment. The thin film transistor has all the beneficial effects of the method for manufacturing the thin film transistor, which will not be described in detail here.

[0195] An embodiment of the present application provides a display panel, which includes a plurality of thin film transistors provided in the above embodiments.

[0196] The display panel provided in this embodiment includes a plurality of thin film transistors provided in the above embodiments, and the display panel has all the beneficial effects of the thin film transistors, which will not be described in detail here.

[0197] In an optional embodiment, the display panel includes a TG structure thin film transistor, a BG structure thin film transistor and a DG structure thin film transistor. Fig.10 shown.

[0198] The display panel includes a substrate 1, a buffer layer 2 disposed on one side of the substrate 1, a first metal layer 7a formed on a side of the buffer layer 2 facing away from the substrate 1, a first insulating layer 3 formed on a side of the first metal layer 7a facing away from the substrate 1, a third metal layer 7b formed on a side of the first insulating layer 3 facing away from the substrate 1, a second insulating layer 4 formed on a side of the third metal layer 7b facing away from the substrate 1, an oxide semiconductor layer 5 formed on a side of the second insulating layer 4 facing away from the substrate 1, a third insulating layer 6 formed on a side of the oxide semiconductor layer 5 facing away from the substrate 1, and a A second metal layer 7c is formed on one side, a fourth insulating layer 11 is formed on the side of the second metal layer 7c away from the substrate 1, a first source 9a, a first gate 9b and a first drain 9c of the thin film transistor with a TG structure are formed on the side of the fourth insulating layer 11 away from the substrate 1, a second source 8a, a second gate 8b and a second drain 8c of the thin film transistor with a BG structure are formed on the side of the fourth insulating layer 11 away from the substrate 1, and a third source 10a, a third gate 10b and a third drain 10c of the thin film transistor with a DG structure are formed on the side of the fourth insulating layer 11 away from the substrate 1.

[0199] The size of the overlapping area between the oxide semiconductor layer and the second metal layer in the thin film transistor of the display panel is as follows: Fig.11 The length of the overlapping region in the first direction X is the channel length of the thin film transistor, and the length in the second direction Y is the channel width of the thin film transistor.

[0200] One embodiment of the present application provides a display device, including a display panel as provided in the above embodiment. The display device can be a laptop, a mobile phone, a wireless device, a personal digital assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, a car display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rear-view camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, etc.

[0201] The display device provided in the present application includes a display panel, and the display device has all the beneficial effects of the display panel, which will not be described in detail here.

[0202] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0203] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for determining parameter information of a thin film transistor, characterized in that: The method comprises: Acquiring design parameters of the thin film transistor; the design parameters include at least one of a threshold voltage, a channel width, a channel length, a ratio of the channel width to the channel length, and a manufacturing process coefficient; Target parameter information is determined according to the design parameters and the design relationship corresponding to the thin film transistor; the design relationship represents the correlation between the threshold voltage, the channel width, the channel length, the ratio of the channel width to the channel length and the manufacturing process coefficient.

2. The method according to claim 1, characterized in that The method further comprises: Determine the design relationship according to the type of the thin film transistor; the design relationship corresponding to different types of thin film transistors includes different coefficient groups, and the coefficient group includes a plurality of different coefficients; Optionally, the design relationship includes a first relationship, a second relationship and a third relationship, the first relationship is used to express the correlation between the threshold voltage, the preparation process coefficient, the channel length, and the ratio of the channel width to the channel length, the second relationship is used to express the channel length, and the correlation between the ratio of the channel width to the channel length, and the third relationship is used to express the correlation between the channel width, the channel length, and the ratio of the channel width to the channel length.

3. The method according to claim 1 or 2, characterized in that: The step of determining target parameter information according to the design parameter and a design relationship corresponding to the thin film transistor includes: Inputting the channel width and the channel length in the design parameters into the design relationship to perform calculation, and outputting the change information between the threshold voltage and the manufacturing process coefficient; Optionally, the manufacturing process coefficient in the design parameter is input into the design relationship to perform calculation, and the variation information among the threshold voltage, the channel width and the channel length is output; Optionally, the manufacturing process coefficient in the design parameter is input into the design relationship to perform calculation, and the change information between the threshold voltage and the ratio of the channel width to the channel length is output; Optionally, determining target parameter information according to the design parameter and a design relationship corresponding to the thin film transistor includes: The threshold voltage, the ratio of the channel width to the channel length, and the manufacturing process coefficient among the design parameters are input into the design relationship to perform calculation, and the channel width and the channel length are output.

4. A method for preparing a thin film transistor, characterized in that: The method comprises: A thin film transistor is prepared according to a channel width and a channel length; the channel width and the channel length are calculated according to the method for determining parameter information of a thin film transistor according to any one of claims 1-3.

5. The method according to claim 4, characterized in that The method of preparing a thin film transistor according to the channel width and the channel length comprises: providing a substrate; forming a first metal layer on one side of the substrate; forming an oxide semiconductor layer on a side of the first metal layer away from the substrate; forming a second metal layer on a side of the oxide semiconductor layer away from the substrate; determining the size of an overlapping region between the oxide semiconductor layer and the second metal layer according to the channel width and the channel length; forming three electrodes of the thin film transistor on a side of the oxide semiconductor layer away from the substrate; Optionally, forming a first metal layer on one side of the substrate; forming an oxide semiconductor layer on a side of the first metal layer away from the substrate; and forming a second metal layer on a side of the oxide semiconductor layer away from the substrate comprises: forming the first metal layer on one side of the substrate; and sequentially forming a first insulating layer and a second insulating layer on a side of the first metal layer away from the substrate; forming the oxide semiconductor layer on a side of the second insulating layer away from the substrate; A third insulating layer is formed on a side of the oxide semiconductor layer away from the substrate, and the second metal layer is formed on a side of the third insulating layer away from the substrate.

6. The method according to claim 5, characterized in that The three electrodes of the thin film transistor are formed on a side of the oxide semiconductor layer away from the substrate, comprising: forming a first source electrode of the thin film transistor on a side of the oxide semiconductor layer facing away from the substrate, and the first source electrode and the oxide semiconductor layer are electrically connected to the first metal layer through a via hole; forming a first drain electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, wherein the first drain electrode is electrically connected to the oxide semiconductor layer; forming a first gate of the thin film transistor on a side of the second metal layer facing away from the substrate, wherein the first gate is electrically connected to the second metal layer; Optionally, the side of the oxide semiconductor layer facing away from the substrate forms three electrodes of the thin film transistor, further comprising: forming a fourth insulating layer on a side of the first source, the first gate and the first drain close to the substrate; Optionally, the three electrodes of the thin film transistor are formed on a side of the oxide semiconductor layer away from the substrate, further comprising: forming a second source electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, the second source electrode being electrically connected to the oxide semiconductor layer, and the second source electrode being electrically connected to the first metal layer through a via hole; A second gate of the thin film transistor is formed on a side of the second metal layer away from the substrate; the second gate is electrically connected to the second metal layer, and the second gate is electrically connected to the second source; forming a second drain electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, wherein the second drain electrode is electrically connected to the oxide semiconductor layer; Optionally, forming a first insulating layer and a second insulating layer in sequence on a side of the first metal layer facing away from the substrate includes: forming the first insulating layer on a side of the first metal layer facing away from the substrate; forming a third metal layer on a side of the first insulating layer facing away from the substrate; The second insulating layer is formed on a side of the third metal layer away from the substrate.

7. The method according to claim 4, characterized in that The method of preparing a thin film transistor according to the channel width and the channel length comprises: providing a substrate; forming a third metal layer on one side of the substrate; forming an oxide semiconductor layer on a side of the third metal layer away from the substrate; forming a second metal layer on a side of the oxide semiconductor layer away from the substrate; and determining the size of an overlapping region between the oxide semiconductor layer and the second metal layer according to the channel width and the channel length; forming three electrodes of the thin film transistor on a side of the oxide semiconductor layer away from the substrate; Optionally, forming three electrodes of the thin film transistor on a side of the oxide semiconductor layer away from the substrate includes: forming a third source electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, wherein the third source electrode is electrically connected to the oxide semiconductor layer; forming a third drain electrode of the thin film transistor on a side of the oxide semiconductor layer away from the substrate, wherein the third drain electrode is electrically connected to the oxide semiconductor layer; A third gate of the thin film transistor is formed on a side of the second metal layer away from the substrate. The third gate is electrically connected to the second metal layer, and the third gate is electrically connected to the third metal layer through a via hole.

8. A thin film transistor, characterized in that: The thin film transistor is prepared by the method according to any one of claims 4 to 7.

9. A display panel, characterized in that: The display panel includes a plurality of thin film transistors as claimed in claim 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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