Display device

Abstract

The embodiment of the present application provides a display device, which comprises a gate drive circuit, a data drive circuit, a power supply circuit, a plurality of sub-pixels and corresponding sub-pixel drive circuits, in the sub-pixel drive circuit, a light-emitting duration control circuit determines light-emitting duration drive data based on light-emitting duration compensation data obtained by a first end of a first capacitor in a display period and a control power supply signal, and adjusts the level state of a first light-emitting control signal output by a second end of the first capacitor according to the change of the light-emitting duration drive data and the control power supply signal, so as to adjust the duration of the driving light-emitting drive circuit connected with the second end of the first capacitor to generate a driving signal, so as to regulate the light intensity generated by the sub-pixel, and the above process does not have the process that the power line transmitting a high level continuously transmits electric energy to the power line transmitting a low level, so that the energy consumption in the light-emitting duration regulation process is reduced, and thus the loss generated in the sub-pixel driving process is reduced.

Description

Technical Field

[0001] Embodiments of this application relate to the field of display technology, and more particularly to a display device. Background Technology

[0002] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0003] The pixel driving circuit of a micro LED can drive the micro LED to emit light through pulse width modulation (PWM) + pulse amplitude modulation (PAM). That is, the pixel driving circuit controls the conduction state of the PWM driving transistor according to the acquired PWM signal and the changing ramp signal, so as to regulate the time when the pixel driving circuit generates the driving signal, that is, the light emission time of the micro transistor in each frame display cycle; then, the current value in the driving signal is determined according to the PAM signal to determine the light intensity of the micro transistor during the light emission process, thereby determining the brightness of the micro LED in each frame display cycle.

[0004] However, in the pulse width modulation circuit within the pixel driving circuit, two transistors are connected to the two ends of the PWM driving transistor. When adjusting the light emission time, the PWM driving transistor and the two transistors will be turned on simultaneously. The power line transmitting the high level transmits electrical signals to the power line transmitting the low level through the two turned-on transistors and the PWM driving transistor, resulting in high energy consumption when adjusting the light emission duration using the on state of the PWM driving transistor. Summary of the Invention

[0005] This application provides a display device to solve the technical problem of high energy consumption when adjusting the light emission duration using the on-state of a PWM-driven transistor.

[0006] This application provides a display device, including:

[0007] Gate driving circuit, data driving circuit, power supply circuit, multiple sub-pixels and corresponding sub-pixel driving circuits;

[0008] The sub-pixel driving circuit includes:

[0009] The light emission duration control circuit is electrically connected to the gate driving circuit, the data driving circuit, and the power supply circuit. The light emission duration control circuit includes a first capacitor and is configured to determine light emission duration driving data based on a control power signal obtained from a first terminal of the first capacitor and light emission duration compensation data during the display cycle. The control power signal is a signal obtained during the data writing stage, and the light emission duration compensation signal is a signal obtained before the data writing stage.

[0010] The light emission duration control circuit is further configured to generate and output a first light emission control signal from the second terminal of the first capacitor based on the light emission duration driving data and the change in the control power supply signal.

[0011] The light-emitting driving circuit, which is electrically connected to the second terminal of the first capacitor and the gate driving circuit, is configured to adjust the duration of its generation of driving signals in the display cycle according to the first light-emitting control signal.

[0012] The sub-pixel is electrically connected to the light-emitting driving circuit and is configured to emit light according to the driving signal.

[0013] In the above technical solution, a display device is provided in which the sub-pixel driving circuit includes a light emission duration driving circuit and a light emission control circuit. A first capacitor is set in the light emission duration driving circuit. The first terminal of the first capacitor determines the light emission duration driving data according to the light emission duration compensation data and control power signal obtained sequentially in each display cycle. The level state of the second terminal of the first capacitor, i.e., the level state of the first light emission control signal, is adjusted according to the changes in the light emission duration driving data and control power signal, thereby regulating the duration of the driving signal generated by the light emission driving circuit to regulate the light intensity of the sub-pixel. The above process does not involve the continuous transmission of power energy from a high-level power line to a low-level power line, reducing the energy consumption generated during the light emission duration regulation process, thereby reducing the loss generated during the sub-pixel driving process.

[0014] In one feasible implementation, the display cycle sequentially includes a first stage, a data writing stage, and a display stage; the light emission duration control circuit further includes a data writing unit;

[0015] The light emission duration control circuit is configured to determine light emission duration driving data based on the control power supply signal obtained from the first capacitor and the light emission duration compensation data within the display cycle, including:

[0016] The first end of the data writing unit is electrically connected to the data driving circuit, its second end is electrically connected to the power supply circuit, and its output end is electrically connected to the first end of the first capacitor. It is configured to, in the first stage, connect the output end and the first end, and turn off the second end, and output the light emission duration compensation data obtained from the first end from the output end.

[0017] The data writing unit is further configured to output preset data obtained from the first terminal from the output terminal during the data writing phase.

[0018] The first capacitor is configured to determine the light emission duration driving data based on the difference between the light emission duration compensation data and the preset data during the data writing phase.

[0019] In one feasible implementation, the light emission duration control circuit is further configured to generate and output a first light emission control signal from the second terminal of the first capacitor based on the changes in the light emission duration driving data and the control power supply signal, including:

[0020] The data writing unit is configured such that during the display phase, the output terminal and the second terminal are connected, and the first terminal is turned off, and the control power signal obtained from the second terminal is output from the output terminal, wherein the initial level value of the control power signal during the display phase is the same as the level value of the preset data;

[0021] The first capacitor is also configured to, during the display phase, determine and output the first light-emitting control signal from its second terminal based on the light-emitting duration driving data, the amount of change in the control power signal, and its capacitance.

[0022] In the above technical solution, the light emission duration control circuit adjusts the first and second terminals of its data writing unit to alternately connect to the output terminal during each display cycle. This ensures that when the first and output terminals are connected, light emission duration compensation data and preset data are sequentially transmitted to the first terminal of the first capacitor electrically connected to the output terminal. The first capacitor then determines and stores the light emission duration driving data based on the obtained data difference. When the first and output terminals of the data writing unit are disconnected and the second and output terminals are connected, the initial level of the control power signal transmitted from the second terminal to the output terminal is the same as the level of the preset data, preventing terminal changes from affecting the light emission duration driving data stored in the first capacitor. According to the influence of the control power signal, during the display phase when the second and output terminals are connected, the level of the first terminal of the first capacitor is adjusted by adjusting the level of the control power signal based on the initial level of the control power signal. This, in turn, adjusts the level of the first light-emitting control signal output from the second terminal of the first capacitor, thereby controlling the light-emitting duration of the driving transistor in the light-emitting driving circuit. Compared to controlling the conduction of the driving transistor by regulating the on and off states of the PWM driving transistor that is electrically connected to the power line that transmits high and low levels, this method saves the energy loss generated during the conduction of the PWM driving transistor, thereby reducing the loss generated during the sub-pixel driving process.

[0023] The display device provided in this application embodiment includes a gate driving circuit, a data driving circuit, a power supply circuit, multiple sub-pixels, and corresponding sub-pixel driving circuits. The sub-pixel driving circuit includes a light emission duration control circuit and a light emission driving circuit. A first capacitor is set in the light emission duration control circuit. During the display cycle, the first capacitor determines the light emission duration driving data based on the light emission duration compensation data and the control power supply signal obtained from its first terminal. The level of the first light emission control signal output from the second terminal of the first capacitor is adjusted according to the changes in the light emission duration driving data and the control power supply signal. This adjusts the duration for which the driving signal is generated by the driving circuit electrically connected to the second terminal of the first capacitor, thereby controlling the light intensity generated by the sub-pixel. The above process does not involve the continuous transmission of power energy from a high-level power line to a low-level power line, reducing the energy consumption generated during the light emission duration control process, thereby reducing the losses generated during the sub-pixel driving process. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0025] Figure 1 This is a schematic diagram of the structure of a display provided according to an exemplary embodiment of this application;

[0026] Figure 2This is a schematic diagram of the structure of a display provided in this application according to another exemplary embodiment;

[0027] Figure 3 This is a circuit structure diagram of a conventional pixel driving circuit provided in accordance with an exemplary embodiment of this application;

[0028] Figure 4 This is a schematic diagram of the structure of a P-type pixel driving circuit provided in an exemplary embodiment of this application;

[0029] Figure 5 This is a timing diagram of the driving signals for a P-type pixel driving circuit provided in an exemplary embodiment of this application;

[0030] Figures 6A to 6E This is a diagram showing the operating state of a P-type pixel driving circuit provided in this application according to an exemplary embodiment;

[0031] Figure 7 This is a schematic diagram of the structure of an N-type pixel driving circuit provided in an exemplary embodiment of this application;

[0032] Figure 8 This is a timing diagram of the driving signals for an N-type pixel driving circuit provided in an exemplary embodiment of this application.

[0033] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0034] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0035] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment. It should be further understood that the terms "comprising" or "including" indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups.

[0036] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise expressly specified. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition occur only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0037] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0038] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0039] A schematic diagram of the display device is shown below. Figure 1 and Figure 2As shown, the system includes a control circuit 250, a data drive circuit 20, a gate drive circuit 30, a display panel 40, and a power supply circuit 280. The control circuit 250 and the data drive circuit 20 are electrically connected, as are the gate drive circuit 30 and the display panel 40.

[0040] The display panel has a power line 90, multiple gate lines 60, multiple data lines 50 and multiple pixel units 80. The multiple pixel units 80 are arranged in an array, and each pixel unit 80 is located in the area where the gate line 60 and the data line 50 intersect.

[0041] The gate driving circuit 30 is electrically connected to the gate line 60. The gate driving circuit 30 is configured to obtain clock signals and trigger signals from the control circuit 250, generate gate driving signals according to the clock signals and trigger signals, and transmit the gate driving signals to the corresponding pixel unit 80 through the gate line 60 to control the transistors in the pixel unit 80 to be turned on or off.

[0042] More specifically, the gate driving circuit 30 can be fabricated as a separate gate driver integrated circuit (GDIC). Alternatively, the gate driving circuit 30 can be integrated into the display panel; this integration is called gate-in-panel (GIP). In some cases, the GDIC can be electrically connected to the display panel 40 via a COG (Chip on Glass) process, or via a COF (Chipon Film) process. In the COF process, the component is electrically connected to the display panel 40 via a flexible printed circuit (FPC).

[0043] The data driving circuit 20 is a circuit that drives the data line 50. It is configured to acquire display data from the control circuit 250 and convert it into an analog data voltage (Vdata). This analog data voltage is transmitted through the data line 50 to the corresponding pixel unit 80, so that the sub-pixel 813 in the pixel unit 80 emits light according to the analog data voltage. The magnitude of the analog data voltage determines the luminous brightness of the sub-pixel 813.

[0044] The data driving circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, and output buffer, etc.

[0045] The power supply circuit 280 is a circuit that provides stable electrical signals and is configured to provide the corresponding power signals to the display panel 40, control circuit 250, data drive circuit 20 and gate drive circuit 30.

[0046] In one configuration, each pixel unit 80 includes three sub-pixel circuits 810, used to display red light, blue light, and green light respectively. In another configuration, each pixel unit 80 includes four sub-pixel circuits 810, used to display red light, blue light, green light, and white light respectively. No specific limitation is made here.

[0047] The emission color of each sub-pixel unit 810 is determined by the properties of its sub-pixel 813. The sub-pixel 813 can be any light-emitting device, including but not limited to OLED and micro LED.

[0048] A micro LED is a miniature light-emitting device manufactured using inorganic semiconductor layers. A micro LED typically includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, including vertical, horizontal, and flip-chip types, and is not particularly limited to a specific structure.

[0049] More specifically, a sub-pixel circuit 810 includes a sub-pixel driving circuit 814 and a sub-pixel 813. The sub-pixel driving circuit 814 is electrically connected to the sub-pixel 813 and is configured to drive the sub-pixel 813 to emit light. The signals required by the sub-pixel driving circuit 814 include a driving signal, a scan signal, and an emission control signal (EM control signal).

[0050] The driving signal can be generated by the control circuit 250 or obtained from an external source. This includes, but is not limited to, a start pulse signal, a clock signal, and an enable signal. The light emission control signal can be a global signal provided by the control circuit 250 or a signal generated by the gate driving circuit 30; no specific limitation is made here. The scanning signal is a successive displacement signal generated by the gate driving circuit 30.

[0051] If the EM control signal is a global signal generated by the control circuit 250, the gate drive circuit 30 obtains the EM control signal from the control circuit 250 and transmits the EM control signal to the corresponding pixel drive circuit 814 through the gate line 60.

[0052] If both the EM control signal and the scan signal are generated by the gate drive circuit 30, the gate drive circuit 30 includes a scan signal generation circuit 301 and an EM control signal generation circuit 302. The scan signal is output by the scan signal generation circuit 301, and the EM control signal is output by the EM control signal generation circuit 302.

[0053] Figure 3 This is a circuit structure diagram of a conventional pixel driving circuit provided in an exemplary embodiment of the present application, including a PWM driving circuit 803 and a PAM driving circuit 804.

[0054] The PWM drive circuit 803 is configured to acquire the light emission duration drive data PWMD and the control power signal SWEEP, and adjust the level of the first light emission control signal it generates according to the light emission duration drive data PWMD and the control power signal SWEEP. The level of the light emission control signal is either the first level or the second level.

[0055] The PAM driving circuit 804 and the PWM driving circuit 803 are electrically connected to the sub-pixel LED and are configured to acquire a first light-emitting control signal and current-brightness driving data PAMD, and generate a driving signal based on the first light-emitting control signal and the current-brightness driving data PAMD to drive the sub-pixel LED to emit light. The first light-emitting control signal is used to regulate the light-emitting duration of the sub-pixel LED, and the current-brightness driving data PAMD is used to regulate the magnitude of the current passing through the sub-pixel LED.

[0056] The PWM drive circuit 803 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. All of these transistors are N-type transistors.

[0057] The first terminal of the fourth transistor T4 is electrically connected to the power supply line 90, the second terminal is electrically connected to the first terminal of the sixth transistor T6, and the control terminal is electrically connected to the gate line 60. It is configured to obtain a low-level power supply signal VGL from its first terminal and a second light emission control signal EM1 from its control terminal. When the second light emission control signal EM1 is high, it is turned on and transmits the power supply signal VGL obtained from its first terminal to the first terminal of the sixth transistor T6.

[0058] The first terminal of the fifth transistor T5 and the second terminal of the sixth transistor T6 are electrically connected. The second terminal is electrically connected to the power supply line 90, and the control terminal is electrically connected to the gate line 60. It is configured to obtain a high-level reference power supply signal REF from its second terminal and a second light emission control signal EM1 from its control terminal. When the second light emission control signal EM1 is high, it is turned on and transmits the reference power supply signal REF obtained from its first terminal to the second terminal.

[0059] The sixth transistor T6 is configured to turn on when the electrical signal obtained at its control terminal is greater than a preset threshold, and to turn off when the electrical signal obtained at its control terminal is less than the preset threshold.

[0060] When the sixth transistor T6 is turned on, since the size of the sixth transistor T6 is larger than that of the fifth transistor T5, the potential value of its second terminal is determined by the electrical signal obtained from its first terminal, which is a low level; when the sixth transistor T6 is turned off, the potential value of the second terminal of the sixth transistor T6 is determined by the fifth transistor T5 which is electrically connected to that point, which is a high level.

[0061] The PAM driving circuit 804 adjusts the time period for generating the driving signal according to the level state provided by the second terminal of the sixth transistor T6. That is, when the second terminal of the sixth transistor T6 is at a high level, the driving signal is stopped and the sub-pixel LED does not emit light; when the first terminal of the sixth transistor T6 is at a low level, the driving signal is generated and the sub-pixel LED emits light.

[0062] When the sixth transistor T6 is turned on, the fifth transistor T5 and the fourth transistor T4 are also turned on. The power line providing the reference power signal REF transmits the electrical signal to the power line providing the power signal VGL through the turned-on fifth transistor T5, sixth transistor T6 and fourth transistor T4. A charging phenomenon occurs in the sixth transistor T6, resulting in high power consumption.

[0063] To address the aforementioned problems, this application provides a display device to solve the technical problem of high energy consumption when adjusting the light emission duration using the conduction state of a PWM driving transistor. The technical concept of this application is: to provide a sub-pixel driving circuit, including a light emission duration driving circuit and a light emission control circuit. The light emission duration control circuit determines light emission duration driving data based on light emission duration compensation data obtained from the first terminal of a first capacitor and a control power signal. It then adjusts the level of the first light emission control signal output from the second terminal of the first capacitor according to changes in the light emission duration driving data and the control power signal, thereby controlling the duration of the driving signal generated by the driving transistor and thus controlling the light intensity of the sub-pixel. This process eliminates the continuous transmission of power from a high-level power line to a low-level power line, reducing energy consumption during light emission duration adjustment and thus reducing losses during sub-pixel driving.

[0064] The pixel driving circuit proposed in this application will be explained in detail below. Figure 4 This is a schematic diagram of a pixel driving circuit provided according to an exemplary embodiment of this application. All transistors in this pixel driving circuit are P-type transistors.

[0065] like Figure 4 As shown, the pixel driving circuit provided in this application includes a light emission duration control circuit 901 and a light emission driving circuit 902.

[0066] The light emission duration control circuit 901 is electrically connected to the power supply line 90 and the data line 50. The light emission duration control circuit 901 includes a first capacitor C1 and is configured to determine and store light emission duration drive data based on the control power signal Sweep and the light emission duration compensation data PWMD obtained from the first terminal of the first capacitor C1 during the display cycle. The control power signal Sweep is obtained during the data writing phase, and the light emission duration compensation signal PWMD is obtained before the data writing phase.

[0067] The light emission duration control circuit 901 is also configured to generate and output a first light emission control signal from the second terminal (point A) of the first capacitor C1 based on the light emission duration drive data and the change in the control power supply signal Sweep.

[0068] The light-emitting driving circuit 902 is electrically connected to the second end of the first capacitor C1 and is configured to adjust the duration of its generation of driving signals in the display cycle according to the first light-emitting control signal.

[0069] The sub-pixel LED and the light-emitting driving circuit 902 are electrically connected and configured to emit light according to the driving signal.

[0070] In the above technical solution, the light emission duration control circuit including the first capacitor determines the light emission duration driving data based on the light emission duration compensation data and control power signal at the first end of the first capacitor, and adjusts the level of the first light emission control signal output from the second end of the first capacitor according to the changes in the light emission duration driving data and control power signal, so as to regulate the duration of the driving signal generated by the light emission driving circuit, thereby regulating the light intensity of the sub-pixel. The above process does not involve the continuous transmission of power energy from a high-level power line to a low-level power line, which reduces the energy consumption in the light emission duration regulation process, thereby reducing the loss generated in the sub-pixel driving process.

[0071] The light emission duration control circuit 901 includes a data writing unit 903 and a first capacitor C1. The display cycle sequentially includes a first stage, the data writing stage, and the display stage.

[0072] The first end of the data writing unit 903 is electrically connected to the data line 50, its second end is electrically connected to the power line 90, and its output end is electrically connected to the first end of the first capacitor C1. It is configured to, in the first stage, connect its output end and its first end, and disconnect its second end, obtain the light emission duration compensation data PWMD from its first end, and output the light emission duration compensation data PWMD from its output end.

[0073] The data writing unit 903 is also configured to obtain preset data from its first end during the data writing phase and output the preset data from its output end.

[0074] The first capacitor C1 is configured to determine the light emission duration driving data based on the difference between the light emission duration compensation data and the preset data during the data writing phase.

[0075] More specifically, the potential value of the second terminal of the first capacitor C1 changes with the change of its first terminal. After the data obtained at its first terminal is adjusted from the light emission duration compensation data to the preset data, the level state of its second terminal is adjusted according to the difference in level determined at its first terminal, its capacitance, and the capacitance in the circuit structure electrically connected to its second terminal, and the level value of the second terminal is determined as the level value corresponding to the light emission duration driving data.

[0076] The data writing unit 903 is also configured to, during the display phase, connect its output terminal and the second terminal, and disconnect the first terminal, obtain the control power signal Sweep from its second terminal, and output the control power signal Sweep from the output terminal.

[0077] The initial level of the control power signal during the display phase is the same as the level of the preset data to prevent the potential value at the output of the data writing unit 903 from changing when the terminal is turned on.

[0078] The first capacitor C1 is also configured to output a first light-emitting control signal from its second terminal during the display phase, based on the light-emitting duration driving data determined during the data writing phase and the changing control power signal Sweep during the light-emitting phase. Specifically, since the first terminal of the first capacitor C1 only receives the control power signal Sweep during the display phase, the level at its second terminal will increase as the control power signal Sweep increases, and decrease as the control power signal Sweep decreases, based on the level value corresponding to the already determined light-emitting duration driving data.

[0079] When the second terminal of the first capacitor C1 is electrically connected to other capacitors, when the potential value of the control power signal SWEEP obtained at its first terminal changes, the first capacitor C1 will couple with other capacitors to adjust the potential value at point A.

[0080] The data writing unit 903 includes a fifth transistor T5 and a seventh transistor T7.

[0081] The first terminal of the fifth transistor T5 serves as the first terminal of the data writing unit 903, and its second terminal serves as the output terminal of the data writing unit 903. Its control terminal is electrically connected to the gate line 60 and is configured to receive the third scan signal S3 from its control terminal, with the third scan signal S3 controlling its conduction state.

[0082] The fifth transistor T5 is turned on when the third scan signal S3 is low, and outputs the light emission duration compensation data PWMD or preset data obtained from the first terminal from its second terminal; it is turned off when the third scan signal S3 is high, stopping the transmission of electrical signals.

[0083] The first terminal of the seventh transistor T7 serves as the second terminal of the data writing unit 903. Its second terminal is electrically connected to the second terminal of the fifth transistor T5, and its control terminal is electrically connected to the gate line 60. It is configured to obtain the third light emission control signal EM2 from its control terminal and control its conduction state by the third light emission control signal EM2.

[0084] The seventh transistor T7 is turned on when the third light-emitting control signal EM2 is low, and outputs the power control signal Sweep from its second terminal; it is turned off when the third light-emitting control signal EM2 is high, and stops the output of the power control signal Sweep.

[0085] In the above technical solution, the light emission duration control circuit adjusts the first and second terminals of its data writing unit to alternately connect to the output terminal during each display cycle. This ensures that when the first and output terminals are connected, light emission duration compensation data and preset data are sequentially transmitted to the first terminal of the first capacitor electrically connected to the output terminal. The first capacitor then determines and stores the light emission duration driving data based on the obtained data difference. When the first and output terminals of the data writing unit are disconnected and the second and output terminals are connected, the initial level of the control power signal transmitted from the second terminal to the output terminal is the same as the level of the preset data, preventing terminal changes from affecting the light emission duration data stored in the first capacitor. Due to the influence of long driving data, during the display phase when the second and output terminals are connected, based on the initial level of the control power signal, the level of the first terminal of the first capacitor is adjusted by adjusting the level of the control power signal, thereby adjusting the level of the first light-emitting control signal output from the second terminal of the first capacitor. This achieves the regulation of the light-emitting duration of the driving transistor. Compared with controlling the conduction and cutoff states of the PWM driving transistor electrically connected to the power line transmitting high and low levels to control the conduction of the driving transistor, this saves the energy loss generated during the conduction process of the PWM driving transistor, thereby reducing the loss generated during the sub-pixel driving process.

[0086] The light-emitting driving circuit 902 includes a light-emitting control circuit 906, a light-emitting threshold compensation circuit 905, and a reset circuit 904.

[0087] The first terminal of the reset circuit 904 is electrically connected to the power line 90, and its second terminal is electrically connected to the second terminal of the light emission threshold compensation circuit 905 and the first capacitor C1 at point A. It is configured to obtain a reference power signal REF from the power line 90 before the compensation stage, and transmit the reference power signal REF to the second terminal of the light emission threshold compensation circuit 905 and the first capacitor C1 when it is turned on.

[0088] The light emission threshold compensation circuit 905 and the first capacitor C1 are configured to perform a reset operation according to the reference power supply signal REF, so that the potential value of the second terminal of the first capacitor C1 and the potential value of the device terminal electrically connected to point A in the light emission threshold compensation circuit 905 are adjusted to the same low level as the reference power supply signal REF.

[0089] The control terminal of the light emission threshold compensation circuit 905 is electrically connected to the second terminal of the first capacitor C1 through point A, its first terminal is electrically connected to the third terminal of the light emission control circuit 906 through point C, its second terminal is electrically connected to the fourth terminal of the light emission control circuit 906 through point E, and its power supply terminal is electrically connected to the power supply line 90 through point B.

[0090] The light emission threshold compensation circuit 905 is configured to obtain a first power supply signal VDD from its power supply terminal and its first terminal respectively during the compensation phase, store the threshold voltage of the driving transistor T2 according to the first power supply signal VDD, and generate and transmit a driving signal to the light emission control circuit 906 according to the stored threshold voltage and the first light emission control signal during the display phase.

[0091] The first end of the light-emitting control circuit 906 is electrically connected to the power line 90 through point B, the second end is electrically connected to the sub-pixel LED through point F, the third end is electrically connected to the light-emitting threshold compensation circuit 905 through point C, and the fourth end is electrically connected to the light-emitting threshold compensation circuit 905 through point E.

[0092] The light-emitting control circuit 906 is configured to receive a first power signal VDD from the power line 90 at its first terminal, output the first power signal to the light-emitting threshold compensation circuit 905 from its third terminal during the compensation phase and display phase of the display cycle, and transmit the driving signal generated by the light-emitting threshold compensation circuit 905 obtained from its fourth terminal to the sub-pixel LED from its second terminal during the display phase to drive the sub-pixel LED to emit light.

[0093] The reset circuit 904 includes a first transistor T1.

[0094] The first terminal of the first transistor T1 is electrically connected to the power supply line 90, its control terminal is electrically connected to the gate line 60, and its second terminal is electrically connected to the second terminal of the first capacitor C1, the second terminal of the second capacitor C2, and the control terminal of the driving transistor T2. It is configured to obtain the first scan signal S1 from its control terminal, obtain the reference power supply signal REF from its first terminal, and control its conduction state by the first scan signal S1.

[0095] The first transistor T1 is turned on when the first scan signal S1 is low, and outputs a reference power supply signal REF from its second terminal for resetting the device electrically connected to the second terminal; it is turned off when the first scan signal S1 is high, and stops the output of the reference power supply signal REF.

[0096] The light-emitting control circuit 906 includes a fourth transistor T4 and a sixth transistor T6.

[0097] The first terminal of the fourth transistor T4 serves as the first terminal of the light-emitting control circuit 906, and its second terminal serves as the third terminal of the light-emitting control circuit 906. Its control terminal is electrically connected to the gate line 60 and is configured to obtain a first power supply signal VDD from its first terminal and a second light-emitting control signal EM1 from its control terminal, and control its conduction state by the second light-emitting control signal EM1.

[0098] The fourth transistor T4 is turned on when the second light-emitting control signal EM1 is low, and outputs the first power supply signal VDD from its second terminal; it is turned off when the second light-emitting control signal EM1 is high, and stops the transmission of the first power supply signal VDD.

[0099] The first terminal of the sixth transistor T6 serves as the fourth terminal of the light-emitting control circuit 906, and its second terminal serves as the second terminal of the light-emitting control circuit 906. Its control terminal is electrically connected to the gate line 60 and is configured to obtain the third light-emitting control signal EM2 from its control terminal, and its conduction state is controlled by the third light-emitting control signal EM2.

[0100] The sixth transistor T6 is turned on when the third light-emitting control signal EM2 is low. When it receives a driving signal at its first terminal, it transmits the driving signal from its second terminal to the positive terminal of the sub-pixel LED so that the sub-pixel LED emits light according to the driving signal.

[0101] The light emission threshold compensation circuit 905 includes: a second capacitor C2, a driving transistor T2, and a third transistor T3.

[0102] The first terminal of the third transistor T3 serves as the control terminal of the light emission threshold compensation circuit 905 and is electrically connected to the control terminal of the driving transistor T2. Its control terminal is electrically connected to the gate line 60. Its second terminal serves as the second terminal of the light emission threshold compensation circuit 905 and is electrically connected to the second terminal of the driving transistor T2. It is configured to obtain the second scan signal S2 from its control terminal and control its conduction state by the second scan signal.

[0103] The third transistor T3 is turned on when the second scan signal S2 is low, shorting the control terminal and the second terminal of the driving transistor T2; it is turned off when the second scan signal S2 is high, disconnecting the control terminal and the second terminal of the driving transistor T2.

[0104] The first terminal of the driving transistor T2 serves as the first terminal of the light emission threshold compensation circuit 905. It is configured to short-circuit its control terminal and its second terminal. When its first terminal receives the first power supply signal VDD transmitted by the fourth transistor T4, it outputs the first power supply signal VDD compensated for by its threshold voltage from its control terminal, with a voltage value of V. A =VVDD +V th , where V A This represents the potential value at point A, which is the potential value at the control terminal of the driving transistor T2, V. VDD This represents the potential value of the first power supply signal VDD, V th This represents the threshold voltage for driving transistor T2.

[0105] The driving transistor T2 is also configured such that when its control terminal and its second terminal are disconnected, the electrical signal obtained from its control terminal controls its conduction state.

[0106] The driving transistor T2 turns on when the voltage value of the electrical signal obtained at its control terminal is within the preset voltage range, generating a driving signal; it turns off when the voltage value of the electrical signal obtained at its control terminal is not within the preset voltage range, stopping the generation of the driving signal.

[0107] The first terminal of the second capacitor C2 is electrically connected to the power line 90, and its second terminal is electrically connected to the control terminal of the driving transistor T2. It is configured to obtain a stable power signal (e.g., the first power signal VDD) from its first terminal and adjust its stored data according to the electrical signal obtained from its second terminal.

[0108] The second capacitor C2 is configured to hold a reference power supply signal REF for reset at its second terminal when the first transistor T1 is turned on, so that the control terminal of the driving transistor T2 can continuously obtain a low-level reference power supply signal REF and remain in the on state.

[0109] The second capacitor C2 is also configured to, after receiving the first power supply signal after threshold voltage compensation generated by the control terminal of the driving transistor T2 at its second terminal, determine the voltage difference between its two terminals as the threshold voltage V of the driving transistor T2 based on the first power supply signal VDD received at its first terminal. th And store the threshold voltage.

[0110] Since the second terminal of the second capacitor C2 is also electrically connected to the second terminal of the first capacitor C1, after the driving transistor T2 generates the first power supply signal for threshold voltage compensation, when the first terminal of the first capacitor C1 receives the electrical signal transmitted by the fifth transistor T5 and adjusts it from the light emission duration compensation data to the preset data, the first capacitor C1 and the second capacitor C2 couple and adjust their stored electrical energy, changing the potential value at point A: Among them, ▲V PWMD c1 represents the potential difference between the preset data and the light emission duration compensation data, c2 represents the capacitance of the first capacitor C1, and c2 represents the capacitance of the second capacitor C2.

[0111] After the electrical signal obtained at the first terminal of the first capacitor C1 is adjusted to the control power signal Sweep transmitted by the seventh transistor T7, the first capacitor C1 and the second capacitor C2 are coupled to adjust the potential value at point A according to the change in the control power signal Sweep: Among them, ▲V Sweep This indicates the change in the control power signal Sweep.

[0112] In the above technical solution, the pixel driving circuit not only controls the conduction time of the driving transistor by changing the potential value of the first terminal of the first capacitor during the control of the driving transistor's conduction process, replacing the function of the transistor that controls the potential value change, thus saving the power consumption of the transistor used for control, but also simplifies the circuit structure and reduces the use of transistors compared to the traditional pixel driving circuit, saving the area occupied by the pixel circuit in the display panel, and effectively improving the pixel density and panel resolution.

[0113] Figure 4 The circuit structure shown is composed of Figure 5 The driving signal timing diagram shown is used for driving.

[0114] The following is combined Figures 6A to 6E The process diagram shown is for Figure 4 The circuit structure shown is explained in terms of its operation within a display cycle. A display cycle T includes the first stage T1, the data writing stage t3, and the display stage t4. The first stage T1 includes the reset stage t1 and the compensation stage t2.

[0115] During the reset phase t1 in the drive signal timing diagram, the first scan signal S1 and the third scan signal S3 are at low level, the second scan signal S2, the second light emission control signal EM1, and the third light emission control signal EM2 are at high level, and the reference power supply signal REF is at low level. The control power supply signal SWEEP is adjusted from low level to high level, and the drive data is the preset data.

[0116] Since the first scan signal S1 is low, the first transistor T1 is turned on, and the reference power supply signal REF obtained from its first terminal is transmitted to point A.

[0117] Since the second light-emitting control signal EM1 is at a high level, the fourth transistor T4 is turned off and cannot transmit the first power supply signal VDD to the driving transistor T2.

[0118] Since the reference power supply signal REF is low, the control terminal of the driving transistor T2 receives a low signal, and the driving transistor T2 is turned on; since the first terminal of the driving transistor T2 does not receive the first power supply signal VDD, the driving transistor T2 does not generate a driving signal.

[0119] In addition, the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 follow the signal obtained at point A and adjust their potentials to initialize their second terminals. The adjusted potential value is the same as the potential value of the reference power supply signal REF.

[0120] Since the third scanning signal S3 is at a low level, the fifth transistor T5 is turned on, transmitting the preset data obtained at its first terminal to the first terminal of the first capacitor C1, so that the first capacitor C1 adjusts the potential of its first terminal to the same potential as the preset data, thereby achieving initialization.

[0121] The control power signal SWEEP is adjusted from low level to high level to prepare for the level change according to the ramp signal during the display stage t4, thus avoiding affecting the accuracy of the data stored in the first capacitor when adjusting the level during the display stage t4.

[0122] Since the third light-emitting control signal EM2 is at a high level, the seventh transistor T7 is turned off. The control power signal SWEEP obtained at its first terminal will not be transmitted to the second terminal, and therefore will not affect the potential value of the first terminal of the first capacitor C1 during the reset phase t1.

[0123] During the reset phase t1, the operating state of the sub-pixel driving circuit is as follows: Figure 6A As shown, the first transistor T1, the fifth transistor T5, and the driving transistor T2, which are marked with arrows, are turned on, while the other transistors are turned off.

[0124] During the compensation phase t2 in the driving signal timing diagram, the second scan signal S2, the third scan signal S3, and the second light emission control signal EM1 are at low levels, while the first scan signal S1, the third light emission control signal EM2, and the control power supply signal SWEEP are at high levels.

[0125] Since the first scan signal S1 is high, the first transistor T1 is turned off, and the transmission of the reference power supply signal REF to each capacitor stops.

[0126] Since the second light-emitting control signal EM1 is at a low level, the fourth transistor T4 is turned on, and the first power supply signal VDD obtained from its first terminal is transmitted to the first terminal of the driving transistor T2.

[0127] Since the second scan signal S2 is low, the third transistor T3 is turned on, shorting the control terminal and the second terminal of the driving transistor T2.

[0128] Since the control terminal and the second terminal of the driving transistor T2 are shorted, and its first terminal receives the first power supply signal VDD, the potential value obtained from its control terminal is V. DD +V th Then the potential value of the second terminal of each capacitor is adjusted to V.DD +V th .

[0129] The second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 store the threshold-compensated first power supply signal VDD.

[0130] Then, during the time period corresponding to compensation phase t2, the operating state of the sub-pixel driving circuit is as follows: Figure 6B As shown, the fifth transistor T5, the fourth transistor T4, the driving transistor T2, and the third transistor T3, which are marked with arrows, are turned on, while the other transistors are turned off.

[0131] During the time period corresponding to the data writing stage t3 in the driving signal timing diagram, the third scan signal S3 is at a low level, while the first scan signal S1, the second scan signal S2, the second light emission control signal EM1, the third light emission control signal EM2, and the control power signal SWEEP are at a high level.

[0132] Since the second light-emitting control signal EM1 is at a high level, the fourth transistor T4 is turned off, stopping the transmission of the first power supply signal VDD obtained from its first terminal to the first terminal of the driving transistor T2.

[0133] Since the second scan signal S2 is high, the third transistor T3 is turned off, and the control terminal and the second terminal of the driving transistor T2 are disconnected.

[0134] Since the electrical signal obtained at the control terminal of the driving transistor T2 is the electrical signal (V) stored in the capacitor. DD +V th If the signal is high, then the driving transistor T2 will be turned off.

[0135] Since the third scan signal S3 is low, the fifth transistor T5 is turned on, transmitting the data signal obtained from its first terminal to the first terminal of the third capacitor C3.

[0136] Then, during the time period corresponding to data writing phase t3, the operating state of the sub-pixel driving circuit is as follows: Figure 6C As shown, the fifth transistor T5, marked with an arrow, is turned on, while the other transistors are turned off.

[0137] The data writing phase t3 can be further divided into: the first data writing sub-phase and the second data writing sub-phase.

[0138] During the first data writing sub-stage, since the data electrical signal obtained by the first terminal of the fifth transistor T5 is still the electrical signal corresponding to the light emission duration compensation data, the level value of the first terminal of the first capacitor C1 remains unchanged.

[0139] During the second data writing sub-stage, the data electrical signal obtained at the first terminal of the fifth transistor T5 is adjusted to the electrical signal corresponding to the preset data. The second terminal of the first capacitor C1 determines the light emission duration driving data based on the change in its first terminal potential value, its capacitance, and the capacitance of the second capacitor C2, and adjusts the potential value of its second terminal accordingly.

[0140] It is worth noting that at the end of the second data writing sub-stage, before the fifth transistor T5 is turned off, the first terminal of the first capacitor C1 still remains in the state of receiving preset data. After the fifth transistor T5 is turned off, the transmission of the original light emission duration driving data is stopped to ensure the accuracy of the target light emission duration driving data obtained by coupling the second terminals of each capacitor.

[0141] After entering the display stage, data line 50 continues to transmit preset data for a period of time before switching back to transmitting light emission duration compensation data. The duration for which data line 50 transmits preset data during the display stage is the same as the duration for transmitting light emission duration compensation data during the data writing stage. This ensures that the clock signal used by data line 50 when transmitting drive data is the same as the clock signal used by gate line 50 when transmitting scan signals, thus maintaining a simple structure for the drive circuit.

[0142] During the time period corresponding to stage t4 shown in the driving signal timing diagram, the second light emission control signal EM1 and the third light emission control signal EM2 are at low level, the first scan signal S1, the second scan signal S2 and the third scan signal S3 are at high level, and the control power signal SWEEP is a ramp signal that is adjusted from high level to low level.

[0143] Since the second light-emitting control signal EM1 is at a low level, the fourth transistor T4 is turned on, and the first power supply signal VDD obtained from its first terminal is transmitted to the first terminal of the driving transistor T2.

[0144] Since the second scanning signal S2 is high, the third transistor T3 is turned off, the control terminal and the second terminal of the driving transistor T2 are disconnected, and the driving transistor T2 adjusts its conduction state according to the level of the electrical signal obtained from its control terminal.

[0145] Since the third scan signal S3 is high, the fifth transistor T5 is turned off, stopping the fifth transistor T5 from transmitting data to the first terminal of the first capacitor C1.

[0146] Since the third light-emitting control signal EM2 is at a low level, the seventh transistor T7 is turned on, and the control power signal Sweep obtained from its first terminal is transmitted to the first terminal of the first capacitor C1.

[0147] Since the level of the control power signal Sweep is the same as the level of the preset data transmitted by the fifth transistor T5 when the seventh transistor T7 is turned on, the potential value of the second terminal of the first capacitor C1 will not be affected during the transistor switching process.

[0148] Since the control power signal SWEEP is a ramp signal that adjusts from a high level to a low level, the potential value of the first light-emitting control signal generated at the second terminal of the first capacitor C1 decreases as the potential value at the first terminal decreases.

[0149] The potential value at the second terminal of the first capacitor C1 is determined based on the coupling effect of each capacitor and the potential change at its first terminal: Where, ΔV A ΔV represents the change in potential at the second terminal of the first capacitor C1. SWEEP c1 represents the potential change of the control power signal SWEEP obtained at the first terminal of the first capacitor C1, and c2 represents the capacitance of the first capacitor C1.

[0150] Based on the change in the potential value at the second terminal of the first capacitor C1 and the conduction voltage range of the driving transistor T2, the display stage T4 is divided into a non-light-emitting stage and a light-emitting stage.

[0151] During the non-light-emitting stage, the potential value at the second end of the first capacitor C1 continues to decrease, but it is still not within the preset voltage range corresponding to the conduction of the driving transistor T2, so the driving transistor T2 remains in the off state.

[0152] In this embodiment, the fact that the potential value of the second terminal of the first capacitor C1 is not within the preset voltage range corresponding to the conduction of the driving transistor T2 indicates that the potential value of the second terminal of the first capacitor C1 is greater than the first conduction preset voltage threshold.

[0153] During the light-emitting phase, the potential value at the second terminal of the first capacitor C1 continuously decreases. When it falls within the driving voltage range corresponding to the conduction of the driving transistor T2, the driving transistor T2 conducts. Based on the first power supply signal VDD obtained from its first terminal, the potential value obtained from its control terminal, and its threshold voltage, a driving signal is generated. Right now Where k is the current transformation coefficient associated with the driving transistor T2.

[0154] In this embodiment, the potential value of the second terminal of the first capacitor C1 being within the preset voltage range corresponding to the conduction of the driving transistor T2 indicates that the potential value of the second terminal of the first capacitor C1 is less than or equal to the first conduction preset voltage threshold.

[0155] Since the third light-emitting control signal EM2 is at a low level, the sixth transistor T6 is turned on.

[0156] During the non-light-emitting stage, the first terminal of the sixth transistor T6 does not receive the driving signal transmitted by the driving transistor T2, therefore the driving signal cannot be transmitted to the sub-pixel LED, and the sub-pixel LED does not emit light. Correspondingly, the operating state of the sub-pixel driving circuit is as follows: Figure 6D As shown, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6, which are marked with arrows, are turned on, while the other transistors are turned off.

[0157] During the light-emitting phase, the sixth transistor T6 transmits the driving signal obtained from its first terminal to the positive terminal of the sub-pixel LED, causing the sub-pixel LED to emit light. Correspondingly, the operating state of the sub-pixel driving circuit is as follows: Figure 6E As shown, the seventh transistor T7, the fourth transistor T4, the sixth transistor T6, and the driving transistor T2, which are marked with arrows, are turned on, while the other transistors are turned off.

[0158] Figure 7 This is a schematic diagram of an N-type pixel driving circuit provided according to an exemplary embodiment of this application, in which each transistor is an N-type transistor. The following is a comparison with... Figure 4 The circuit structure shown is for Figure 7 A brief explanation of the circuit structure shown is provided.

[0159] Compared to Figure 4 The circuit structures shown differ in that:

[0160] Each transistor turns on when it receives a high level and turns off when it receives a low level.

[0161] The reference power signal REF obtained from the first terminal of the first transistor T1 from the power line 90 is at a high level. The first power signal VSS obtained from the first terminal of the fourth transistor T4 and the first terminal of the second capacitor C2 from the power line 90 is at a low level. The second terminal of the sixth transistor T6 is electrically connected to the negative terminal of the sub-pixel LED. The sub-pixel LED emits light when it receives the second power signal VDD at its positive terminal and the driving signal transmitted by the sixth transistor T6 at its negative terminal.

[0162] Other circuit connection relationships and Figure 4 The circuit structure shown is the same, so it will not be described again here.

[0163] Figure 7 The circuit structure shown is composed of Figure 8 The driving signal timing diagram shown is used for driving.

[0164] During the reset phase t1 in the drive signal timing diagram, the first scan signal S1 and the third scan signal S3 are at high level, the second scan signal S2, the second light emission control signal EM1, and the third light emission control signal EM2 are at low level, and the reference power supply signal REF is at high level. The control power supply signal SWEEP is adjusted from high level to low level.

[0165] The first transistor T1 is turned on according to the first scan signal S1, and transmits the reference power supply signal REF obtained by its first terminal to the second terminal of each capacitor and the control terminal of the driving transistor T2, so as to reset the second terminal of each capacitor and control the driving transistor T2 to turn on.

[0166] The fifth transistor T5 is turned on according to the third scan signal S3, and transmits the light emission duration compensation data obtained by its first terminal to the first terminal of the first capacitor C1, thereby resetting the first terminal of the first capacitor C1.

[0167] During the compensation phase t2 in the driving signal timing diagram, the second scan signal S2, the third scan signal S3, and the second light emission control signal EM1 are at high level, while the first scan signal S1, the third light emission control signal EM2, and the control power supply signal SWEEP are at low level.

[0168] The fourth transistor T4 is turned on according to the second light-emitting control signal EM1, and transmits the first power signal VSS obtained at its first terminal to the first terminal of the driving transistor T2.

[0169] The third transistor T3 is turned on according to the second scan signal S2, shorting the second terminal and the control terminal of the driving transistor T2, so that the driving transistor T2 determines the threshold voltage compensated first power signal VSS+Vth from its control terminal according to the first power signal VSS obtained from its first terminal, and stores the compensated first power signal in the second terminal of each capacitor, where Vth is the threshold voltage of the driving transistor T2.

[0170] During the time period corresponding to the data writing stage t3 in the driving signal timing diagram, the third scan signal S3 is at a high level, while the first scan signal S1, the second scan signal S2, the second light emission control signal EM1, the third light emission control signal EM2, and the control power signal SWEEP are at a low level.

[0171] The fifth transistor T5 is turned on according to the third scan signal S3, transmitting the preset data obtained at its first terminal to the first terminal of the first capacitor C1. The first capacitor C1, together with other capacitors, couples the change in the driving data obtained at its first terminal, storing the light emission duration driving data at the second terminal of each capacitor, and adjusting the potential value at point A according to the light emission duration driving data.

[0172] Since the control terminal of the driving transistor T2 is electrically connected to the second terminal of each capacitor, the driving data is turned off according to the target emission duration determined above.

[0173] During the time period corresponding to stage t4 shown in the driving signal timing diagram, the second light emission control signal EM1 and the third light emission control signal EM2 are at high level, the first scan signal S1, the second scan signal S2 and the third scan signal S3 are at low level, and the control power signal SWEEP is a ramp signal that is adjusted from low level to high level.

[0174] The fifth transistor T5 is turned off according to the third scan signal S3, stopping the transmission of drive data.

[0175] The seventh transistor T7 is turned on according to the third light-emitting control signal EM2, and transmits the control power signal Sweep obtained at its first terminal to the first terminal of the first capacitor C1.

[0176] The second terminal of the first capacitor C1 adjusts the potential value of its output first light-emitting control signal according to the change of the control power signal SWEEP obtained from its first terminal.

[0177] The fourth transistor T4 is turned on according to the second light-emitting control signal EM1, and transmits the first power signal VSS obtained at its first terminal to the first terminal of the driving transistor T2.

[0178] When the potential value of the first light-emitting control signal is less than the second preset conduction voltage threshold that turns on the driving transistor T2, the driving transistor T2 does not conduct and does not generate a driving signal.

[0179] As the control power signal SWEEP increases, the potential value of the first light-emitting control signal increases. When its potential value is greater than or equal to the second preset conduction voltage threshold that turns on the driving transistor T2, the driving transistor T2 turns on. Based on the first power signal VSS obtained from its first terminal and its threshold voltage, a driving signal is generated. Right now Where k is the current transformation coefficient associated with the driving transistor T2.

[0180] The sixth transistor T6 is turned on according to the third light-emitting control signal EM2. When the driving transistor T2 generates the driving signal, it transmits the driving signal obtained from its first terminal to the negative terminal of the sub-pixel LED.

[0181] The sub-pixel LEDs emit light according to the driving signal.

[0182] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0183] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display device, comprising: Gate driving circuit, data driving circuit, power supply circuit, multiple sub-pixels and corresponding sub-pixel driving circuits; The sub-pixel driving circuit is characterized by comprising: The light emission duration control circuit is electrically connected to the gate driving circuit, the data driving circuit, and the power supply circuit. The light emission duration control circuit includes a first capacitor and is configured to determine light emission duration driving data based on a control power signal obtained from a first terminal of the first capacitor and light emission duration compensation data during the display cycle. The control power signal is a signal obtained during the data writing stage, and the light emission duration compensation signal is a signal obtained before the data writing stage. The light emission duration control circuit is further configured to generate and output a first light emission control signal from the second terminal of the first capacitor based on the light emission duration driving data and the change in the control power supply signal. The light-emitting driving circuit, which is electrically connected to the second terminal of the first capacitor and the gate driving circuit, is configured to adjust the duration of its generation of driving signals in the display cycle according to the first light-emitting control signal. The sub-pixel is electrically connected to the light-emitting driving circuit and is configured to emit light according to the driving signal.

2. The display device according to claim 1, characterized in that, The display cycle includes a first stage, a data writing stage, and a display stage in sequence, and the light emission duration control circuit also includes a data writing unit; The light emission duration control circuit is configured to determine light emission duration driving data based on the control power supply signal obtained from the first terminal of the first capacitor and the light emission duration compensation data within the display cycle, including: The first end of the data writing unit is electrically connected to the data driving circuit, its second end is electrically connected to the power supply circuit, and its output end is electrically connected to the first end of the first capacitor. It is configured to, in the first stage, connect the output end and the first end, and turn off the second end, and output the light emission duration compensation data obtained from the first end from the output end. The data writing unit is further configured to output preset data obtained from the first terminal from the output terminal during the data writing phase. The first capacitor is configured to determine the light emission duration driving data based on the difference between the light emission duration compensation data and the preset data during the data writing phase.

3. The display device according to claim 2, characterized in that, The light emission duration control circuit is further configured to generate and output a first light emission control signal from the second terminal of the first capacitor based on the changes in the light emission duration driving data and the control power supply signal, including: The data writing unit is configured such that during the display phase, the output terminal and the second terminal are connected, and the first terminal is turned off, and the control power signal obtained from the second terminal is output from the output terminal, wherein the initial level value of the control power signal during the display phase is the same as the level value of the preset data; The first capacitor is also configured to, during the display phase, determine and output the first light-emitting control signal from its second terminal based on the light-emitting duration driving data, the amount of change in the control power signal, and its capacitance.

4. The display device according to claim 2 or 3, characterized in that, The data writing unit includes: The fifth transistor has a first terminal as the first terminal of the data writing unit, a second terminal as the output terminal of the data writing unit, and its control terminal is electrically connected to the gate driving circuit. It is configured to obtain a third scan signal from its control terminal and control its conduction state by the third scan signal. The seventh transistor has its first terminal serving as the second terminal of the data writing unit, its second terminal being electrically connected to the second terminal of the fifth transistor, and its control terminal being electrically connected to the gate driving circuit. It is configured to obtain a third light-emitting control signal from its control terminal and control its conduction state by the third light-emitting control signal.

5. The display device according to claim 1, characterized in that, The light-emitting driving circuit includes a light-emitting control circuit, a light-emitting threshold compensation circuit, and a reset circuit; the first stage includes a reset stage and a compensation stage in sequence. The reset circuit is electrically connected to the gate drive circuit, the power supply circuit, the light emission threshold compensation circuit, and the second terminal of the first capacitor. It is configured to obtain a first scan signal from the gate drive circuit, obtain a reference power supply signal from the power supply circuit, and be controlled by the first scan signal to output the reference power supply signal to reset the light emission threshold compensation circuit and the second terminal of the first capacitor. The light-emitting control circuit is electrically connected to the gate driving circuit, the power supply circuit, and the light-emitting threshold compensation circuit, and is configured to obtain a first power supply signal from the power supply circuit and a second light-emitting control signal from the gate driving circuit. During the compensation phase and the display phase of the display cycle, the second light-emitting control signal controls the output of the first power supply signal. The light emission threshold compensation circuit is electrically connected to the gate driving circuit and the second terminal of the first capacitor. The light emission threshold compensation circuit includes a driving transistor and is configured to obtain a second scan signal from the gate driving circuit, store the threshold voltage of the driving transistor in the first capacitor when the second scan signal is at a first level, and generate a driving signal based on the first light emission control signal when the second scan signal is at a second level. The light-emitting control circuit is also electrically connected to the sub-pixel and is configured to obtain a third light-emitting control signal from the gate driving circuit, obtain the driving signal from the light-emitting threshold compensation circuit, and control its output of the driving signal by the third light-emitting control signal.

6. The display device according to claim 1, characterized in that, A display cycle consists of the following phases in sequence: reset phase, compensation phase, data writing phase, and display phase. During the reset phase, the first scan signal and the third scan signal are at a first level, the second scan signal, the second light emission control signal and the third light emission control signal are at a second level, and the control power signal is adjusted from the first level to the second level. The reset circuit is turned on according to the first scan signal and transmits the obtained reference power supply signal to the second terminal of the first capacitor and the light emission threshold compensation circuit. The first capacitor resets its second terminal according to the reference power supply signal; The light emission threshold compensation circuit is reset according to the reference power supply signal; The fifth transistor is turned on according to the third scan signal, and transmits the light emission duration compensation data obtained at its first terminal to the second terminal, and stores it at the first terminal of the first capacitor.

7. The display device according to claim 6, characterized in that, During the compensation phase, the second scanning signal, the third scanning signal, and the second light emission control signal are at a first level, while the first scanning signal, the third light emission control signal, and the control power supply signal are at a second level. The light emission control circuit transmits the first power supply signal it obtains to the light emission threshold compensation circuit according to the second light emission control signal. The light emission threshold compensation circuit obtains a first power supply signal for threshold voltage compensation of the driving transistor based on the second scanning signal and the first power supply signal. The first capacitor stores the first power supply signal for threshold voltage compensation; The fifth transistor maintains the output of the light emission duration compensation data according to the third scan signal, so that the potential value of the first terminal of the first capacitor remains unchanged.

8. The display device according to claim 6, characterized in that, During the data writing phase, the third scan signal is at a first level, and the first scan signal, the second scan signal, the second light emission control signal, the third light emission control signal, and the control power signal are at a second level. The fifth transistor is turned on according to the third scan signal, and transmits the preset data obtained by its first terminal to the first terminal of the first capacitor; The first capacitor determines and stores the light emission duration driving data from its second terminal based on the difference between the light emission duration compensation data and the preset data, its capacitance value, and the first power supply signal for threshold voltage compensation of the driving transistor; The preset data level value is the same as the second level level value.

9. The display device according to claim 6, characterized in that, During the display phase, the second light emission control signal and the third light emission control signal are at a first level, the first scan signal, the second scan signal and the third scan signal are at a second level, and the control power signal is a ramp signal that is adjusted from the second level to the first level; The light emission control circuit transmits the first power supply signal it obtains to the light emission threshold compensation circuit according to the second light emission control signal. The seventh transistor is turned on according to the third light-emitting control signal, and transmits the control power signal obtained at its first terminal to the first terminal of the first capacitor. The first capacitor outputs the first light emission control signal from its second terminal based on the potential change at its first terminal and the light emission duration driving data stored therein. The light emission threshold compensation circuit determines a preset voltage range based on the first power supply signal, and generates a driving signal based on the first light emission control signal and the preset voltage range. The light emission control circuit transmits the driving signal to the sub-pixel when it receives the driving signal, based on the third light emission control signal. The sub-pixel emits light according to the driving signal.

10. The display device according to claim 9, characterized in that, The display phase includes a non-light-emitting period and a light-emitting period; The light emission threshold compensation circuit determines a preset voltage range based on the first power supply signal, and generates a driving signal based on the first light emission control signal and the preset voltage range, including: During the non-light-emitting period, the control power supply signal is a ramp signal adjusted from the second level to the third level, the potential value of the first light-emitting control signal is not within the preset voltage range, and the light-emitting threshold compensation circuit does not generate a drive signal. During the light emission period, the control power supply signal is a ramp signal that is adjusted from the third level to the first level, the potential value of the first light emission control signal is within the preset voltage range, and the light emission threshold compensation circuit generates a drive signal. The third level is located between the first level and the second level.

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