Light-emitting signal generating circuit and shift register

Abstract

The invention discloses a light-emitting signal generating circuit which is used for driving a pixel row and comprises a first circuit unit, a second circuit unit and a third circuit unit. The first circuit unit generates a total light-emitting signal according to a total clock signal, a first reference signal and a second reference signal. The second circuit unit is coupled to the first circuit unit and generates a first light-emitting signal according to the total light-emitting signal, the first reference signal, the second reference signal and the first clock signal so as to drive the first sub-pixel and the third sub-pixel of the pixel row. The third circuit unit is coupled to the first circuit unit and generates a second light-emitting signal according to the total light-emitting signal, the first reference signal, the second reference signal and the second clock signal so as to drive the second sub-pixel of the pixel row.

Description

Technical Field

[0001] The present disclosure relates to a luminous signal generating circuit and a shift register. Background Art

[0002] In order to drive the pixel circuit on the display panel, it is necessary to configure a light emitting signal generating circuit and a scanning signal generating circuit to supply various driving signals to the pixel circuit, thereby controlling the light emitting time and light emitting brightness of the pixel circuit. However, as the application of pixel circuits becomes more complex, the number of driving signals also increases, resulting in an increase in the number of pins and wires of the driving circuit, which is not only not conducive to reducing costs, but also occupies too much volume in the display device. Summary of the invention

[0003] Therefore, the embodiment of the present disclosure provides a light-emitting signal generating circuit for driving a pixel row, and includes a first circuit unit, a second circuit unit, and a third circuit unit. The first circuit unit is used to generate a total light-emitting signal according to a plurality of total clock signals, a first reference signal, and a second reference signal. The second circuit unit is coupled to the first circuit unit, and is used to generate a first light-emitting signal according to the total light-emitting signal, the first reference signal, the second reference signal, and the first clock signal, wherein the first light-emitting signal is used to drive the first sub-pixel and the third sub-pixel in this pixel row. The third circuit unit is coupled to the first circuit unit, and is used to generate a second light-emitting signal according to the total light-emitting signal, the first reference signal, the second reference signal, and the second clock signal, wherein the second light-emitting signal is used to drive the second sub-pixel in this pixel row.

[0004] According to an embodiment of the present disclosure, the first circuit unit further includes a coupling circuit. The coupling circuit is configured as an output stage of the first circuit unit and is used to transmit the first reference signal and the second reference signal to the second circuit unit and the third circuit unit.

[0005] According to an embodiment of the present disclosure, the second circuit unit and the third circuit unit are coupled to a first node of the coupling circuit, and the coupling circuit includes a first transistor and a second transistor. The first end of the first transistor receives a first reference signal, and the second end thereof is coupled to the first node, wherein the first transistor is turned on and transmits the first reference signal to the first node. The first end of the second transistor is coupled to the first node, and the second end thereof receives a second reference signal, wherein the second transistor is turned on and transmits the second reference signal to the first node.

[0006] Another embodiment of the present disclosure provides a light-emitting signal generating circuit, which is configured to drive a pixel row and includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is used to generate a total light-emitting signal based on a plurality of total clock signals, a first reference signal, and a second reference signal. The second circuit unit is coupled to the first circuit unit, and is used to generate a first light-emitting signal based on the total light-emitting signal, the first reference signal, the second reference signal, and the first clock signal, wherein the first light-emitting signal is used to drive a first sub-pixel in this pixel row. The third circuit unit is coupled to the first circuit unit, and is used to generate a second light-emitting signal based on the total light-emitting signal, the first reference signal, the second reference signal, and the second clock signal, wherein the second light-emitting signal is used to drive a second sub-pixel in this pixel row. The fourth circuit unit is coupled to the first circuit unit, and is used to generate a third light-emitting signal based on the total light-emitting signal, the first reference signal, the second reference signal, and the third clock signal, wherein the third light-emitting signal is used to drive a third sub-pixel in this pixel row.

[0007] According to an embodiment of the present disclosure, the first circuit unit further includes a coupling circuit. The coupling circuit is configured as an output stage of the first circuit unit and is used to transmit the first reference signal and the second reference signal to the second circuit unit, the third circuit unit and the fourth circuit unit.

[0008] According to an embodiment of the present disclosure, the second circuit unit, the third circuit unit, and the fourth circuit unit are coupled to a first node of the coupling circuit, and the coupling circuit includes a first transistor and a second transistor. The first end of the first transistor receives a first reference signal, and the second end thereof is coupled to the first node, wherein the first transistor is turned on and transmits the first reference signal to the first node. The first end of the second transistor is coupled to the first node, and the second end thereof receives a second reference signal, wherein the second transistor is turned on and transmits the second reference signal to the first node.

[0009] According to an embodiment of the present disclosure, each of the second circuit unit, the third circuit unit and the fourth circuit unit includes a third transistor, a fourth transistor, a fifth transistor and a capacitor. The first end of the third transistor is coupled to the first node, and the control end thereof receives the first reference signal. The first end of the fourth transistor receives the corresponding first clock signal, the second clock signal or the third clock signal, and the control end thereof is coupled to the second end of the third transistor at the second node. The first end of the fifth transistor is coupled to the second end of the fourth transistor at the third node, and the second end thereof receives the second reference signal. The first end of the capacitor is coupled to the second node, and the second end thereof is coupled to the third node to output the corresponding first light-emitting signal, the second light-emitting signal or the third light-emitting signal.

[0010] Another embodiment of the present disclosure provides a shift register, comprising a plurality of light-emitting signal generating circuits. These light-emitting signal generating circuits are used to generate and transmit a total light-emitting signal to sequentially drive each pixel row, and each of these light-emitting signal generating circuits comprises a first circuit unit, a second circuit unit and a third circuit unit. The first circuit unit is used to generate a total light-emitting signal based on a plurality of total clock signals, a first reference signal and a second reference signal. The second circuit unit is coupled to the first circuit unit, and is used to generate a first light-emitting signal based on the total light-emitting signal, the first reference signal, the second reference signal and the first clock signal, wherein the first light-emitting signal is used to drive a first sub-pixel and a third sub-pixel in the first pixel row. The third circuit unit is coupled to the first circuit unit, and is used to generate a second light-emitting signal based on the total light-emitting signal, the first reference signal, the second reference signal and the second clock signal, wherein the second light-emitting signal is used to drive a second sub-pixel in the first pixel row.

[0011] According to an embodiment of the present disclosure, the first circuit unit further includes a coupling circuit. The coupling circuit is configured as an output stage of the first circuit unit and is used to transmit the first reference signal and the second reference signal to the second circuit unit and the third circuit unit.

[0012] According to an embodiment of the present disclosure, the second circuit unit and the third circuit unit are coupled to a first node of the coupling circuit, and the coupling circuit includes a first transistor and a second transistor. The first end of the first transistor receives a first reference signal, and the second end thereof is coupled to the first node, wherein the first transistor is turned on and transmits the first reference signal to the first node. The first end of the second transistor is coupled to the first node, and the second end thereof receives a second reference signal, wherein the second transistor is turned on and transmits the second reference signal to the first node. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To make the above and other features, advantages and embodiments of the present invention more understandable, the accompanying drawings are described as follows:

[0014] Figure 1 It is a schematic diagram of the structure of a pixel circuit, a light emitting signal generating circuit and a scanning signal generating circuit according to an embodiment of the present invention;

[0015] Figure 2 is a schematic diagram of a shift register according to an embodiment of the present invention;

[0016] Figure 3 is a schematic diagram of a light emitting signal generating circuit according to an embodiment of the present invention;

[0017] Figure 4 A timing waveform diagram of a driving signal of a pixel circuit according to an embodiment of the present invention;

[0018] Figure 5is a schematic diagram of a shift register according to another embodiment of the present invention;

[0019] Figure 6 is a schematic diagram of a light emitting signal generating circuit according to another embodiment of the present invention; and

[0020] Figure 7 FIG. 4 is a timing waveform diagram of a driving signal of a pixel circuit according to another embodiment of the present invention.

[0021] Wherein, the reference numerals are:

[0022] 10: Pixel Array

[0023] 100: Shift register

[0024] 110: Luminous signal generating circuit

[0025] 111: first circuit unit

[0026] 111a: Coupling circuit

[0027] 112: Second circuit unit

[0028] 113: The third circuit unit

[0029] 200: Shift register

[0030] 210: Luminous signal generating circuit

[0031] 211: first circuit unit

[0032] 212: Second circuit unit

[0033] 213: Third circuit unit

[0034] 214: Fourth circuit unit

[0035] B[1],B[2],B[3],B[n]: luminous signal

[0036] B_CK: Clock signal

[0037] CKE, XCKE: total clock signal

[0038] C1, C2, C4a, C4b, C4c: capacitors

[0039] EMT[1],EMT[2],EMT[3],EMT[n]: total luminescence signal

[0040] EMT[n-1],EMT[n+1]: total luminescence signal

[0041] G_CK: Second clock signal

[0042] G[1],G[2],G[3],G[n]: luminous signal

[0043] P: Pixel circuit

[0044] P1, P2, P3: Luminous time

[0045] Q1-Q4,QA,QB,QC,QD1-QD3,QR:Node

[0046] RB_CK: First clock signal

[0047] RB[1],RB[2],RB[3],RB[n]: luminous signal

[0048] R[1], R[2], R[3], R[n]: luminous signal

[0049] RS[n]: scanning signal

[0050] WS[n]: data write signal

[0051] Reset: Reset signal

[0052] SR: Scanning signal generating circuit

[0053] T1-T11,T15: Transistor

[0054] T12a-T12c,T13a-T13c,T14a-T14c: Transistors

[0055] U2D,D2U: Select signal

[0056] VGL: First reference signal

[0057] VGH: Second reference signal

[0058] VSTV: Start signal

[0059] VEND: End signal DETAILED DESCRIPTION

[0060] The following disclosure provides many different embodiments or examples for implementing different features of the provided invention. The embodiments of the components and configurations described below are provided as examples only and are not intended to be limiting. In addition, for the purpose of simplicity and clarity, the disclosure repeats reference symbols and / or numbers in each example, which in itself does not limit the relationship between the various embodiments and / or components discussed.

[0061] Please refer to Figure 1 , Figure 1Schematic diagram of the structure of the pixel circuit P, the light-emitting signal generating circuit 110 and the scanning signal generating circuit SR according to an embodiment of the present invention. The light-emitting signal generating circuit 110 and the scanning signal generating circuit SR are coupled to the pixel circuit P in the pixel array 10 of the display panel (not shown), and are configured to provide a variety of driving signals required by the pixel circuit P in a time-sharing manner. In the embodiment of the present invention, the driving signal includes but is not limited to the scanning signal RS[n], the data writing signal WS[n] and the light-emitting signal EM[n], etc., which can be used to control the operation of the transistors and capacitors in the pixel circuit P, and further control the light-emitting time and light-emitting brightness of the light-emitting element (e.g., light-emitting diode) therein.

[0062] In an embodiment of the present invention, each row of the pixel array 10 includes a plurality of pixel circuits P, and each pixel circuit P can represent one of the first sub-pixel (e.g., a red sub-pixel), the second sub-pixel (e.g., a green sub-pixel), and the third sub-pixel (e.g., a blue sub-pixel).

[0063] Please refer to Figure 2 , Figure 2 1 is a schematic diagram of a shift register 100 according to an embodiment of the present invention. The shift register 100 includes a plurality of light emitting signal generating circuits 110, and each light emitting signal generating circuit 110 includes a first circuit unit 111, a second circuit unit 112, and a third circuit unit 113 to sequentially drive corresponding pixel rows on the display panel. It should be understood that for the sake of simplicity, Figure 2 Only one set of luminous signal generating circuit 110 and its internal component circuits are marked.

[0064] Taking the first-stage light-emitting signal generating circuit 110 as an example, the first circuit unit 111 thereof generates a light-emitting signal according to the total clock signals XCKE and CKE, the first reference signal VGL and the second reference signal VGH ( Figure 2 The first-stage light-emitting signal generating circuit 110 (not shown) generates a total light-emitting signal EMT[1] to further control the second circuit unit 112 and the third circuit unit 113 connected in series to generate the first light-emitting signal RB[1] and the second light-emitting signal G[1] to the corresponding pixel circuits P in the first pixel row. The total light-emitting signal EMT[1] generated by the first-stage light-emitting signal generating circuit 110 is also transmitted to the second-stage light-emitting signal generating circuit 110 to trigger the second-stage light-emitting signal generating circuit 110 to continue to operate. Similarly, the pixel circuits P in the 1st row to the nth row are sequentially driven by the first light-emitting signals RB[1] to RB[n] and the second light-emitting signals G[1] to G[n].

[0065] Specifically, the second circuit unit 112 and the third circuit unit 113 are coupled to the first circuit unit 111, wherein the second circuit unit 112 generates the first light-emitting signal RB[1] according to the total light-emitting signal EMT[1] generated by the first circuit unit 111, the first reference signal VGL, the second reference signal VGH and the first clock signal RB_CK, and the third circuit unit 113 generates the second light-emitting signal G[1] according to the total light-emitting signal EMT[1] generated by the first circuit unit 111, the first reference signal VGL, the second reference signal VGH and the second clock signal G_CK.

[0066] In the embodiment of the present invention, each pixel circuit P in the first pixel row receives the first light emitting signal RB[1] supplied by the second circuit unit 112 or the second light emitting signal G[1] supplied by the third circuit unit 113 according to the color sub-pixel it represents. Figure 2 In the example shown, the pixel circuit P serving as a red sub-pixel and the pixel circuit P serving as a blue sub-pixel share the same light-emitting signal, i.e., receive the first light-emitting signal RB[1] supplied by the second circuit unit 112; and the pixel circuit P serving as a green sub-pixel independently uses another set of light-emitting signals, i.e., receives the second light-emitting signal G[1] supplied by the third circuit unit 113.

[0067] Specifically, each level of the light-emitting signal generating circuit 110 drives the second circuit unit 112 and the third circuit unit 113 through a single first circuit unit 111, and can independently separate the color sub-pixels to be controlled separately, so as to optimize the light-emitting time of the red sub-pixels, the blue sub-pixels and the green sub-pixels respectively and improve the overall efficiency. Compared with the architecture of pushing one group of circuit units to provide light-emitting signals, this architecture of pushing multiple groups of circuit units can more effectively save the number of pins and the number of wires required for the driving signal.

[0068] Please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a light emitting signal generating circuit 110 according to an embodiment of the present invention, and illustrates the internal circuit structure of a first circuit unit 111 , a second circuit unit 112 , and a third circuit unit 113 .

[0069] The first circuit unit 111 includes transistors T1 to T11, a transistor T15, and capacitors C1 and C2. The first end of the transistor T9 receives the previous stage total light emitting signal EMT[n-1] (or the start signal VSTV), and the second end of the transistor T9 is coupled to the first end of the transistor T10. The second end of the transistor T10 receives the next stage total light emitting signal EMT[n+1] (or the end signal VEND). The control ends of the transistors T9 and T10 receive the selection signals U2D and D2U, respectively. The selection signals U2D and D2U are used to set the scanning direction of the multi-stage light emitting signal generating circuit 110 in the display panel. When the selection signal U2D is a logic low voltage, the previous stage total light emitting signal EMT[n-1] is transmitted to the node Q4, and when the selection signal D2U is a logic low voltage, the next stage total light emitting signal EMT[n+1] is transmitted to the node Q4.

[0070] It should be understood that in applications where the first circuit unit 111 includes the selection signals U2D and D2U, Figure 2 The total luminous signals EMT[1] to EMT[n-1] between each stage of the luminous signal generating circuit 110 can also be transmitted in the reverse direction to drive the second circuit unit 112 and the third circuit unit 113 connected in series to generate corresponding luminous signals when operating normally.

[0071] Please continue to refer to Figure 3 The first circuit unit 111 receives several total clock signals (for example, the total clock signals CKE and XCKE), the first reference signal VGL and the second reference signal VGH, and the previous stage total light-emitting signal EMT[n-1] or the subsequent stage total light-emitting signal EMT[n+1] received by the node Q4, and outputs the total light-emitting signal EMT[n] between the transistor T2 and the transistor T3 according to the above signals.

[0072] The transistor T11 and the transistor T15 are the output stage of the first circuit unit 111, and are configured as a coupling circuit 111a to transmit the first reference signal VGL and the second reference signal VGH to the second circuit unit 112 and the third circuit unit 113, so that the second circuit unit 112 generates the first light-emitting signal RB[1] at the output end according to the total light-emitting signal EMT[n], the first reference signal VGL, the second reference signal VGH and the first clock signal RB_CK, and the third circuit unit 113 generates the second light-emitting signal G[1] according to the total light-emitting signal EMT[n], the first reference signal VGL, the second reference signal VGH and the second clock signal G_CK.

[0073] In detail, the second circuit unit 112 and the third circuit unit 113 are coupled to the node QR of the coupling circuit 111a. The first end of the transistor T11 receives the first reference signal VGL, the second end thereof is coupled to the node QR, and the control end thereof is coupled to the node Q1. The transistor T11 is turned on or off according to the control signal received at the node Q1, and then transmits the first reference signal VGL to the node QR during the on-time. The first end of the transistor T15 is coupled to the node QR, the second end thereof receives the second reference signal VGH, and the control end thereof is coupled to the node Q3. The transistor T15 is turned on or off according to the control signal received at the node Q3, and then transmits the second reference signal VGH to the node QR during the on-time.

[0074] Each of the second circuit unit 112 and the third circuit unit 113 includes a plurality of transistors and a capacitor. The second circuit unit 112 includes a capacitor C4a and transistors T12a-T14a, and the third circuit unit 113 includes a capacitor C4b and transistors T12b-T14b.

[0075] The first end of the transistor T12a is coupled to the node QR, and the control end thereof receives the first reference signal VGL. The first end of the transistor T13a receives the first clock signal RB_CK, and the control end thereof is coupled to the second end of the transistor T12a at the node QA. The first end of the transistor T14a is coupled to the second end of the transistor T13a at the node QD1, and the second end thereof receives the second reference signal VGH. The first end of the capacitor C4a is coupled to the node QA, and the second end thereof is coupled to the node QD1 to output the first light emitting signal RB[n], thereby driving the pixel circuit P in the nth row as the red sub-pixel and the blue sub-pixel.

[0076] The first end of the transistor T12b is coupled to the node QR, and the control end thereof receives the first reference signal VGL. The first end of the transistor T13b receives the second clock signal G_CK, and the control end thereof is coupled to the second end of the transistor T12b at the node QB. The first end of the transistor T14b is coupled to the second end of the transistor T13b at the node QD2, and the second end thereof receives the second reference signal VGH. The first end of the capacitor C4b is coupled to the node QB, and the second end thereof is coupled to the node QD2 to output the second light emitting signal G[n], thereby driving the pixel circuit P in the nth row as a green sub-pixel.

[0077] Please refer to Figure 4 , Figure 4 1 is a timing waveform diagram of a driving signal of a pixel circuit P according to an embodiment of the present invention, wherein the driving signal comprises a scan signal RS[n], a data write signal WS[n], a first light emitting signal RB[n] and a second light emitting signal G[n].

[0078] The scan signal RS[n] and the data write signal WS[n] are generated by Figure 1 The first light emitting signal RB[n] and the second light emitting signal G[n] are provided by the scanning signal generating circuit SR shown in the figure, while the first light emitting signal RB[n] and the second light emitting signal G[n] are provided by the light emitting signal generating circuit 110 of the present invention. It can be found that since the second light emitting signal G[n] supplied to the red sub-pixel and the blue sub-pixel is relatively independent of the first light emitting signal RB[n] supplied to the green sub-pixel, the light emitting time P2 (or duty cycle) of the pixel circuit P as the green sub-pixel can be independently controlled.

[0079] It should be understood that the present invention can select any two of the red sub-pixel, the blue sub-pixel and the green sub-pixel to be controlled by the same light-emitting signal according to actual needs, and the remaining one is independently controlled by another light-emitting signal. In this way, not only the overall light-emitting efficiency can be improved, but also the number of pins and wires can be minimized.

[0080] Please refer to Figure 5 , Figure 5 FIG. 2 is a schematic diagram of a shift register 200 according to another embodiment of the present invention. The shift register 200 includes a plurality of light emitting signal generating circuits 210, and each light emitting signal generating circuit 210 includes a first circuit unit 211, a second circuit unit 212, a third circuit unit 213, and a fourth circuit unit 214 to sequentially drive corresponding pixel rows on the display panel.

[0081] Compared to Figure 2 The difference of the shift register 100 shown in the figure is that the pixel circuits P as the red sub-pixel, the blue sub-pixel and the green sub-pixel are all independently controlled by the second circuit unit 212, the third circuit unit 213 and the fourth circuit unit 214 and the first light-emitting signal R[n], the second light-emitting signal G[n] and the third light-emitting signal B[n] supplied by them. In such an embodiment, the light-emitting time of each sub-pixel of the three colors can be independently adjusted to achieve the optimized overall light-emitting efficiency, and the light-emitting signal generating circuit 210 and the fourth circuit unit 214 are controlled independently. Figure 1 The light emitting signal generating circuit 110 also has a one-push-multiple circuit unit structure, which can also effectively save the number of pins and wires required for the driving signal.

[0082] Please refer to Figure 6 , Figure 6FIG. 2 is a schematic diagram of a light emitting signal generating circuit 210 according to another embodiment of the present invention, and illustrates the internal circuit structure of a first circuit unit 211, a second circuit unit 212, a third circuit unit 213, and a fourth circuit unit 214. Since the circuit operation and structure of the light emitting signal generating circuit 210 are similar to those of the light emitting signal generating circuit 110, and the newly added fourth circuit unit 214 is also similar to the first circuit unit 211, the second circuit unit 212, and the third circuit unit 213, no further details will be given here.

[0083] Please refer to Figure 7 , Figure 7 FIG. 1 is a timing waveform diagram of a driving signal of a pixel circuit P according to another embodiment of the present invention, wherein the driving signal includes a scanning signal RS[n], a data writing signal WS[n], a first light emitting signal R[n], a second light emitting signal G[n] and a third light emitting signal B[n]. The scanning signal RS[n] and the data writing signal WS[n] are also generated by Figure 1 The first light emitting signal R[n], the second light emitting signal G[n] and the third light emitting signal B[n] are provided by the light emitting signal generating circuit 210 of the present invention.

[0084] It can be found that since the first light emitting signal R[n], the second light emitting signal G[n] and the third light emitting signal B[n] supplied to the red sub-pixel, the blue sub-pixel and the green sub-pixel are all independent light emitting signals, the light emitting time P1, P2 and P3 of each color sub-pixel can be independently controlled. In this way, not only the light emitting efficiency can be optimized, but also the number of pins and the number of wires can be reduced.

[0085] In summary, the shift register and the light-emitting signal generating circuit of the present invention supply light-emitting signals to each pixel row through a one-push-multiple circuit unit architecture, which can not only effectively save the number of pins and wires required for the driving signal, but also further isolate the color sub-pixels that need to be more regulated, thereby improving the overall light-emitting efficiency.

[0086] Although the present invention has been disclosed as above in various embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A luminous signal generating circuit, characterized in that: The invention is used for driving a pixel row in a pixel array, and comprises: A first circuit unit, for generating a total light-emitting signal according to a plurality of total clock signals, a first reference signal and a second reference signal; a second circuit unit, coupled to the first circuit unit, and used for generating a first light-emitting signal according to the total light-emitting signal, the first reference signal, the second reference signal and a first clock signal, wherein the first light-emitting signal is used for driving a first sub-pixel and a third sub-pixel of the pixel row; as well as A third circuit unit is coupled to the first circuit unit and is used to generate a second light emitting signal according to the total light emitting signal, the first reference signal, the second reference signal and a second clock signal, wherein the second light emitting signal is used to drive a second sub-pixel of the pixel row.

2. The luminous signal generating circuit according to claim 1, characterized in that: The first circuit unit further comprises: A coupling circuit is configured as an output stage of the first circuit unit and is used to transmit the first reference signal and the second reference signal to the second circuit unit and the third circuit unit.

3. The luminous signal generating circuit according to claim 2, characterized in that: The second circuit unit and the third circuit unit are coupled to a first node of the coupling circuit, and the coupling circuit comprises: a first transistor, a first terminal of which receives the first reference signal and a second terminal of which is coupled to the first node, wherein the first transistor is turned on to transmit the first reference signal to the first node; as well as A second transistor has a first terminal coupled to the first node and a second terminal receiving the second reference signal, wherein the second transistor is turned on to transmit the second reference signal to the first node.

4. A luminous signal generating circuit, characterized in that: The device is configured to drive a pixel row and comprises: A first circuit unit, for generating a total light-emitting signal according to a plurality of total clock signals, a first reference signal and a second reference signal; a second circuit unit, coupled to the first circuit unit, and used for generating a first light-emitting signal according to the total light-emitting signal, the first reference signal, the second reference signal and a first clock signal, wherein the first light-emitting signal is used for driving a first sub-pixel in the pixel row; a third circuit unit, coupled to the first circuit unit, and used for generating a second light emitting signal according to the total light emitting signal, the first reference signal, the second reference signal and a second clock signal, wherein the second light emitting signal is used for driving a second sub-pixel of the pixel row; as well as A fourth circuit unit is coupled to the first circuit unit and is used to generate a third light emitting signal according to the total light emitting signal, the first reference signal, the second reference signal and a third clock signal, wherein the third light emitting signal is used to drive a third sub-pixel of the pixel row.

5. The luminous signal generating circuit as claimed in claim 4, characterized in that: The first circuit unit further comprises: A coupling circuit is configured as an output stage of the first circuit unit and is used to transmit the first reference signal and the second reference signal to the second circuit unit, the third circuit unit and the fourth circuit unit.

6. The luminous signal generating circuit according to claim 5, characterized in that: The second circuit unit, the third circuit unit and the fourth circuit unit are coupled to a first node of the coupling circuit, and the coupling circuit comprises: a first transistor, a first terminal of which receives the first reference signal and a second terminal of which is coupled to the first node, wherein the first transistor is turned on to transmit the first reference signal to the first node; as well as A second transistor has a first terminal coupled to the first node and a second terminal receiving the second reference signal, wherein the second transistor is turned on to transmit the second reference signal to the first node.

7. The luminous signal generating circuit according to claim 6, characterized in that: The second circuit unit, the third circuit unit and the fourth circuit unit each include: a third transistor, a first terminal of which is coupled to the first node, and a control terminal of which receives the first reference signal; a fourth transistor, a first end of which receives the first clock signal, the second clock signal or the third clock signal, and a control end of which is coupled to the second end of the third transistor at a second node; a fifth transistor, a first terminal of which is coupled to the second terminal of the fourth transistor at a third node, and a second terminal of which receives the second reference signal; as well as A capacitor has a first end coupled to the second node and a second end coupled to the third node to output the corresponding first light emitting signal, the second light emitting signal or the third light emitting signal.

8. A shift register, characterized in that: Include: A plurality of light emitting signal generating circuits are used to respectively generate and transmit a total light emitting signal to sequentially drive a plurality of pixel rows in a pixel array, and each of the light emitting signal generating circuits comprises: A first circuit unit, used for generating the total light-emitting signal according to a plurality of total clock signals, a first reference signal and a second reference signal; a second circuit unit, coupled to the first circuit unit, and used for generating a first light-emitting signal according to the total light-emitting signal, the first reference signal, the second reference signal and a first clock signal, wherein the first light-emitting signal is used for driving a first sub-pixel and a third sub-pixel of a first pixel row among the pixel rows; as well as A third circuit unit is coupled to the first circuit unit and is used to generate a second light-emitting signal according to the total light-emitting signal, the first reference signal, the second reference signal and a second clock signal, wherein the second light-emitting signal is used to drive a second sub-pixel of the first pixel row.

9. The shift register as claimed in claim 8, wherein: The first circuit unit further comprises: A coupling circuit is configured as an output stage of the first circuit unit and is used to transmit the first reference signal and the second reference signal to the second circuit unit and the third circuit unit.

10. The shift register as claimed in claim 9, wherein: The second circuit unit and the third circuit unit are coupled to a first node of the coupling circuit, and the coupling circuit comprises: a first transistor, a first terminal of which receives the first reference signal and a second terminal of which is coupled to the first node, wherein the first transistor is turned on to transmit the first reference signal to the first node; as well as A second transistor has a first terminal coupled to the first node and a second terminal receiving the second reference signal, wherein the second transistor is turned on to transmit the second reference signal to the first node.

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