Display panel and driving method thereof

Abstract

The present invention provides a display panel and a driving method thereof, wherein a first reset transistor in a pixel circuit is used to reset one of the anode and cathode of a light-emitting element according to a first reset signal, and sub-pixels in the 1st to mth sub-display areas turned on sequentially all receive the same first reset signal, and the refresh rate of the display panel in the nth frame is greater than the refresh rate in the (n+1)th frame, and the first and second display areas of the display panel both display images in the nth frame, and only the first display area displays the image in the (n+1)th frame, and the amplitude of the first reset signal corresponding to the 1st to mth sub-display areas in the nth frame gradually decreases or increases, and is greater than or less than its amplitude in the (n+1)th frame, so as to improve the flickering phenomenon of the lower half of the screen when the AOD function is initially turned on.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a driving method thereof. Background Art

[0002] OLED (Organic Light Emitting Diode) display devices are self-luminous, so they can precisely control the lighting of each pixel on the screen, thus having an AOD (Always On Display) function, that is, most of the screen is no longer displayed, and only a small area is retained to display important information.

[0003] However, when the AOD function is turned on, the refresh rate is usually lowered to reduce power consumption. When switching to the AOD function, the gate drive circuit is transmitted from top to bottom, and the upper half of the screen is scanned at a lower refresh rate, resulting in the voltage of the pixel circuit in the lower half of the screen being unable to be refreshed for a long period of time, and still maintaining the voltage value at the previous higher refresh rate, so that the lower half of the screen still shows the picture when the AOD function is not turned on, causing the lower half of the screen to still flash in the early stage of turning on the AOD function. Summary of the Invention

[0004] The present invention aims to provide a display panel and a driving method thereof, so as to improve the problem that the lower half of the screen of the existing OLED display device still flashes in the early stage of turning on the AOD function.

[0005] An embodiment of the present invention provides a display panel, wherein a display area of ​​the display panel includes a first display area and a second display area located at least below the first display area, the display area is divided into a first sub-display area to an mth sub-display area, and subpixels in the first sub-display area to the mth sub-display area are sequentially turned on within a frame, where m is a positive integer greater than 1;

[0006] The sub-pixel includes a pixel circuit and a light-emitting element that are electrically connected, and the pixel circuit includes:

[0007] a driving transistor electrically connected to the light emitting element and configured to generate a driving current according to a data signal to drive the light emitting element to emit light;

[0008] a first reset transistor electrically connected to the light-emitting element, configured to reset one of an anode and a cathode of the light-emitting element according to a first reset signal, wherein the sub-pixels in the first to m-th sub-display areas all receive the same first reset signal;

[0009] The refresh rate of the display panel in the nth frame is greater than the refresh rate in the (n+1)th frame, the first display area and the second display area both display images in the nth frame, and the first display area displays images and the second display area is turned off in the (n+1)th frame, where n is a positive integer;

[0010] The amplitude of the first reset signal in the nth frame includes a first sub-amplitude to an mth sub-amplitude corresponding to the first sub-display area to the mth sub-display area;

[0011] The first sub-amplitude to the mth sub-amplitude gradually decrease and are all greater than the amplitude of the first reset signal in the (n+1)th frame;

[0012] Alternatively, the first sub-amplitude to the mth sub-amplitude gradually increase and are all smaller than the amplitude of the first reset signal in the (n+1)th frame.

[0013] An embodiment of the present invention further provides a display panel, wherein a display area of ​​the display panel includes a first display area and a second display area located at least below the first display area, the display area is divided into a first sub-display area to an m-th sub-display area, and subpixels in the first sub-display area to the m-th sub-display area are sequentially turned on within a frame, where m is a positive integer greater than 1;

[0014] The refresh rate of the display panel in the nth frame is greater than the refresh rate in the (n+1)th frame, the first display area and the second display area both display images in the nth frame, and the first display area displays images and the second display area is turned off in the (n+1)th frame, where n is a positive integer;

[0015] In the nth frame, the sub-pixels in the 1st sub-display area to the mth sub-display area are controlled by m first driving signals whose amplitudes decrease or increase sequentially, and in the (n+1)th frame, the sub-pixels in the 1st sub-display area to the mth sub-display area are controlled by the same second driving signal whose amplitude is smaller than or greater than multiple first driving signals.

[0016] An embodiment of the present invention further provides a method for driving a display panel, the method comprising:

[0017] receiving a display mode switching instruction for switching the display panel from a first display mode to a second display mode, wherein a refresh frequency of the first display mode is higher than a refresh frequency of the second display mode;

[0018] maintaining the refresh rate of the display panel at the refresh rate of the first display mode within a preset number of frames after receiving the display mode switching instruction, and applying driving voltage signals with successively increasing or decreasing amplitudes to the sub-pixels of the plurality of sequentially turned-on regions of the display panel;

[0019] After the preset number of frames, the display panel is controlled to display images in the second display mode, and the amplitude of the driving voltage signal is controlled to be greater than or less than the amplitude of the driving voltage signal within the preset number of frames.

[0020] The present invention provides a display panel and a driving method thereof, wherein the display panel has a first display area and a second display area at least located below the first display area, sub-pixels in the first to m-th sub-display areas of the display panel are sequentially turned on within a frame, the pixel circuit includes a first reset transistor for resetting one of the anode and the cathode of the light-emitting element according to a first reset signal, the sub-pixels in the plurality of sub-display areas all receive the same first reset signal, the refresh rate of the display panel in the n-th frame is greater than the refresh rate in the (n+1)-th frame, the first display area and the second display area both display images in the n-th frame, and the image is turned on in the (n+1)-th frame. The first display area displays a picture and the second display area is off, and n is a positive integer. By setting the 1st sub-amplitude to the mth sub-amplitude of the first reset signal corresponding to the 1st sub-display area to the mth sub-display area in the nth frame to gradually decrease and be greater than the amplitude of the first reset signal in the (n+1) frame, or setting the 1st sub-amplitude to the mth sub-amplitude to gradually increase and be less than the amplitude of the first reset signal in the (n+1) frame, the brightness of the area below the display area in the initial second display area in the (n+1) frame will be reduced, thereby improving the flickering phenomenon of the area below the display area in the second display area in the (n+1) frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings described below are only used to illustrate some embodiments of the present invention, and those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0022] Figure 1 A schematic top view of a display panel provided by an embodiment of the present invention.

[0023] Figure 2 A pixel circuit diagram of a sub-pixel provided in an embodiment of the present invention.

[0024] Figures 3 to 5 This is a timing diagram of some signals provided by an embodiment of the present invention.

[0025] Figure 6 This is a flow chart of a method for driving a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined, and "electrically connected" means that there is conductivity between the two, and is not limited to direct connection or indirect connection.

[0028] In addition, it should be noted that the drawings only provide structures and steps that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is exactly the same as the attached drawings. Figure 1 The same is not a limitation of the actual device.

[0029] The present invention provides a display panel, which may include but is not limited to the following embodiments and combinations of the following embodiments.

[0030] In some embodiments, combined Figure 1 and Figure 2As shown, the display area of ​​the display panel 100 includes a first display area A1 and a second display area A2 at least located below the first display area A1. The display panel 100 includes a plurality of sub-pixels Pi, and the plurality of sub-pixels Pi are divided into a plurality of sub-display areas a. The sub-pixels Pi in the plurality of sub-display areas a are sequentially turned on in one frame. For example, the plurality of sub-display areas a are sequentially from the 1st sub-display area to the mth sub-display area, where m is a positive integer greater than 1. Then, the sub-pixels in the 1st sub-display area to the mth sub-display area are sequentially turned on in one frame. The sub-pixels Pi include electrically connected The pixel circuit 200 and the light-emitting element Di are connected, and the pixel circuit 200 includes: a driving transistor T1, which is electrically connected to the light-emitting element Di and is used to generate a driving current according to a data signal Data to drive the light-emitting element Di to emit light; a first reset transistor T7, which is electrically connected to the light-emitting element Di and is used to reset one of the anode and the cathode of the light-emitting element Di according to a first reset signal Vref1 (the former is used as an example here), and the sub-pixels Pi in the plurality of sub-display areas a (i.e., the 1st sub-display area to the mth sub-display area) are all electrically connected to the same first The reset line receives the same first reset signal Vref1; wherein the refresh rate of the display panel 100 in the nth frame is greater than the refresh rate in the (n+1)th frame, and in the nth frame, the first display area A1 and the second display area A2 both display images, and in the (n+1)th frame, the first display area A1 displays images and the second display area A2 is off, and n is a positive integer; the amplitude of the first reset signal in the nth frame includes the first sub-amplitude to the mth sub-amplitude corresponding to the first sub-display area to the mth sub-display area; wherein the first reset signal Vref The amplitude of 1 in the nth frame gradually decreases and is greater than the amplitude of the first reset signal Vref1 in the (n+1)th frame, that is, the first sub-amplitude to the mth sub-amplitude gradually decrease and are all greater than the amplitude of the first reset signal Vref1 in the (n+1)th frame; or, the amplitude of the first reset signal Vref1 in the nth frame gradually increases and is less than the amplitude of the first reset signal Vref1 in the (n+1)th frame, that is, the first sub-amplitude to the mth sub-amplitude gradually increase and are all less than the amplitude of the first reset signal Vref1 in the (n+1)th frame.

[0031] The display panel 100 may be, but is not limited to, a liquid crystal display panel or a self-luminous display panel. The latter is used as an example for illustration herein. The display panel 100 may include a display area A and a non-display area B surrounding the display area A. A first display area A1 may be a smaller area near the top edge, bottom edge, center, or other location within the display area A, used to display time information, icons, or other specific information. A larger area within the display area A, excluding the first display area A1, may be defined as a second display area A2.

[0032] Specifically, in this embodiment, in the nth frame, both the first display area A1 and the second display area A2 are controlled to display a picture, that is, a global picture display is performed, and in the (n+1)th frame, the first display area A1 is controlled to display a picture and the second display area A2 is turned off, that is, a non-global picture display is performed, which can be referred to as the AOD function of the display panel 100. Among them, when the global picture display is switched to turn on the AOD function, since the area for picture display only includes the smaller first display area A1, the requirements for picture quality are reduced. In order to reduce the power consumption of the display panel 100, in this embodiment, the refresh rate of the (n+1)th frame is set to be lower than the refresh rate in the nth frame.

[0033] Specifically, such as Figure 2 As shown, the driving transistor T1 in the pixel circuit 200 is used to generate a driving current according to the data signal Data to drive the light-emitting element Di to emit light, and before that, the first reset transistor T7 is used to reset one of the anode and cathode of the light-emitting element Di according to the first reset signal Vref1.

[0034] It should be noted that, since the AOD function is turned on, the larger second display area A2 is in an off state compared to the global screen display. It can be considered that the sub-pixels Pi in this area are affected by the data signal Data corresponding to the grayscale of 0. In order to make the brightness of the sub-pixels Pi in this area close to 0, the amplitude of the first reset signal Vref1 used to reset one of the anode and cathode of the light-emitting element Di can be set differently in the nth frame and the (n+1)th frame, so that the amplitude of the first reset signal Vref1 in the (n+1)th frame when the AOD function is turned on can achieve "over-" resetting of one of the anode and cathode, so as to increase the difficulty of the light-emitting element Di to emit light in the (n+1)th frame.

[0035] However, as shown in the schematic diagram of the mode switching of the comparative example in Table 1, if only the amplitude of the first reset signal Vref1 is set differently in the nth frame and the (n+1)th frame (for example, set to -0.4V and -2.5V respectively), then in the (n+1)th frame, the area above the second display area A2 near the display area A is scanned at a lower refresh rate (for example, 30Hz), resulting in the brightness of the sub-pixels Pi in the area below the display area A in the second display area A2 being maintained for a long time at a larger value corresponding to the combined effect of the amplitude of the first reset signal Vref1 and the non-zero grayscale data signal Data in the nth frame, resulting in the area below the display area A in the second display area A2 in the (n+1)th frame appearing to flicker.

[0036] Table 1

[0037]

[0038] It can be understood that, as shown in Table 2, the schematic diagram of the mode switching of the embodiment, in this embodiment, based on the differential setting of the amplitude of the first reset signal Vref1 in the n frame and the (n+1) frame, the amplitude of the first reset signal Vref1 in the n frame is set to gradually decrease and be greater than the amplitude in the (n+1) frame, or the amplitude of the first reset signal Vref1 in the n frame is gradually increased and less than the amplitude in the (n+1) frame. The former is taken as an example here, that is, the amplitude of the first reset signal Vref1 in the n frame is set to gradually change in the direction close to its amplitude in the (n+1) frame, so that the amplitude of the first reset signal Vref1 acting on the area below the display area A in the second display area A2 in the n frame is greater than that acting on the area below the display area A The amplitude of the first reset signal Vref1 in the upper area is closer to the amplitude of the first reset signal Vref1 in the (n+1)th frame, that is, the (i+1)th sub-amplitude in the nth frame is closer to the amplitude of the first reset signal Vref1 in the (n+1)th frame than the i-th sub-amplitude, where i is a positive integer from 1 to (m-1). Therefore, the brightness of the area below the display area A in the second display area A2 in the nth frame will be closer to its theoretical brightness close to 0 in the (n+1)th frame compared with the comparative example shown in Table 1. Ultimately, the brightness of the area below the display area A in the second display area A2 in the initial stage in the (n+1) frame will be reduced, thereby improving the flicker phenomenon of the area below the display area A in the second display area A2 in the (n+1) frame.

[0039] Table 2

[0040]

[0041] In some embodiments, in combination with Table 2 and Figure 3 As shown, the amplitude of the first reset signal Vref1 in the middle period t2 of the nth frame is between the amplitude of the start period t1 of the nth frame and the amplitude of the end period t3 of the nth frame. In combination with the above discussion, it can be seen that in this embodiment, at least the nth frame is divided into the start period t1, the middle period t2, and the end period t3, which are arranged in sequence, and the amplitude of the first reset signal Vref1 is sequentially increased or decreased in the three periods, so that the amplitude of the first reset signal Vref1 gradually changes in the nth frame toward its amplitude in the (n+1) frame.

[0042] Furthermore, the amplitude of the first reset signal Vref1 is different at each moment in at least one of the start period t1, the middle period t2, and the end period t3 of the nth frame. That is, the amplitude of the first reset signal Vref1 is constant in at least one of the above three periods in the nth frame, so that the at least one sub-display area a that is turned on at this time can be affected by the first reset signal Vref1 of the same amplitude.

[0043] It can be understood that if the number of change steps corresponding to the gradual change of the amplitude of the first reset signal Vref1 in the nth frame is greater, the number of sub-display areas a loaded with the first reset signal Vref1 with the same amplitude will be smaller, the number of groups that the multiple sub-display areas a can be divided into according to the differences in the amplitude of the loaded first reset signal Vref1 will be greater, and the brightness transition of the entire display area A in the nth frame will be smoother.

[0044] In some embodiments, combined Figures 1 to 2 , Table 2 to Figure 3 As shown, the sizes of the multiple sub-display areas a are equal, that is, the sizes of the first sub-display area to the mth sub-display area are equal, and the amplitude of the first reset signal Vref1 when each sub-pixel Pi in the same sub-display area a is equal during the nth frame when it is turned on. That is, each of the first sub-amplitude to the mth sub-amplitude has the same value when the corresponding multiple sub-pixels are turned on. It can be understood that in this embodiment, the number of rows of sub-pixels Pi in each sub-display area a is equal, and the amplitude of the first reset signal Vref1 is the same during the period when multiple rows of sub-pixels Pi in the same sub-display area a are turned on, so that the brightness of the display area A can be gradually increased or decreased according to the distribution of the multiple sub-display areas a.

[0045] Further, combined Figures 1 to 2 , Table 2 to Figure 3 As shown, the absolute value of the difference in amplitude of the first reset signal Vref1 when the multiple sub-pixels Pi in each adjacent sub-display area a are turned on is equal to the first preset difference, that is, the first sub-amplitude to the m-th sub-amplitude are an arithmetic progression. Specifically, the amplitude of the first reset signal Vref1 increases or decreases in an arithmetic progression according to the distribution of the multiple sub-display areas a. When the multiple sub-pixels Pi in each next sub-display area a are turned on, the amplitude of the first reset signal Vref1 increases or decreases by the first preset difference, so that the amplitude of the first reset signal Vref1 changes uniformly in steps within the nth frame, thereby further achieving that the display area A can uniformly increase or decrease the brightness according to the distribution of the multiple sub-display areas a.

[0046] like Figure 3As shown, the frame start signal TE includes a front blanking period VBP, a display period Vactive and a rear blanking period VFP arranged in sequence in each frame; wherein, the non-display area B of the display panel 100 may be provided with a plurality of rows of first virtual sub-pixels (for example, 32H, i.e., 32 rows) located above the plurality of rows of sub-pixels Pi, and a plurality of rows of second virtual sub-pixels (for example, 96H, i.e., 96 rows) located below the plurality of rows of sub-pixels Pi (for example, 3200H, i.e., 3200 rows), and the row synchronization signal Hsync includes a plurality of pulses corresponding to the plurality of rows of first virtual sub-pixels, the plurality of rows of sub-pixels Pi, and the plurality of rows of second virtual sub-pixels, and each pulse may be used to control the output of the source driver. The data signal Data output is the corresponding data voltage; wherein, the multiple pulses of the line synchronization signal Hsync in the front blanking period VBP are used to control the data voltage in the data signal Data to be an invalid data voltage to drive the brightness of multiple rows of first virtual sub-pixels to 0, the multiple pulses of the line synchronization signal Hsync in the rear blanking period VFP are used to control the data voltage in the data signal Data to be an invalid data voltage to drive the brightness of multiple rows of second virtual sub-pixels to 0, and the multiple pulses of the line synchronization signal Hsync in the display period Vactive are used to control the data voltage in the data signal Data to be a valid data voltage to drive multiple rows of sub-pixels Pi to emit light.

[0047] For example, combining Figures 1 to 2 , Table 2 to Figure 3As shown, taking the number of sub-display areas a as 5 as an example, the intermediate period t2 may include a first intermediate period t21, a second intermediate period t22, and a third intermediate period t23, and the amplitude of the first reset signal Vref1 in the nth frame is respectively 5 values ​​corresponding to the 5 sub-display areas a arranged from top to bottom and increasing or decreasing in sequence, that is, the amplitude of the first reset signal Vref1 in the starting period t1, the first intermediate period t21, the second intermediate period t22, the third intermediate period t23 and the ending period t3 are respectively 5 values ​​increasing or decreasing in sequence (for example, the above-mentioned m is 5, the multiple sub-display areas a include the 1st sub-display area to the 5th sub-display area, and the amplitude of the first reset signal in the nth frame includes the 1st sub-amplitude to the 5th sub-amplitude corresponding to the 1st sub-display area to the mth sub-display area), wherein the starting period t1 may be corresponding to the multiple rows The time periods in which the multiple pulses of the first virtual sub-pixel and the first sub-display area a are located, the first intermediate time period t21, the second intermediate time period t22, and the third intermediate time period t23 can be the time periods corresponding to the multiple pulses of the second, third, and fourth sub-display areas a, respectively, and the end time period t3 can be the time period corresponding to the multiple rows of second virtual sub-pixels and the fourth sub-display area a, so that the timing can be started from the starting point of the front blanking period VBP of the frame start signal TE by, for example, a timer, so as to adjust the amplitude of the first reset signal Vref1 when the first time length Hsync1, the second time length Hsync2, the third time length Hsync3, and the fourth time length Hsync4 are respectively passed in the nth frame, so that the amplitude of the first reset signal Vref1 is 5 values ​​that increase or decrease in sequence in the nth frame.

[0048] In some embodiments, different from Table 2 and Figure 3 In the embodiment shown, the refresh rate of the display panel 100 in the (ni)th frame to the nth frame is greater than the refresh rate in the (n+1)th frame, and i is a positive integer greater than 0 and less than n; wherein, the amplitude of the first reset signal Vref1 in the (ni)th frame to the nth frame gradually decreases and is greater than the amplitude of the first reset signal in the (n+1)th frame; or, the amplitude of the first reset signal Vref1 in the (ni)th frame to the nth frame gradually increases and is less than the amplitude of the first reset signal Vref1 in the (n+1)th frame.

[0049] Specifically, this embodiment not only sets the amplitude of the first reset signal Vref1 to gradually approach its amplitude in the (n+1)th frame in the nth frame, but also, on this basis, gradually approaches the amplitude of the first reset signal Vref1 in multiple frames from the (ni)th frame to the nth frame. The amplitude of the first reset signal Vref1 is set differently in at least one frame before the nth frame, which increases the number of frames occupied by gradually reducing or increasing the amplitude of the first reset signal Vref1, slows down the speed of change of the amplitude of the first reset signal Vref1, and further reduces the smoothness of the brightness transition of the entire display area A in multiple frames.

[0050] Wherein, refer to Table 2 and Figure 3 From the discussion above, it can be seen that the amplitude of the first reset signal Vref1 at the start period of the (ni)th frame and the amplitude at the end period of the nth frame can be used as the upper limit and lower limit of the amplitude of the first reset signal Vref1 within the range from the (ni)th frame to the nth frame.

[0051] Furthermore, the absolute value of the difference between the amplitudes of the first reset signal Vref1 between each adjacent frame from the (ni)th frame to the nth frame is equal to the second preset difference, that is, the absolute value of the difference between the amplitudes of each adjacent frame is equal. The amplitude of the first reset signal Vref1 in each of the (ni)th frame to the nth frame can be understood as the average, median or mode of the values ​​in the frame, that is, the amplitude of the first reset signal Vref1 increases or decreases in an arithmetic progression from the (ni)th frame to the nth frame, and in each next frame, the amplitude of the first reset signal Vref1 increases or decreases by the second preset difference, so that the amplitude of the first reset signal Vref1 changes uniformly in steps from the (ni)th frame to the nth frame, so as to further achieve that the brightness of the display area A can be uniformly increased or decreased in multiple frames.

[0052] In some embodiments, combined Figures 1 to 2 、 Figure 3 As shown, the pixel circuit 200 also includes: a second reset transistor T4, electrically connected to the gate G of the driving transistor T1, for resetting the gate G of the driving transistor T1 according to a second reset signal Vref2; wherein the amplitude of the second reset signal Vref2 in the nth frame gradually decreases and is greater than the amplitude of the second reset signal in the (n+1)th frame; or, the amplitude of the second reset signal in the nth frame gradually increases and is less than the amplitude of the second reset signal in the (n+1)th frame.

[0053] Among them, since the potential of the gate G of the driving transistor T1 affects the magnitude of the above-mentioned driving current and thus affects the brightness of the light-emitting element Di, and before this, the potential of the gate G of the driving transistor T1 is reset by the second reset signal Vref2, therefore, on the basis of the above-mentioned setting of the first reset signal Vref1, the amplitude of the second reset signal Vref2 that determines the brightness of the light-emitting element Di in the nth frame and the (n+1)th frame are also set differently, and the amplitude of the second reset signal Vref2 in the nth frame is set to gradually decrease and be greater than the amplitude in the (n+1) frame, or the amplitude of the second reset signal Vref2 in the nth frame is set to gradually increase and be less than the amplitude in the (n+1) frame. This can be combined with the above-mentioned setting of the amplitude of the first reset signal Vref1 to improve the flicker phenomenon in the area below the display area A in the second display area A2 within the (n+1) frame.

[0054] In some embodiments, combined Figures 1 to 2 、 Figure 4 As shown, the display panel 100 further includes: a first power line connected to one of the source S and the drain D of the driving transistor T1 (the former is used as an example here for description), and is used to transmit a first power signal VDD to one of the source S and the drain D of the driving transistor T1; a second power line connected to the other of the anode and the cathode of the light-emitting element Di (the latter is used as an example here for description), and is used to transmit a second power signal VSS to the other of the anode and the cathode of the light-emitting element Di; wherein the amplitude of the first power signal VDD gradually decreases in the nth frame. Decreases and is greater than the amplitude of the first power signal VDD in the (n+1)th frame; or, the amplitude of the first power signal VDD in the nth frame gradually increases and is less than the amplitude of the first power signal VDD in the (n+1)th frame; or, the amplitude of the second power signal VSS in the nth frame gradually decreases and is greater than the amplitude of the second power signal VSS in the (n+1)th frame; or, the amplitude of the second power signal VSS in the nth frame gradually increases and is less than the amplitude of the second power signal VSS in the (n+1)th frame.

[0055] The first power signal VDD affects the potential of the source S of the driving transistor T1, thereby affecting the magnitude of the driving current, and the second power signal VSS affects the potential of the cathode of the light-emitting element Di, thereby affecting the difficulty of the light-emitting element Di being turned on and affecting the time when it emits light.

[0056] Similarly, regarding the setting method of the amplitude of the first reset signal Vref1 and the amplitude of the second reset signal Vref2 mentioned above, in this embodiment, the amplitude of at least one of the first power supply signal VDD and the second power supply signal VSS that affect the brightness of the light-emitting element Di is also set differently in the n frame and the (n+1) frame, and is further set in the n frame to gradually approach its value in the (n+1) frame, so as to avoid a sudden change in its amplitude when switching from the n frame to the (n+1) frame, thereby improving the flickering phenomenon in the area below the display area A in the second display area A2 within the (n+1) frame.

[0057] In some embodiments, combined Figures 1 to 2 、 Figure 4 As shown, here, taking the n-th row of sub-pixels Pi as an example, the gate of the first reset transistor T7 is electrically connected to the first gate line, and the first gate pulse in the first gate signal Scan(n-1) transmitted by the first gate line is used to control the first reset transistor T7 to be turned on; wherein, the amplitudes of the multiple first gate pulses corresponding to the multiple sub-display areas a turned on in sequence within one frame gradually decrease in the n-th frame and are greater than the amplitudes of the multiple first gate pulses in the (n+1)-th frame, that is, the m types of the first gate pulses corresponding to the 1st sub-display area to the m-th sub-display area The amplitude of the first gate pulse in the nth frame gradually decreases and is greater than the amplitudes of the m types of the first gate pulse in the (n+1)th frame; or, the amplitudes of the multiple types of the first gate pulses corresponding to the multiple sub-display areas a that are sequentially turned on in one frame gradually increase in the nth frame and are less than the amplitudes of the multiple types of the first gate pulses in the (n+1)th frame, that is, the amplitudes of the m types of the first gate pulses corresponding to the 1st sub-display area to the mth sub-display area gradually increase in the nth frame and are less than the amplitudes of the m types of the first gate pulses in the (n+1)th frame.

[0058] Among them, the first gate pulse in the first gate signal Scan(n-1) is used to control whether the first reset transistor T7 is turned on. Furthermore, the amplitude of the first gate pulse can control the conduction degree of the first reset transistor T7, thereby affecting the effect of the first reset signal Vref1 being transmitted to the anode of the light-emitting element Di, and then affecting the potential of the anode of the light-emitting element Di, and also affecting the difficulty of the light-emitting element Di being turned on, thereby affecting the early or late moment of its light emission.

[0059] It can be understood that since the brightness of each row of sub-pixels Pi is controlled by the amplitude of the first gate pulse in the first gate signal Scan(n-1) of the corresponding level, this embodiment differentiates the amplitudes of the multiple first gate pulses acting on the multiple sub-display areas a that are turned on in sequence in the nth frame and the (n+1)th frame, and in the nth frame, it is also set to gradually approach its value in the (n+1)th frame, thereby avoiding the sudden change in amplitude when switching from the nth frame to the (n+1)th frame, thereby improving the flickering phenomenon in the area below the display area A in the second display area A2 in the (n+1) frame.

[0060] Specifically, such as Figure 2 As shown, the pixel circuit 200 also includes a compensation transistor T3 electrically connected between the gate G and the drain D of the driving transistor T1, a data writing transistor T2 electrically connected to the source S of the driving transistor T1, a first switching transistor T5 electrically connected between the source S of the driving transistor T1 and the first power line, a second switching transistor T6 electrically connected between the drain D of the driving transistor T1 and the light-emitting element Di, and a capacitor C1 electrically connected between the gate G of the driving transistor T1 and the first power line.

[0061] Among them, taking the nth row sub-pixel Pi as an example, the gate of the compensation transistor T3 and the gate of the data writing transistor T2 are both loaded with the first type of gate signal of this level (here referred to as the second gate signal Scan(n)), the gate of the second reset transistor T4 and the gate of the first reset transistor T7 are both loaded with the first type of gate signal of the previous level (that is, the above-mentioned first gate signal Scan(n-1)), and the gate of the first switching transistor T5 and the gate of the second switching transistor T6 are both loaded with the second type of gate signal (here referred to as the third gate signal EM(n)).

[0062] Combine Figure 2 and Figure 5 As shown, here, taking the above transistors as P-type transistors as an example, the pixel circuit 200 may include but is not limited to the following working stages:

[0063] In phase 1, the first gate signal Scan(n-1) is at a corresponding low level, the second reset transistor T4 and the first reset transistor T7 are both turned on, the second reset signal Vref2 is transmitted to the gate G of the driving transistor T1 to reset it, and simultaneously the capacitor C1 is charged in combination with the first power supply signal VDD. The first reset signal Vref1 is transmitted to the anode of the light-emitting element Di to reset it;

[0064] In the second stage, the second gate signal Scan(n) is at a corresponding low potential, the compensation transistor T3 and the data writing transistor T2 are both turned on, the data signal Data is transmitted to the source S of the driving transistor T1, and the gate G and drain D of the driving transistor T1 are short-circuited to form a diode structure to charge the gate G of the driving transistor T1 until its potential reaches (Vdate+Vth), at which point the driving transistor T1 is turned off.

[0065] In phase three, the third gate signal EM(n) is at a corresponding low potential, the first switch transistor T5 and the second switch transistor T6 are both turned on to form a path between the first power line and the second power line, and the driving transistor T1 is turned on to conduct the driving current to drive the light-emitting element Di to emit light.

[0066] Combined with the above discussion, it can be seen that the second gate signal Scan(n) can also control the conductivity of the data writing transistor T2 and the compensation transistor T3, and the third gate signal EM(n) can also control the conductivity of the first switching transistor T5 and the second switching transistor T6. All of the above will affect at least one of the potentials of the gate G, source S, and drain D of the driving transistor T1.

[0067] Therefore, in addition to the above-mentioned first reset signal Vref1, second reset signal Vref2, first power signal VDD, second power signal VSS and first gate signal Scan(n-1), the second gate signal Scan(n) and the third gate signal EM(n) can also be set as above.

[0068] It should be noted that the first gate signal Scan(n-1), the second gate signal Scan(n), and the third gate signal EM(n) can be generated by the gate driver according to the third voltage signal VGH and the fourth voltage signal VGL, or the clock signal can be generated by the voltage conversion circuit according to the third voltage signal VGH and the fourth voltage signal VGL, and then generated by the gate driver according to the clock signal, that is, Figure 4 As shown, by differentially setting the amplitude of the third voltage signal VGH and the amplitude of the fourth voltage signal VGL in the nth frame and the (n+1)th frame, and further setting them in the nth frame to gradually approach their values ​​in the (n+1)th frame, thereby avoiding a sudden change in amplitude when switching from the nth frame to the (n+1)th frame, the amplitude of at least one of the first gate signal Scan(n-1), the second gate signal Scan(n), and the third gate signal EM(n) can be controlled to achieve the above-mentioned setting, thereby improving the flickering phenomenon in the area below the display area A in the second display area A2 within the (n+1) frame.

[0069] The present invention also provides a display panel, Figure 1 and Figure 2 As shown, the display panel 100 has a display area A, the display area A includes a first display area A1 and a second display area A2 located at least below the first display area A1, the display area A includes a plurality of sub-display areas a, and the sub-pixels Pi in the plurality of sub-display areas a are sequentially turned on in one frame; wherein, the refresh rate of the display panel 100 in the nth frame is greater than the refresh rate in the (n+1)th frame, in the nth frame, the first display area A1 and the second display area A2 both display images, in the (n+1)th frame, the first display area A1 displays images and the second display area A2 is off, and n is a positive integer; in the nth frame, the sub-pixels Pi are sequentially turned on The sub-pixels Pi in the multiple sub-display areas a that are turned on are controlled by multiple first driving signals (for example, at least one of the above-mentioned first reset signal Vref1, second reset signal Vref2, first power signal VDD, second power signal VSS, first gate signal Scan(n-1), second gate signal Scan(n), and third gate signal EM(n)) whose amplitudes decrease or increase successively, and in the (n+1)th frame, the sub-pixels Pi in the multiple sub-display areas a are controlled by the same second driving signal (the type is the same as the first driving signal) whose amplitude is smaller than or greater than the multiple first driving signals.

[0070] In combination with the above discussion, it can be seen that this embodiment does not limit the voltage specifically referred to by the first driving signal acting on the sub-pixel Pi, that is, it can be any of the signals mentioned above. The focus of this embodiment is to only limit the multiple first driving signals corresponding to the multiple sub-display areas a that are turned on in sequence, and their corresponding multiple amplitudes decrease or increase in sequence in the nth frame, and gradually approach the amplitudes of the multiple second driving signals in the (n+1)th frame. Here, it is considered that the amplitudes of the multiple first driving signals in the (n+1)th frame are the same and are constant.

[0071] The present invention also provides a method for driving a display panel, such as Figure 6 As shown, the method includes but is not limited to the following steps and combinations of the following steps.

[0072] S1, receiving a display mode switching instruction for switching the display panel from a first display mode to a second display mode, wherein a refresh frequency of the first display mode is higher than a refresh frequency of the second display mode.

[0073] Combined with the above discussion, we can see that Figure 1As shown in Table 2, the first display mode and the second display mode here can be the above-mentioned global screen display mode and the mode of turning on the AOD function, that is, in the first display mode, both the first display area A1 and the second display area A2 display the screen, and in the second display mode, only the first display area A1 displays the screen and the second display area A2 is off (the sub-pixel Pi in this area is still turned on but is affected by the data signal Data corresponding to the grayscale 0), and since the latter does not display the screen globally, the refresh rate can be set lower.

[0074] S2, within a preset number of frames after receiving the display mode switching instruction, maintaining the refresh rate of the display panel at the refresh frequency of the first display mode, and applying driving voltage signals with successively increasing or decreasing amplitudes to the sub-pixels of multiple areas of the display panel that are sequentially turned on.

[0075] Combine Figure 1 As shown in Table 2, for example, when a display mode switching instruction is received in the (n-1)th frame, the refresh rate of the display panel 100 is maintained at the higher refresh frequency of the first display mode in the nth frame, and the amplitudes of the multiple first driving voltage signals acting on the multiple sub-display areas a (that is, different areas of the display panel 100 here) are differentiated and gradually approached to their amplitudes in the second display mode.

[0076] S3, after the preset number of frames, controlling the display panel to display images in the second display mode, and controlling the amplitude of the driving voltage signal to be greater than or less than the amplitude of the driving voltage signal within the preset number of frames.

[0077] It can be understood that after receiving the display mode switching instruction in the (n-1)th frame, the present invention does not immediately switch to the second display mode and directly switch the amplitude of the first driving voltage signal, but maintains the refresh rate of the display panel 100 at the refresh frequency of the first display mode within a preset number of frames (taking 1 frame as an example here) after the (n-1)th frame, and differentiates the multiple first driving voltage signals within the preset number of frames, so that the multiple sub-display areas a from top to bottom are acted upon by the first driving voltage signal with an amplitude that increases or decreases in sequence and is close to its amplitude in the second display mode. Finally, in the first frame of the second display mode (for example, the (n+1) frame), the brightness of the area below the display area A in the initial second display area A2 will be reduced, thereby improving the flickering phenomenon of the area below the display area A in the second display area A2 within the (n+1) frame.

[0078] Of course, after step S3, combined with Figure 1As shown in Table 2, when the instruction to exit the second display mode is received, the amplitude of the first driving voltage signal can be maintained equal to its amplitude in the second display mode within the current frame, and the refresh rate of the display panel can be maintained at the refresh frequency of the second display mode. At the beginning of the next frame, the amplitude of the first driving voltage signal becomes equal to its amplitude in the first display mode, and the refresh rate of the display panel becomes the larger refresh frequency of the first display mode.

[0079] The above is a detailed introduction to the structure of the display panel and its driving method provided in the embodiments of the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: The display area of ​​the display panel includes a first display area and a second display area at least below the first display area, the display area is divided into a first sub-display area to an m-th sub-display area, and sub-pixels in the first sub-display area to the m-th sub-display area are sequentially turned on within one frame, where m is a positive integer greater than 1; The sub-pixel includes a pixel circuit and a light-emitting element that are electrically connected, and the pixel circuit includes: a driving transistor electrically connected to the light emitting element and configured to generate a driving current according to a data signal to drive the light emitting element to emit light; a first reset transistor electrically connected to the light-emitting element, configured to reset one of an anode and a cathode of the light-emitting element according to a first reset signal, wherein the sub-pixels in the first to m-th sub-display areas all receive the same first reset signal; The refresh rate of the display panel in the nth frame is greater than the refresh rate in the (n+1)th frame, the first display area and the second display area both display images in the nth frame, and the first display area displays images and the second display area is turned off in the (n+1)th frame, where n is a positive integer; The amplitude of the first reset signal in the nth frame includes a first sub-amplitude to an mth sub-amplitude corresponding to the first sub-display area to the mth sub-display area; The first sub-amplitude to the mth sub-amplitude gradually decrease and are all greater than the amplitude of the first reset signal in the (n+1)th frame; Alternatively, the first sub-amplitude to the mth sub-amplitude gradually increase and are all smaller than the amplitude of the first reset signal in the (n+1)th frame.

2. The display panel according to claim 1, wherein The amplitude of the first reset signal in the middle period of the nth frame is between the amplitude of the start period of the nth frame and the amplitude of the end period of the nth frame.

3. The display panel according to claim 2, wherein: The amplitude of the first reset signal at each moment in at least one of a start period, a middle period, and an end period in the nth frame is different.

4. The display panel according to claim 1, wherein: The sizes of the first sub-display area to the mth sub-display area are equal, and each of the first sub-amplitude to the mth sub-amplitude has the same value when the corresponding plurality of sub-pixels are turned on.

5. The display panel according to claim 4, wherein: The first sub-amplitude to the mth sub-amplitude are an arithmetic progression.

6. The display panel according to claim 1, wherein: The refresh rate of the display panel from the ni frame to the nth frame is greater than the refresh rate of the n+1th frame, where i is a positive integer greater than 0 and less than n; The amplitude of the first reset signal gradually decreases from the ni-th frame to the n-th frame and is greater than the amplitude of the first reset signal in the n+1-th frame; Alternatively, the amplitude of the first reset signal from the ni-th frame to the n-th frame gradually increases and is smaller than the amplitude of the first reset signal in the (n+1)-th frame.

7. The display panel according to claim 6, wherein: The absolute values ​​of the differences between the amplitudes of the first reset signal in each adjacent frame from the ni-th frame to the n-th frame are all equal.

8. The display panel according to any one of claims 1 to 7, wherein: The pixel circuit further includes: a second reset transistor electrically connected to the gate of the driving transistor, and configured to reset the gate of the driving transistor according to a second reset signal; wherein the amplitude of the second reset signal in the nth frame gradually decreases and is greater than the amplitude of the second reset signal in the (n+1)th frame; Alternatively, the amplitude of the second reset signal in the nth frame gradually increases and is smaller than the amplitude of the second reset signal in the (n+1)th frame.

9. The display panel according to any one of claims 1 to 7, wherein: The display panel further includes: a first power line connected to one of the source and the drain of the driving transistor, and configured to transmit a first power signal to one of the source and the drain of the driving transistor; a second power line connected to the other of the anode and the cathode of the light-emitting element, for transmitting a second power signal to the other of the anode and the cathode of the light-emitting element; The amplitude of the first power signal in the nth frame gradually decreases and is greater than the amplitude of the first power signal in the (n+1)th frame; Alternatively, the amplitude of the first power signal in the nth frame gradually increases and is smaller than the amplitude of the first power signal in the (n+1)th frame; Alternatively, the amplitude of the second power signal in the nth frame gradually decreases and is greater than the amplitude of the second power signal in the (n+1)th frame; Alternatively, the amplitude of the second power signal in the nth frame gradually increases and is smaller than the amplitude of the second power signal in the (n+1)th frame.

10. The display panel according to any one of claims 1 to 7, wherein: The gate of the first reset transistor is electrically connected to a first gate line, and a first gate pulse in a first gate signal transmitted by the first gate line is used to control the first reset transistor to be turned on; The amplitudes of the m types of the first gate pulses corresponding to the first sub-display area to the m-th sub-display area in the n-th frame gradually decrease and are all greater than the amplitudes of the m types of the first gate pulses in the (n+1)-th frame; Alternatively, the amplitudes of the m types of the first gate pulses corresponding to the 1st sub-display area to the mth sub-display area in the nth frame gradually increase and are all smaller than the amplitudes of the m types of the first gate pulses in the (n+1)th frame.

11. A display panel, characterized in that: The display area of ​​the display panel includes a first display area and a second display area at least below the first display area, the display area is divided into a first sub-display area to an m-th sub-display area, and sub-pixels in the first sub-display area to the m-th sub-display area are sequentially turned on within one frame, where m is a positive integer greater than 1; The refresh rate of the display panel in the nth frame is greater than the refresh rate in the (n+1)th frame, the first display area and the second display area both display images in the nth frame, and the first display area displays images and the second display area is turned off in the (n+1)th frame, where n is a positive integer; In the nth frame, the sub-pixels in the first to the mth sub-display areas are controlled by m first driving signals having successively decreasing amplitudes, and in the (n+1)th frame, the sub-pixels in the first to the mth sub-display areas are all controlled by the same second driving signal having an amplitude smaller than the plurality of the first driving signals; Alternatively, in the nth frame, the sub-pixels in the first sub-display area to the mth sub-display area are controlled by m third driving signals with successively increasing amplitudes, and in the n+1th frame, the sub-pixels in the first sub-display area to the mth sub-display area are all controlled by the same fourth driving signal with an amplitude greater than multiple of the first driving signals.

12. A method for driving a display panel, characterized in that: The method comprises: receiving a display mode switching instruction for switching the display panel from a first display mode to a second display mode, wherein a refresh frequency of the first display mode is higher than a refresh frequency of the second display mode; maintaining the refresh rate of the display panel at the refresh rate of the first display mode within a preset number of frames after receiving the display mode switching instruction, and applying driving voltage signals with successively increasing or decreasing amplitudes to the sub-pixels of the plurality of sequentially turned-on regions of the display panel; After the preset number of frames, the display panel is controlled to display images in the second display mode, and within the preset number of frames, if the amplitudes of the driving voltage signals applied by the sub-pixels of the multiple areas of the display panel that are sequentially turned on increase sequentially, then after the preset number of frames, the amplitude of the driving voltage signal is controlled to be greater than the amplitude within the preset number of frames; if the amplitudes of the driving voltage signals applied by the sub-pixels of the multiple areas of the display panel that are sequentially turned on decrease sequentially, then after the preset number of frames, the amplitude of the driving voltage signal is controlled to be less than the amplitude within the preset number of frames.

Images