Memory built-in self-test method, controller and circuit

Abstract

The invention provides a memory built-in self-test method, a controller and a circuit, and relates to the technical field of memory testing, and the test method comprises the following steps: S1, starting to write 0 in an ascending order from the lowest address; s2, reading 0 for the lowest address, and then writing 1 and reading 1 in an ascending order; s3, reading 1 for the lowest address, and then writing 0 and reading 0 in an ascending order; s4, reading 0 for the lowest address, and then writing 1 in an ascending order; s5, reading 1 for the highest address, and then writing 0 and reading 0 in a descending order; s6, reading 0 for the lowest address, and then writing 0 in an ascending order; s7, reading 0 for the highest address, and then writing 1 and reading 1 in a descending order; and S8, reading 1 from the lowest address in an ascending order. The invention also provides a memory built-in self-test controller and a memory built-in self-test circuit. Based on the newly proposed March-E algorithm, the test speed and the fault coverage rate can be improved and the power consumption can be reduced with relatively low area overhead.

Description

Technical Field

[0001] The present invention relates to the technical field of memory testing, and in particular to a memory built-in self-test method, a controller and a circuit. Background Art

[0002] In modern SOC based designs, embedded memory occupies a large portion of the area. Hence, as the memory density increases, the need for fast self-test plays a vital role in SOC devices.

[0003] With the continuous increase of integrated circuit scale and the expansion of memory capacity, traditional test methods are becoming increasingly unfeasible because they require a lot of time and resources. Therefore, the MBIST method came into being. The MBIST method is the mainstream technology for large-capacity memory testing at present. This technology uses the BIST circuit specially designed inside the chip to perform automated testing, and can perform comprehensive testing on embedded modules such as embedded memory with complex circuit structures. The MBIST circuit places the circuit module that generates the test vector and the comparison module that detects the test result inside the chip. After the test is completed, the test result is sent to the outside of the chip through the test pins of the chip.

[0004] March algorithm is a series of algorithms. Because of its high fault coverage and short test time, it has been widely studied and applied in the MBIST field. This type of algorithm has been widely used in the testing of large-capacity SRAM and DRAM. Its basic idea is to traverse each storage unit under the control of a finite state machine and perform a series of operations on each storage unit. Before operating the next storage unit, these operations on the current unit are called March elements. Each March element has a specified address ascending and descending order. When a storage unit completes a series of operations, the next storage unit to perform the operation is determined according to the address ascending and descending order. When a March element completes all operations on all storage units, the next March element is executed.

[0005] The differences between various March type algorithms are reflected in the March elements. With the deepening of research, various improved algorithms have also emerged. The current March algorithms mainly include March-A, March-B, March-C and other types. For example, March-C is a simple algorithm with 6 steps and 10 elements to perform memory test operations. Address sequences in both directions can calculate address decoder errors. The first three steps are used to calculate SA1 and SA0 faults, and the last three steps are used to calculate jump faults and some coupling faults. It is relatively simple and performs at most 2 operations on each storage location, so it cannot accurately detect coupling faults, such as stuck-open faults, which are caused by the inability to access the storage unit after the word line is opened. In order to detect this fault, there must be a step in the March algorithm to perform sequential read, write, read 1 or 0 operations. However, in the March-C algorithm, a step contains at most 2 elements, which cannot meet this condition. In addition, it only relies on the address sequence to calculate the address decoder fault. Summary of the invention

[0006] The purpose of the present invention is to propose a test method, a controller and a circuit for testing the memory of a SOC device, wherein the controller is called a memory built-in self-test controller (MBSIT). The test method and the controller are based on the March-E algorithm proposed in the present invention, which can improve the test speed, fault coverage and reduce power consumption with a lower area overhead. The algorithm can be easily integrated into the system-level chip design for detecting memory faults and their types.

[0007] The technical solution adopted by the present invention to achieve its invention object is a memory built-in self-test method, comprising the following steps performed in sequence on the memory to be tested:

[0008] Step S1, starting from the lowest address, write 0 operation in ascending order, i.e. ↑(w0);

[0009] Step S2, read 0 operation on the lowest address, then write 1 operation, read 1 operation on the address again, add 1 to the address after completion, write 1 and read 1 operation again, until the above operations are completed on the entire memory, that is, ↑(r0,w1,r1);

[0010] Step S3, read 1 operation on the lowest address, then write 0 operation, read 0 operation on the address again, add 1 to the address after completion, write 0 and read 0 operation again, until the above operations are completed on the entire memory, that is, ↑(r1,w0,r0);

[0011] Step S4, read 0 operation on the lowest address, then write 1 operation, after completion, the address is increased by 1, and write 1 operation is performed again until the above operations are performed on the entire memory, that is, ↑(r0,w1);

[0012] Step S5, read 1 operation on the highest address, then write 0 operation, read 0 operation on the address again, after completion, the address is reduced by 1, write 0 and read 0 operation are performed again, until the above operations are performed on the entire memory, that is, ↓(r1,w0,r0);

[0013] Step S6, perform a read 0 operation on the lowest address, then perform a write 0 operation, after completion, the address is incremented by 1, and the write 0 operation is performed again until the above operations are performed on the entire memory, that is, ↑(r0,w0);

[0014] Step S7, read 0 operation on the highest address, then write 1 operation, read 1 operation on the address again, after completion, the address is reduced by 1, write 1 and read 1 operation are performed again, until the above operations are performed on the entire memory, that is, ↓(r0,w1,r1);

[0015] Step S8, starting from the lowest address, read 1 operation in ascending order, i.e. ↑(r1).

[0016] The above test method is based on the March-E algorithm proposed by the present invention. The March-E algorithm includes the 8 operations mentioned above, namely ↑(w0), ↑(r0,w1,r1), ↑(r1,w0,r0), ↑(r0,w1), ↓(r1,w0,r0), ↑(r0,w0), ↓(r0,w1,r1);

[0017] Among them, ↑ indicates ascending order, ↓ indicates descending order, w0 indicates writing 0 to the storage cell, w1 indicates writing 1 to the storage cell, r0 indicates reading 0 from the storage cell, and r1 indicates reading 1 from the storage cell.

[0018] The March-E algorithm has a simple structure and is developed using the Verilog hardware description language. It can be easily integrated with SOCs and is used to determine the location and type of faults in semiconductor memories.

[0019] The present invention also provides a memory built-in self-test controller, comprising: a state machine, the state machine consists of ten states, wherein the first state is an initial state, that is, the initial state in which the state machine waits for a start signal to start running. The second to ninth states respectively execute the eight steps of the above-mentioned memory built-in self-test method, and the tenth state is a recording state, which records failure information when the memory to be tested fails.

[0020] The present invention also provides a memory built-in self-test circuit, comprising:

[0021] Memory to be tested;

[0022] The memory built-in self-test controller as described above is used to receive an external self-test enable signal, and initialize the self-test circuit under the action of the signal, and to provide a preset expected value to the comparator;

[0023] A read / write enable module, for generating a read / write enable signal under the control of a memory built-in self-test controller;

[0024] An address generation module, used to generate a memory address to be read or written under the control of a memory built-in self-test controller;

[0025] A data generator, for generating test vector data under the control of a memory built-in self-test controller; a test vector refers to a test operation on the memory;

[0026] A readout unit, used to perform a read operation on the memory to be tested under the control of the read-write enable signal, and output the readout data to a data register;

[0027] A data register, used to receive the test vector data output by the data generator under the control of the read / write enable signal, and output it to the write unit; and also used to output the read data received from the read unit to the comparator;

[0028] A write unit, used to perform a write operation on the memory to be tested according to the received test vector data under the control of the read / write enable signal;

[0029] The comparator is used to compare the read data with the expected value and output the comparison result to the memory built-in self-test controller.

[0030] The beneficial effects of the present invention are:

[0031] As mentioned above, the traditional March-C algorithm cannot identify certain fault types. The test method of the present invention is derived to overcome this limitation, but it will bring some area overhead.

[0032] In order to solve the problem that the fault coverage of the March-C algorithm is not comprehensive, the present invention provides an improved March-E algorithm, which increases the steps and elements by adding some other read and write operations. The MARCH-E algorithm has a total of 8 steps and 18 elements. The comparison of the number of operations and coverage of various March algorithms is shown in the following table:

[0033]

[0034] In the first three steps, all potential fixed-1 (SA1) and fixed-0 (SA0) faults can be found. Address decoding faults and transition faults can also be found by reading data from different memory locations through similar steps. In order to improve fault coverage, more steps can be used to detect the same problem. Coupling faults are errors that may appear in any location of the memory. These faults can be calculated by closely monitoring and repeated testing with three elements of steps. Therefore, at low power consumption, in the fastest possible test time, and through reasonable additional hardware, the test method based on the MARCH-E algorithm of the present invention improves fault coverage. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the steps of a memory built-in self-test method according to Embodiment 1 of the present invention;

[0036] Figure 2 This is a schematic diagram of a state machine of a memory built-in self-test controller according to Embodiment 2 of the present invention;

[0037] Figure 3 This is a schematic block diagram of the memory built-in self-test circuit structure according to Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0038] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] Example 1

[0040] Figure 1 A specific implementation of the memory built-in self-test method of the present invention is shown, comprising the following steps performed sequentially on the memory to be tested:

[0041] Step S1, starting from the lowest address, write 0 operation in ascending order, i.e. ↑(w0);

[0042] Step S2, read 0 operation on the lowest address, then write 1 operation, read 1 operation on the address again, add 1 to the address after completion, write 1 and read 1 operation again, until the above operations are completed on the entire memory, that is, ↑(r0,w1,r1);

[0043] Step S3, read 1 operation on the lowest address, then write 0 operation, read 0 operation on the address again, add 1 to the address after completion, write 0 and read 0 operation again, until the above operations are completed on the entire memory, that is, ↑(r1,w0,r0);

[0044] Step S4, read 0 operation on the lowest address, then write 1 operation, after completion, the address is increased by 1, and write 1 operation is performed again until the above operations are performed on the entire memory, that is, ↑(r0,w1);

[0045] Step S5, read 1 operation on the highest address, then write 0 operation, read 0 operation on the address again, after completion, the address is reduced by 1, write 0 and read 0 operation are performed again, until the above operations are performed on the entire memory, that is, ↓(r1,w0,r0);

[0046] Step S6, perform a read 0 operation on the lowest address, then perform a write 0 operation, after completion, the address is incremented by 1, and the write 0 operation is performed again until the above operations are performed on the entire memory, that is, ↑(r0,w0);

[0047] Step S7, read 0 operation on the highest address, then write 1 operation, read 1 operation on the address again, after completion, the address is reduced by 1, write 1 and read 1 operation are performed again, until the above operations are performed on the entire memory, that is, ↓(r0,w1,r1);

[0048] Step S8, starting from the lowest address, read 1 operation in ascending order, i.e. ↑(r1).

[0049] Example 2

[0050] Figure 2 A specific implementation of the memory built-in self-test controller of the present invention is shown, comprising: a state machine, the state machine consists of ten states, wherein the first state is the initial state, the second to the ninth state are Figure 1 P0 to P7 in the embodiment respectively execute the eight steps of the memory built-in self-test method of embodiment 1. The tenth state is a recording state, and the failure information is recorded when the memory to be tested fails.

[0051] The initial state is the initial state in which the state machine waits for the start signal to start running. After receiving the start signal, the state machine jumps to the P0 state and performs write 0 operations on all addresses one by one in ascending order of address. When the maximum address position is reached, the state machine jumps to the next state and performs the corresponding operation in the algorithm. When performing the test operation, if the read data does not match the expected value, the state machine will jump to the recording state and display all fault information such as the fault memory ID, fault address, and damaged unit. After displaying the fault information, the state machine will jump to the next memory address and repeat the same operation. Therefore, the above process will continue until the highest address of the memory location under test. Once the state machine has executed all operations from P0 to P7, it will jump to the recording state and display all information related to the memory location under test.

[0052] Example 3

[0053] Figure 3 A specific implementation of the memory built-in self-test circuit of the present invention is shown, comprising:

[0054] Memory to be tested;

[0055] The memory built-in self-test controller as described above is used to receive an external self-test enable signal, and initialize the self-test circuit under the action of the signal, and to provide a preset expected value to the comparator;

[0056] A read / write enable module, for generating a read / write enable signal under the control of a memory built-in self-test controller;

[0057] An address generation module, used to generate a memory address to be read or written under the control of a memory built-in self-test controller;

[0058] A data generator for generating test vector data under the control of a memory built-in self-test controller;

[0059] A readout unit, used to perform a read operation on the memory to be tested under the control of the read-write enable signal, and output the readout data to a data register;

[0060] A data register, used to receive the test vector data output by the data generator under the control of the read / write enable signal, and output it to the write unit; and also used to output the read data received from the read unit to the comparator;

[0061] A write unit, used to perform a write operation on the memory to be tested according to the received test vector data under the control of the read / write enable signal;

[0062] The comparator is used to compare the read data with the expected value and output the comparison result to the memory built-in self-test controller.

[0063] Each module is independently developed using Verilog and then verified separately. Finally, all modules are instantiated to test the memory under test.

[0064] In this embodiment, the address generation module needs to address the memory to be tested through the address latch module, the row decoding module and the column decoding module. The address latch module, the row decoding module and the column decoding module are all existing technologies and will not be described in detail here.

[0065] The principle of using the circuit of this embodiment for testing is:

[0066] First, the built-in self-test controller of the memory is the MBIST controller that receives the external self-test enable signal, under this signal effect, the self-test circuit is initialized, and according to the March-E test algorithm, the read-write enable, address, data signal are automatically generated and the memory to be tested is tested. The data read from the memory to be tested are sent to the comparator through the data register, and the expected value pre-set with the MBIST controller is compared, and the comparator can feedback to the MBIST controller whether to complete, whether the result is correct. When all tests are completed, the MBIST controller can export total test completion signal and test correct or not signal.

Claims

1. A memory built-in self-test method, characterized in that: The following steps are performed sequentially on the memory to be tested: Step S1, starting from the lowest address, write 0 operation in ascending order; Step S2, perform a read 0 operation on the lowest address, then perform a write 1 operation, perform a read 1 operation on the address again, after completion, add 1 to the address, perform write 1 and read 1 operations again, until the above operations are completed on the entire memory; Step S3, performing a read 1 operation on the lowest address, then performing a write 0 operation, performing a read 0 operation on the address again, after completion, adding 1 to the address, performing the write 0 and read 0 operations again, until the above operations are completed on the entire memory; Step S4, performing a read 0 operation on the lowest address, and then performing a write 1 operation, after completion, the address is incremented by 1, and the write 1 operation is performed again, until the above operations are performed on the entire memory; Step S5, performing a read 1 operation on the highest address, then performing a write 0 operation, performing a read 0 operation on the address again, after completion, the address is reduced by 1, and the write 0 and read 0 operations are performed again, until the above operations are performed on the entire memory; Step S6, performing a read 0 operation on the lowest address, and then performing a write 0 operation, after completion, the address is incremented by 1, and the write 0 operation is performed again, until the above operations are performed on the entire memory; Step S7, perform a read 0 operation on the highest address, then perform a write 1 operation, perform a read 1 operation on the address again, after completion, reduce the address by 1, perform the write 1 and read 1 operations again, until the above operations are completed on the entire memory; Step S8, starting from the lowest address, read 1 operations in ascending order.

2. A memory built-in self-test controller, characterized in that: The invention comprises a state machine, wherein the state machine is composed of ten states, wherein the first state is an initial state, the second to ninth states respectively execute eight steps of the memory built-in self-test method as claimed in claim 1, and the tenth state is a recording state, which records failure information when the memory to be tested fails.

3. A memory built-in self-test circuit, characterized in that: include: Memory to be tested; The memory built-in self-test controller as claimed in claim 2, which is used to receive an external self-test enable signal, and initialize the self-test circuit under the action of the signal, and is used to provide a preset expected value to the comparator; A read / write enable module, for generating a read / write enable signal under the control of a memory built-in self-test controller; An address generation module, used to generate a memory address to be read or written under the control of a memory built-in self-test controller; A data generator for generating test vector data under the control of a memory built-in self-test controller; A readout unit, used to perform a read operation on the memory to be tested under the control of the read-write enable signal, and output the readout data to a data register; A data register, used to receive the test vector data output by the data generator under the control of the read / write enable signal, and output it to the write unit; and also used to output the read data received from the read unit to the comparator; A write unit, used to perform a write operation on the memory to be tested according to the received test vector data under the control of the read / write enable signal; The comparator is used to compare the read data with the expected value and output the comparison result to the memory built-in self-test controller.

4. A memory built-in self-test circuit according to claim 3, characterized in that: The memory built-in self-test controller is also used to output the test result externally.

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