Memory function test system and method

Abstract

The invention discloses a memory function test system and method.The system comprises a chip temperature screening device, an upper computer and an environment box, the chip temperature screening device comprises a test bottom plate, the test bottom plate is divided into an interface area and a test area, and the test bottom plate is connected with a microcontroller through an interface in the interface area; a to-be-tested memory chip is connected with the test carrier plate in the test area in a spring crimping manner; the upper computer is used for generating a test instruction and sending the test instruction to the microcontroller, so that the microcontroller tests the memory chip to be tested in the test area; and the environment box is used for providing a temperature environment required for testing the memory chip. The temperature screening device and the environment box are adopted, read-write function testing of the memory chip at different temperatures can be met, the testing accuracy is improved, the testing carrier plate and the memory chip to be tested are in spring crimping connection, and the testing sensitivity and reliability are improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a memory function testing system and method. Background Art

[0002] The Automatic Train Protection (ATP) system is an important and key device in the high-speed railway train control system, which is related to the safety of train operation. In the ATP system, the Vehicle Control Unit (VCU) is a comprehensive processing unit with a powerful processor and memory, which can load software for different purposes to achieve different functions. The read and write performance of the VCU memory will directly affect the stability of the ATP system operation.

[0003] In order to ensure the stability of the ATP system operation, after obtaining the memory, it is necessary to test the read and write functions of the memory to screen the memory according to the test results. It can be seen that how to ensure the accuracy of the memory test results has become the main problem for the accurate application of the memory. Summary of the invention

[0004] In response to the above problems, the present application provides a memory function testing system and method, which achieves the purpose of improving the accuracy and reliability of memory chip testing.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A memory function test system comprises: a chip temperature screening device, a host computer and an environmental chamber, wherein the chip temperature screening device comprises a test base plate, the test base plate is divided into an interface area and a test area, a microcontroller is connected through an interface in the interface area, and a memory chip to be tested is connected to a test carrier in the test area by a spring pressing method;

[0007] The host computer is used to generate a test instruction and send the test instruction to the microcontroller, so that the microcontroller tests the memory chip to be tested in the test area;

[0008] The environmental box is used to provide the temperature environment required for memory chip testing.

[0009] Optionally, a power interface is further provided in the interface area, a power supply module is connected via the power interface, and power is supplied to the test area via the power supply module.

[0010] Optionally, the test carrier is divided into a flash memory chip test area and a dual-port memory chip test area.

[0011] Optionally, the flash memory type memory chip test area includes 64 slots, and the dual-port memory chip test area includes 4 slots.

[0012] Optionally, the host computer may be connected to four test boards, wherein the host computer may distinguish each of the test boards based on an address code corresponding to the test board.

[0013] Optionally, the test carrier board has a unified external interface.

[0014] A memory function test method is applied to a microcontroller in the memory function test system as described above, the method comprising:

[0015] In response to receiving a test instruction for a memory chip to be tested in a test area sent by a host computer, performing a read and write test on the memory chip to be tested based on the test instruction to obtain a test result;

[0016] The test result is output to the host computer.

[0017] Optionally, performing a read and write test on the memory chip to be tested based on the test instruction to obtain a test result includes:

[0018] Determining a test process based on the type of the memory chip to be tested in the test instruction;

[0019] Testing the memory chip to be tested based on the test process to obtain a test result;

[0020] Wherein, if the memory chip to be tested is a dual-port memory, the test process includes left-side data writing, left-side data reading, right-side data writing and right-side data reading;

[0021] If the storage chip to be tested is a flash memory chip, the test process includes full chip erasing, data writing, data reading and data verification.

[0022] Optionally, the testing the memory chip to be tested based on the test process to obtain a test result includes:

[0023] Parsing the test instruction, if the test instruction is an automatic loop test, sequentially testing each storage area of ​​the memory chip to be tested based on each test step in the test flow to obtain a test result;

[0024] If the test instruction is a single test, a target to-be-tested function corresponding to the to-be-tested memory chip is determined, and the target to-be-tested function is tested based on the test flow to obtain a test result of the target memory area.

[0025] Optionally, it also includes:

[0026] Based on the test process, generate test progress information;

[0027] The test progress information is sent to the host computer so that the host computer outputs the test progress information.

[0028] Compared with the prior art, the present application provides a memory function test system and method, which includes: a chip temperature screening device, a host computer and an environmental chamber, wherein the chip temperature screening device includes a test base plate, the test base plate is divided into an interface area and a test area, the microcontroller is connected through an interface in the interface area, and the memory chip to be tested is connected to the test carrier in the test area by spring compression; the host computer is used to generate test instructions and send the test instructions to the microcontroller so that the microcontroller tests the memory chip to be tested in the test area; the environmental chamber is used to provide the temperature environment required for the memory chip test. The present application uses a temperature screening device and an environmental chamber to meet the read and write function test of the memory chip at different temperatures, which improves the accuracy of the test, and the test carrier is connected to the memory chip to be tested by spring compression, which improves the test sensitivity and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0030] Figure 1 A schematic diagram of the structure of a memory function test system provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of a carrier board provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of a test base plate provided in an embodiment of the present application;

[0033] Figure 4 A schematic diagram of a CTST universal base plate provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of a flow chart of a memory function testing method provided in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of a display interface of a host computer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] The terms "first" and "second" and the like in the specification and claims of this application and the above drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0038] In order to facilitate the description of the embodiments of the present application, the relevant terms of the present application are now explained.

[0039] CTST:Chip Temperature Slect Tool chip temperature screening device;

[0040] ATP:Automatic Train Protection train automatic protection system;

[0041] VCU:Vehicle Control Unit

[0042] SOP 44: 44-Pin small Out-Line package 44-pin small outline package;

[0043] TSOP: Thin small Out-Line package;

[0044] TS 040: 40-Pin TSOP StandardPinout40-pin standard thin small outline package;

[0045] TS 048: 48-Pin TSOP StandardPinout40-pin standard thin small outline package;

[0046] TSR 040: 40-Pin TSOP Reverse Pinout 40-pin reverse outline thin small outline package;

[0047] TSR 048: 48-Pin TSOP Reverse Pinout 40-pin reverse outline thin small outline package;

[0048] TQFP 100: 100-pin Thin quad flatpackage 100-pin thin quad flat package;

[0049] Flash: Flash memory;

[0050] DPRAM: Dual Port Random Access Memory;

[0051] MCU: Microcontroller Unit microcontroller unit;

[0052] RAM: Random-access Memory;

[0053] Sector: Sector.

[0054] A memory function test system is provided in an embodiment of the present application. The system can perform high and low temperature temperature change specific memory function tests. In actual production application scenarios, it can verify whether the read and write performance of the memory chip at different temperatures meets application requirements.

[0055] See also Figure 1 , is a structural schematic diagram of a memory function test system provided in an embodiment of the present application, the system includes a chip temperature screening device 101, a host computer 102 and an environmental chamber 103, wherein the chip temperature screening device includes a test base plate, the test base plate is divided into an interface area and a test area, a microcontroller is connected through an interface in the interface area, and the memory chip to be tested is connected to the test carrier in the test area by spring crimping.

[0056] The host computer 102 is used to generate a test instruction and send the test instruction to the microcontroller, so that the microcontroller tests the memory chip to be tested in the test area;

[0057] The environmental box 103 is used to provide the temperature environment required for the memory chip test.

[0058] In the embodiment of the present application, the chip temperature screening tool (CTST) is implemented by using a design architecture of a dedicated test carrier (referred to as the dedicated carrier) and a universal test baseboard (referred to as the baseboard). After inserting different types of memory chips to be tested into the corresponding dedicated carrier, the pins of the memory chips of different types can be redistributed to the same external interface to achieve consistency in external electrical definitions. For example, see Figure 2 , the same external interface type and line sequence can use 2.0mm pins. After the carrier conversion, the external electrical interfaces of different chips are completely consistent, which greatly improves the scalability and compatibility of CTST. Specifically, the carriers include: TS040 carrier, TSR040 carrier, SO044 carrier and TQFP100 carrier.

[0059] In an embodiment of the present application, a power interface is also provided in the interface area, a power supply module is connected through the power interface, and power is supplied to the test area through the power supply module. Optionally, the test carrier is divided into a flash memory type memory chip test area and a dual-port memory chip test area. Among them, the flash memory type memory chip test area includes 64 slots, and the dual-port memory chip test area includes 4 slots. Further, the host computer can be connected to 4 test carriers, wherein the host computer can distinguish each of the test carriers based on the address code corresponding to the test carrier. The test carrier has a unified external interface.

[0060] See also Figure 3 , is a schematic diagram of a test baseboard provided in an embodiment of the present application. The test baseboard in the embodiment of the present application, i.e., the universal baseboard, is designed with 64+4 carrier board insertion slots, of which 64 slots can be inserted into any Flash carrier board, and 4 slots can be inserted into the DPRAM carrier board. There is an MCU controller on the universal baseboard, which is responsible for functional testing of all inserted chips. It should be noted that the Flash carrier board and the DPRAM carrier board are multiplexed due to the number of MCU hardware ports, and are configured with different programs for testing, so they cannot be inserted at the same time.

[0061] See also Figure 4 , which is a schematic diagram of a CTST universal baseboard provided in an embodiment of the present application. In the CTST test baseboard, 4 DPRAMs are used to form a group of 64-bit RAM memory. There are 4 groups of Flash and 1 group of RAM on a universal baseboard. The MCU uses GPIO to simulate the external bus to implement operations on Flash or RAM. Among them, each test unit needs to have independent power control, and the static current of each group of test units should be measurable. The communication between the MCU and the host computer is realized by a USB serial port bridge. An external 5V power supply is provided inside the board, and the current is not less than 2A. Address coding should be designed for the universal baseboard.

[0062] In the embodiment of the present application, a memory function test method is also provided, which can be applied to a microcontroller in a memory function test system. Figure 5 , the method may include the following steps:

[0063] S201, in response to receiving a test instruction for a memory chip to be tested in a test area sent by a host computer, performing a read and write test on the memory chip to be tested based on the test instruction to obtain a test result;

[0064] S202: Output the test result to the host computer.

[0065] In one implementation, performing a read and write test on the memory chip to be tested based on the test instruction to obtain a test result includes:

[0066] Determining a test process based on the type of the memory chip to be tested in the test instruction;

[0067] Testing the memory chip to be tested based on the test process to obtain a test result;

[0068] Wherein, if the memory chip to be tested is a dual-port memory, the test process includes left-side data writing, left-side data reading, right-side data writing and right-side data reading;

[0069] If the storage chip to be tested is a flash memory chip, the test process includes full chip erasing, data writing, data reading and data verification.

[0070] Optionally, the testing the memory chip to be tested based on the test process to obtain a test result includes:

[0071] Parsing the test instruction, if the test instruction is an automatic loop test, sequentially testing each storage area of ​​the memory chip to be tested based on each test step in the test flow to obtain a test result;

[0072] If the test instruction is a single test, a target to-be-tested function corresponding to the to-be-tested memory chip is determined, and the target to-be-tested function is tested based on the test flow to obtain a test result of the target memory area.

[0073] Optionally, it also includes:

[0074] Based on the test process, generate test progress information;

[0075] The test progress information is sent to the host computer so that the host computer outputs the test progress information.

[0076] For example, the process of executing the test flow through the microcontroller can execute the corresponding test flow based on the type of memory chip to be tested. The functional test of DPRAM includes: left data write, left data read, right data write, right data read. The functional test of Flash includes: full chip erase, data write, data read, data verification. The test options should support two modes: fast self-test test and automatic cycle test.

[0077] The test process can also be performed based on the test mode selected by the host computer. For example, a fast self-test test can be used. This mode is used for preliminary verification and can quickly determine whether the chip is inserted and configured correctly. The specific process may include: After the test environment is set up, the fast mode is selected from the host computer and instructions are issued. The instructions issued should include the number of the chipset to be tested. The MCU powers on the chipset to be tested, measures the static current, and then returns to the host computer. The MCU erases, writes 0xAA, and reads the address 0x155555, verifies the correctness of the data, and feeds back the results to the host computer. The MCU erases, writes 0x55, and reads the address 0x0AAAAA, verifies the correctness of the data, and feeds back the results to the host computer. The MCU powers off the chipset to be tested.

[0078] It can also include automatic cycle testing, which is used for functional verification. The specific process is as follows:

[0079] After the test environment passes the quick self-test, select the automatic mode from the host computer and issue instructions. The instructions issued should include the number of the chipset to be tested. MC powers on the chipset to be tested, measures the static current, and then returns to the host computer. MCU performs a sector erase operation on the Flash. After completion, the MCU should periodically feedback the status to the host computer. Write 0x55 to the sector address space one by one. After the writing is completed, the MCU will feedback the status to the host computer. Read the sector address space one by one and verify its correctness. After the verification is completed, the MCU should feedback the status to the host computer. Repeat the sector operation process until all sectors are tested. Execute the Flash test process again, but change the write data to 0xAA. After the writing of 0x55 and 0xAA is completed, the MCU powers off the chipset to be tested.

[0080] It can also include single test, which can test a single function. For example, read the baseboard number. Channel power on and off test. Erase Flash first area, write data 0xA5 / 0x5A to 0xA55A in Flash first area, read data from 0xA55A in Flash first area, erase the entire Flash, write data to all addresses in Flash first area, read data from all addresses in Flash first area. DPRAM test (same as above), print out the test results to the computer.

[0081] In the embodiment of the present application, the host computer connected to the chip temperature screening device (CTST) can be directly operated on the electronic device, and its interface is as follows: Figure 6 As shown. The same host computer can be connected to up to 4 test boards through the USB interface, and the test boards can be distinguished by setting address codes. Specifically, the host computer can run on a win 10 computer. Search for the connected universal board and read the board address code. You can arbitrarily select the combination of chipsets to be tested on the same universal board. For the automatic cycle test mode, you can manually set the number of cycles and test intervals. It has the function of real-time echo of universal board feedback information. It has the function of saving test records. For test abnormalities, obvious prompts should be given on the interface. Multiple host computer interfaces can be opened to meet the needs of testing multiple universal boards at the same time.

[0082] The chip temperature screening device used in the memory function test system of the embodiment of the present application can achieve high and low temperature screening, greatly improve product performance, and reduce the return rate. The test seat on the chip temperature screening device test carrier is a precision device, and the test carrier and the chip to be tested are connected by spring compression, which is sensitive to the test and has high reliability.

[0083] Based on the foregoing embodiments, embodiments of the present application provide a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any of the memory function testing methods above.

[0084] An embodiment of the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a memory function testing method when executing the program.

[0085] It should be noted that the above-mentioned processor or CPU can be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It can be understood that the electronic device that realizes the function of the above-mentioned processor can also be other, and the embodiments of the present application are not specifically limited.

[0086] It should be noted that the above-mentioned computer storage medium / memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM) and other memories; it can also be various terminals including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0087] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0088] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0089] In addition, all functional units in the embodiments of the present application can be integrated into one processing module, or each unit can be a separate unit, or two or more units can be integrated into one unit; the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units. A person of ordinary skill in the art can understand that all or part of the steps of the above method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium, which, when executed, executes the steps of the above method embodiments; and the aforementioned storage medium includes: mobile storage devices, read-only memory (ROM), random access memory (RAM), disks or optical disks, and other media that can store program codes.

[0090] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0091] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0092] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0093] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0094] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0095] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory function test system, characterized in that: include: A chip temperature screening device, a host computer and an environmental chamber, wherein the chip temperature screening device comprises a test base plate, the test base plate is divided into an interface area and a test area, a microcontroller is connected through an interface in the interface area, and a memory chip to be tested is connected to a test carrier in the test area by a spring crimping method; The host computer is used to generate a test instruction and send the test instruction to the microcontroller, so that the microcontroller tests the memory chip to be tested in the test area; The environmental box is used to provide the temperature environment required for memory chip testing.

2. The memory function test system according to claim 1, characterized in that: The interface area is also provided with a power interface, through which a power supply module is connected, and through which power is supplied to the test area.

3. The memory function test system according to claim 1, characterized in that: The test carrier is divided into a flash memory type memory chip test area and a dual-port memory chip test area.

4. The memory function test system according to claim 3, characterized in that: The flash memory chip test area includes 64 slots, and the dual-port memory chip test area includes 4 slots.

5. The memory function test system according to claim 3, characterized in that: The host computer can be connected to four test boards, wherein the host computer can distinguish each of the test boards based on the address codes corresponding to the test boards.

6. The memory function test system according to claim 3, characterized in that: The test carrier board has a unified external interface.

7. A memory function testing method, characterized in that: The method applied to the microcontroller in the memory function test system according to claim 1 comprises: In response to receiving a test instruction for a memory chip to be tested in a test area sent by a host computer, performing a read and write test on the memory chip to be tested based on the test instruction to obtain a test result; The test result is output to the host computer.

8. The memory function testing method according to claim 7, characterized in that: The performing a read and write test on the memory chip to be tested based on the test instruction to obtain a test result includes: Determining a test process based on the type of the memory chip to be tested in the test instruction; Testing the memory chip to be tested based on the test process to obtain a test result; Wherein, if the memory chip to be tested is a dual-port memory, the test process includes left-side data writing, left-side data reading, right-side data writing and right-side data reading; If the storage chip to be tested is a flash memory chip, the test process includes full chip erasing, data writing, data reading and data verification.

9. The memory function testing method according to claim 8, characterized in that: The step of testing the memory chip to be tested based on the test process to obtain a test result includes: Parsing the test instruction, if the test instruction is an automatic loop test, sequentially testing each storage area of ​​the memory chip to be tested based on each test step in the test flow to obtain a test result; If the test instruction is a single test, a target to-be-tested function corresponding to the to-be-tested memory chip is determined, and the target to-be-tested function is tested based on the test flow to obtain a test result of the target memory area.

10. The memory function testing method according to claim 8, characterized in that: Also includes: Based on the test process, generate test progress information; The test progress information is sent to the host computer so that the host computer outputs the test progress information.

Images