Formation method of semiconductor structure
During the semiconductor structure formation process, the machine temperature of the low-temperature ion implantation process is set to -30°C to -80°C, and the amorphous region, light doping region and stress concentration region are formed under a specific mask structure, which solves the problems of capacity loss and cooling pipeline condensation in the prior art, and achieves a more efficient process flow and lower energy consumption.
Patent Information
- Application Number
- CN202311482060.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-08
- Publication Date
- 2025-05-13
AI Technical Summary
The low-temperature ion implantation process used in the formation of existing semiconductor structures has problems of capacity loss and cooling pipeline condensation, which affects process efficiency and equipment life.
By setting the machine temperature of the first low-temperature ion implantation process and the second low-temperature ion implantation process to -30°C to -80°C, an amorphous region, a light doping region and a stress concentration region are formed under a specific mask structure, and doping is made with different ions (such as carbon ions and germanium ions) to form an optimized semiconductor structure.
It effectively reduces the capacity loss when cooling the silicon wafer again, reduces the problem of condensation inside the cooling pipeline, extends the time for cleaning and condensation, and further reduces the capacity loss, while not affecting the performance of the final semiconductor structure.
Smart Images
Figure CN119993828A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] Ion implantation is a material surface improvement technology that has flourished and been widely used internationally in recent years. Its principle is to use an ion beam with an energy of, for example, 100 KeV to be incident on the material, causing a series of physical and chemical interactions between the ion beam and the atoms or molecules in the material. The incident ions gradually lose energy and finally stay in the material, causing changes in the surface composition, structure and properties of the material, thereby optimizing the performance of the material surface or obtaining some new excellent properties.
[0003] At present, the ion implantation process generally adopts room temperature ion implantation, and the ambient temperature of room temperature implantation is about 15°C. During the implantation, when the ions are implanted into the substrate lattice, the substrate lattice will be damaged. At the same time, the silicon wafer will heat up to 50°C to 60°C (under the condition of ambient temperature of 15°C) because the kinetic energy loss of the ions is converted into heat energy, causing the damage to self-repair instantly. The temperature of the substrate is strongly related to the self-repair of the damage. The higher the temperature, the stronger the self-repair ability, thus affecting the effect of ion implantation.
[0004] In order to solve these problems, cold ion implantation (Cold IMP) was introduced. Compared with normal temperature ion implantation, the process temperature of cold ion implantation is lower than room temperature. During the cold implantation process, the self-repair process of the lattice will become extremely slow. In this case, the amorphous state is generated faster, and the amorphous layer has fewer lattice gaps, which can effectively block the rapid penetration of the implanted atoms, thereby greatly reducing the lattice defects in the lower part of the amorphous layer after annealing.
[0005] However, there are still many problems with the low-temperature ion implantation used in the semiconductor structure formation process in the prior art. Summary of the invention
[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can effectively reduce production capacity loss.
[0007] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a gate structure on the substrate; forming a first sidewall on the sidewall of the gate structure; using the gate structure and the first sidewall as a mask, adopting a first low-temperature ion implantation process to form an amorphous region in the substrate on both sides of the gate structure, the machine temperature of the first low-temperature ion implantation process is set to -30°C to -80°C; forming a lightly doped region in the amorphous region on both sides of the gate structure; after forming the lightly doped region, forming a second sidewall on the sidewall of the first sidewall; using the gate structure, the first sidewall and the second sidewall as a mask, adopting a second low-temperature ion implantation process to form a stress concentration region in the substrate on both sides of the gate structure, the machine temperature of the second low-temperature ion implantation process is set to -30°C to -80°C; forming a source-drain doped region in the stress concentration region on both sides of the gate structure.
[0008] Optionally, the implanted ions in the first low-temperature ion implantation process include carbon ions.
[0009] Optionally, the implanted ions in the second low-temperature ion implantation process include germanium ions.
[0010] Optionally, the method for forming the lightly doped region includes: using the gate structure and the first sidewall as masks, and injecting lightly doped ions into the amorphous regions on both sides of the gate structure to form the lightly doped region.
[0011] Optionally, the method for forming the source-drain doped region includes: using the gate structure, the first side wall and the second side wall as masks, and injecting source-drain ions into the stress concentration region on both sides of the gate structure to form the source-drain doped region.
[0012] Optionally, the electrical type of the lightly doped ions is the same as the electrical type of the source and drain ions.
[0013] Optionally, the lightly doped ions and the source and drain ions are both N-type ions.
[0014] Optionally, the gate structure includes: a gate dielectric layer, and a gate layer located on the gate dielectric layer.
[0015] Optionally, the material of the gate layer includes: amorphous silicon.
[0016] Optionally, the structure of the first side wall includes: a single-layer structure or a stacked structure; the structure of the second side wall includes: a single-layer structure or a stacked structure.
[0017] Optionally, the material of the first sidewall spacer includes one or more of silicon nitride, silicon carbonitride and silicon carbide; the material of the second sidewall spacer includes one or more of silicon nitride, silicon carbonitride and silicon carbide.
[0018] Optionally, the substrate is a planar structure.
[0019] Optionally, the substrate includes: a base and a fin located on the base.
[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0021] In the method for forming a semiconductor structure of the technical solution of the present invention, by setting the machine temperature of the first low-temperature ion implantation process and the second low-temperature ion implantation process at -30°C to -80°C, the capacity loss when the silicon wafer is cooled again is effectively reduced, and the problem of condensation inside the cooling pipeline can be effectively reduced, and the time to remove condensation at room temperature is extended, further reducing the capacity loss. In addition, setting the machine temperature of the first low-temperature ion implantation process and the second low-temperature ion implantation process at -30°C to -80°C will not affect the performance of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figures 1 to 8 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention; DETAILED DESCRIPTION
[0023] As described in the background art, the low-temperature ion implantation used in the semiconductor structure formation process in the prior art still has many problems, which will be described in detail below.
[0024] At present, the low-temperature ion implantation process is used in the formation of lightly doped regions and source-drain doped regions of transistors. However, the machine temperature of the low-temperature ion implantation process is generally set at -100°C. During the ion implantation process, the temperature of the silicon wafer surface will rise, and then it needs to be cooled again.
[0025] However, the lower the temperature level, the more cooling materials (such as liquid nitrogen) are needed for re-cooling, and the greater the capacity loss. In addition, the cooling pipeline works in a continuous low temperature (-100℃) environment, which is prone to condensation inside the pipeline. It needs to be raised to room temperature and cleared once every two days. Re-cooling will cause more capacity loss.
[0026] On this basis, the present invention provides a method for forming a semiconductor structure, by setting the machine temperature of the first low-temperature ion implantation process and the second low-temperature ion implantation process at -30°C to -80°C, the capacity loss when the silicon wafer is cooled again is effectively reduced, and the problem of condensation inside the cooling pipeline is effectively reduced, and the time to remove condensation at room temperature is extended, thereby further reducing the capacity loss. In addition, setting the machine temperature of the first low-temperature ion implantation process and the second low-temperature ion implantation process at -30°C to -80°C will not affect the performance of the semiconductor structure finally formed.
[0027] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0028] Figures 1 to 8 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.
[0029] Please refer to Figure 1 , providing a substrate 100.
[0030] In this embodiment, the semiconductor structure is formed as a planar structure, and the corresponding substrate 100 is a planar structure.
[0031] In other embodiments, when the formed semiconductor structure is a fin field effect transistor, the corresponding substrate may further include a base and a fin located on the base.
[0032] In this embodiment, the substrate 100 is made of silicon.
[0033] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.
[0034] In other embodiments, the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate 100 .
[0035] Please refer to Figure 2 , a gate structure 101 is formed on the substrate 100 .
[0036] In this embodiment, the gate structure 101 includes: a gate dielectric layer, and a gate layer (not shown) located on the gate dielectric layer.
[0037] In this embodiment, the method for forming the gate structure 101 includes: forming a gate dielectric material layer (not shown) on the substrate 100; forming a gate material layer (not shown) on the gate dielectric material layer; and patterning the gate material layer and the gate dielectric material layer to form the gate layer and the gate dielectric layer.
[0038] In this embodiment, the material of the gate dielectric layer is silicon oxide, and the material of the gate layer is amorphous silicon.
[0039] Please refer to Figure 3 , a first spacer 102 is formed on the sidewall of the gate structure 101 .
[0040] In this embodiment, the first spacer 102 is used to define the position of the lightly doped region 104 to be formed subsequently.
[0041] In this embodiment, the method for forming the first sidewall 102 includes: forming a first sidewall material layer (not shown) on the sidewall and top surface of the gate structure 101 and the top surface of the substrate 100; and etching back the first sidewall material layer until the top surface of the gate structure 101 and the top surface of the substrate 100 are exposed to form the first sidewall 102.
[0042] The structure of the first spacer 102 includes: a single-layer structure or a stacked-layer structure, and the material of the first spacer 102 includes: one or more of: silicon nitride, silicon carbonitride and silicon carbide.
[0043] In this embodiment, the first sidewall spacer 102 has a single-layer structure, and the material of the first sidewall spacer 102 is silicon nitride.
[0044] Please refer to Figure 4 Using the gate structure 101 and the first sidewall 102 as masks, a first low-temperature ion implantation process is used to form an amorphous region 103 in the substrate 100 on both sides of the gate structure 101. The machine temperature of the first low-temperature ion implantation process is set to -30°C to -80°C.
[0045] In this embodiment, the implanted ions in the first low-temperature ion implantation process are carbon ions.
[0046] It should be noted that, in this embodiment, the machine temperature of the first low-temperature ion implantation process is set to -30°C to -80°C, that is, the temperature of the wafer used to form the semiconductor structure is between -30°C and -80°C. The working principle of the machine of the first low-temperature ion implantation process is: the temperature of the wafer surface is detected in real time by a sensor, and when the deviation between the detected temperature and the temperature set by the machine is greater than a threshold range, the wafer is cooled by a cooling material (such as liquid nitrogen) until it reaches the temperature position set by the machine.
[0047] Please refer to Figure 5 , a lightly doped region 104 is formed in the amorphous region 103 on both sides of the gate structure 101 .
[0048] In this embodiment, the lightly doped region 104 provides an impurity concentration gradient for the subsequently formed source-drain doped region 107 , reduces the electric field between the junction and the channel region, and can prevent the generation of hot carriers.
[0049] In this embodiment, the method for forming the lightly doped region 104 includes: using the gate structure 101 and the first sidewall 102 as masks, and implanting lightly doped ions into the amorphous region 103 on both sides of the gate structure 101 to form the lightly doped region 104 .
[0050] In this embodiment, the lightly doped ions are N-type ions, and the N-type ions include phosphorus, arsenic or antimony.
[0051] Please refer to Figure 6 After forming the lightly doped region 104 , a second sidewall spacer 105 is formed on the sidewall of the first sidewall spacer 102 .
[0052] In this embodiment, the second spacer 105 is used to define the position of the source / drain doped region 107 to be formed subsequently.
[0053] In this embodiment, the method for forming the second sidewall 105 includes: forming a second sidewall material layer (not shown) on the top surface of the gate structure 101, the sidewall and top surface of the first sidewall 102, and the top surface of the substrate 100; and etching back the second sidewall material layer until the top surface of the gate structure 101, the top surface of the first sidewall 102, and the top surface of the substrate 100 are exposed, thereby forming the second sidewall 105.
[0054] The structure of the second sidewall spacer 105 includes a single-layer structure or a stacked-layer structure, and the material of the second sidewall spacer 105 includes one or more of silicon nitride, silicon carbonitride and silicon oxycarbide.
[0055] In this embodiment, the second sidewall spacer 105 is a single-layer structure, and the first sidewall spacer 102 is made of silicon nitride.
[0056] Please refer to Figure 7 , using the gate structure 101, the first sidewall 102 and the second sidewall 105 as masks, a second low-temperature ion implantation process is adopted to form a stress concentration area 106 in the substrate 100 on both sides of the gate structure 101, and the machine temperature of the second low-temperature ion implantation process is set to -30°C to -80°C.
[0057] It should be noted that the low-temperature ion implantation process has obvious advantages over the traditional room-temperature ion implantation process. The defect performance is better, the amorphous area formed is more uniform and flat, and the local mismatch of the lattice is smaller. The performance of devices formed by the low-temperature ion implantation process can be improved by 3% to 7% compared with the traditional room-temperature ion implantation process.
[0058] In this embodiment, the implanted ions in the second low-temperature ion implantation process are germanium ions.
[0059] It should be noted that, in this embodiment, the machine temperature of the second low-temperature ion implantation process is set to -30°C to -80°C, that is, the temperature of the silicon wafer is between -30°C and -80°C.
[0060] In this embodiment, by setting the machine temperature of the first low-temperature ion implantation process and the second low-temperature ion implantation process at -30°C to -80°C, the production capacity loss when the silicon wafer is cooled again is effectively reduced, and the problem of condensation inside the cooling pipeline can be effectively reduced, and the time to rise to room temperature to remove condensation is extended, further reducing the production capacity loss. In addition, experimental comparison shows that the machine temperature of the first low-temperature ion implantation process and the second low-temperature ion implantation process is set at -30°C to -80°C, compared with -100°C, which does not affect the performance of the semiconductor structure finally formed.
[0061] It should be noted that, in the present embodiment, the machine temperature of the first low-temperature ion implantation process and the second low-temperature ion implantation process is preferably set at -40°C. Experimental data show that when the machine temperature of the low-temperature ion implantation process is higher than -20°C, it will affect the performance of the semiconductor structure finally formed. The machine of the low-temperature ion implantation process also has a certain range of deviation when adjusting the temperature. Therefore, in order to absorb the machine error and improve the process window, the machine temperature of the low-temperature ion implantation process is also maximized to reduce the production capacity loss. Therefore, the machine temperature of the first low-temperature ion implantation process and the second low-temperature ion implantation process is preferably set at -40°C.
[0062] Please refer to Figure 8 , source-drain doped regions 107 are formed in the stress concentration regions 106 on both sides of the gate structure 101 .
[0063] In this embodiment, the method for forming the source-drain doped region 107 includes: using the gate structure 101, the first side wall 102 and the second side wall 105 as masks, injecting source-drain ions into the stress concentration region 106 on both sides of the gate structure 101 to form the source-drain doped region 107.
[0064] In this embodiment, the electrical type of the lightly doped ions is the same as the electrical type of the source and drain ions, so the corresponding source and drain ions are also N-type ions.
[0065] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a gate structure on the substrate; forming a first spacer on a sidewall of the gate structure; Using the gate structure and the first sidewall as masks, a first low-temperature ion implantation process is used to form an amorphous region in the substrate on both sides of the gate structure, wherein the machine temperature of the first low-temperature ion implantation process is set to -30°C to -80°C; forming lightly doped regions in the amorphous regions on both sides of the gate structure; After forming the lightly doped region, forming a second sidewall spacer on the sidewall of the first sidewall spacer; Using the gate structure, the first sidewall and the second sidewall as masks, a second low-temperature ion implantation process is performed to form stress concentration areas in the substrate at both sides of the gate structure, wherein the machine temperature of the second low-temperature ion implantation process is set to -30°C to -80°C; Source and drain doping regions are formed in the stress concentration regions on both sides of the gate structure.
2. The method for forming a semiconductor structure according to claim 1, wherein: The implanted ions in the first low-temperature ion implantation process include carbon ions.
3. The method for forming a semiconductor structure according to claim 1, wherein: The implanted ions in the second low-temperature ion implantation process include germanium ions.
4. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the lightly doped region includes: using the gate structure and the first sidewall as masks, and injecting lightly doped ions into the amorphous regions on both sides of the gate structure to form the lightly doped region.
5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the source-drain doped region includes: using the gate structure, the first sidewall and the second sidewall as masks, injecting source-drain ions into the stress concentration regions on both sides of the gate structure to form the source-drain doped region.
6. The method for forming a semiconductor structure according to claim 5, wherein: The electrical type of the lightly doped ions is the same as the electrical type of the source and drain ions.
7. The method for forming a semiconductor structure according to claim 6, wherein: The lightly doped ions and the source and drain ions are both N-type ions.
8. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure includes: a gate dielectric layer and a gate layer located on the gate dielectric layer.
9. The method for forming a semiconductor structure according to claim 8, wherein: The material of the gate layer includes: amorphous silicon.
10. The method for forming a semiconductor structure according to claim 1, wherein: The structure of the first sidewall includes: a single-layer structure or a stacked structure; the structure of the second sidewall includes: a single-layer structure or a stacked structure.
11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first sidewall spacer includes one or more of silicon nitride, silicon carbonitride and silicon carbide oxide; the material of the second sidewall spacer includes one or more of silicon nitride, silicon carbonitride and silicon carbide oxide.
12. The method for forming a semiconductor structure according to claim 1, wherein: The substrate is a planar structure.
13. The method for forming a semiconductor structure according to claim 1, wherein: The substrate includes a base and a fin located on the base.