Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure. The preparation method of the semiconductor structure comprises the steps of providing a substrate; forming an initial bonding structure on the substrate, wherein the size of the initial bonding structure is smaller than that of the substrate; circumferentially removing a part of the initial bonding structure to form a step structure, wherein the remaining initial bonding structure forms a target bonding structure; and forming a continuous sputtering layer, wherein the continuous sputtering layer covers the top surface of the step structure, the top surface of the target bonding structure and the exposed top surface of the substrate. According to the preparation method of the semiconductor structure, after a part of the initial bonding structure is removed in the circumferential direction, the formed step structure reduces the height difference between the initial bonding structure and the substrate, so that the connection between the formed target bonding structure and the substrate is smoother, and therefore, when the continuous sputtering layer is formed, the sputtering efficiency is improved. The top surface of the step structure, the top surface of the target bonding structure and the exposed top surface of the substrate can be continuously covered, and the fracture of the continuous construction layer is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] As an advanced packaging and connection technology, hybrid bonding technology is widely used in semiconductor manufacturing, microelectronic packaging, optoelectronic devices, etc. It combines different types of bonding methods to achieve high-strength and high-reliability connections.

[0003] However, since the hybrid bonding process has a weaker control over the total thickness variation (TTV) at the edge of the semiconductor structure, the edge of the bonded semiconductor structure has a higher step. In the subsequent process, when a new film layer is formed at the step, it is easy to break, thus affecting the reliability of the semiconductor structure. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a method for preparing a semiconductor structure and a semiconductor structure, which can at least effectively avoid film layer breakage.

[0005] According to some embodiments, a method for preparing a semiconductor structure is provided, the method comprising: providing a substrate; forming an initial bonding structure on the substrate, the size of the initial bonding structure being smaller than the size of the substrate; circumferentially removing a portion of the initial bonding structure to form a step structure, the remaining initial bonding structure constituting a target bonding structure; forming a continuous sputtering layer, the continuous sputtering layer covering the top surface of the step structure, the top surface of the target bonding structure and the exposed top surface of the substrate.

[0006] In the method for preparing the semiconductor structure, a portion of the initial bonding structure is removed circumferentially to form a step structure, and the remaining initial bonding structure constitutes a target bonding structure; and then a continuous sputtering layer is formed to cover the top surface of the step structure, the top surface of the target bonding structure, and the exposed top surface of the substrate. Since the step structure formed after the circumferential removal of a portion of the initial bonding structure reduces the height difference between the initial bonding structure and the substrate, the connection between the formed target bonding structure and the substrate is smoother, so that when forming a continuous sputtering layer, the top surface of the step structure, the top surface of the target bonding structure, and the exposed top surface of the substrate can be continuously covered, avoiding the breakage of the continuous construction layer.

[0007] In some embodiments, the step structure includes at least one step layer; and the total thickness of the target bonding structure is a preset multiple of the thickness of the step layer.

[0008] In some embodiments, the preset multiple ranges from 5 times to 20 times.

[0009] In some embodiments, the step structure includes multiple step layers; circumferentially removing part of the initial bonding structure to form the step structure includes: circumferentially removing part of the initial bonding structure in steps to sequentially form multiple step layers; wherein the target size of each step layer is the same.

[0010] In some embodiments, the target size of the step layer is in the range of 15 nm to 25 nm.

[0011] In some embodiments, the initial bonding structure includes a wiring structure and a peripheral dielectric layer surrounding the wiring structure; and removing a portion of the initial bonding structure in a circumferential direction to form a step structure includes:

[0012] A portion of the peripheral dielectric layer is removed in a circumferential direction to form a step structure, the step structure surrounds the wiring structure, and the remaining peripheral dielectric layer and the wiring structure constitute a target bonding structure.

[0013] In some embodiments, the routing structure includes routing layers arranged at intervals along a direction parallel to the substrate; the method further includes: based on a continuous sputtering layer, forming a boss structure arranged at intervals along a direction parallel to the substrate, the boss structure is correspondingly located on the top surface of the routing layer.

[0014] According to some embodiments, the present application further provides a semiconductor structure, which is prepared using the method for preparing the semiconductor structure in any of the above embodiments.

[0015] In the above-mentioned semiconductor structure, since the step structure reduces the height difference between the target bonding structure and the substrate, the connection between the formed target bonding structure and the substrate is smoother, so that when forming a continuous sputtering layer, the top surface of the step structure, the top surface of the target bonding structure and the exposed top surface of the substrate can be continuously covered, thereby avoiding the breakage of the continuous construction layer.

[0016] In some embodiments, the step structure includes at least one step layer, and the total thickness of the target bonding structure is a preset multiple of the thickness of the step layer.

[0017] In some embodiments, the target bonding structure includes a routing structure, and the step structure surrounds the routing structure; the routing structure includes a routing layer arranged at intervals along a direction parallel to the substrate; the semiconductor structure also includes a boss structure arranged at intervals along a direction parallel to the substrate; the boss structure is correspondingly located on the top surface of the routing layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the positions of a fixing member and a probe in a method for preparing a semiconductor structure;

[0019] Figure 2 A schematic diagram of the positions of a fixing member and a probe in another method for preparing a semiconductor structure;

[0020] Figure 3 A schematic flow chart of a method for preparing a semiconductor structure provided by an embodiment;

[0021] Figure 4 A schematic cross-sectional view of a structure obtained in step S10 and step S30 in a method for preparing a semiconductor structure provided in an embodiment;

[0022] Figure 5 A schematic cross-sectional view of a structure obtained in step S511 in a method for preparing a semiconductor structure provided in an embodiment;

[0023] Figure 6 A schematic cross-sectional view of a structure obtained in step S512 in a method for preparing a semiconductor structure provided in an embodiment;

[0024] Figure 7 A schematic cross-sectional view of a structure obtained in step S70 in a method for preparing a semiconductor structure provided in an embodiment;

[0025] Figure 8 The cross-sectional view of the structure obtained in step S90 in a method for preparing a semiconductor structure provided by an embodiment is a schematic diagram.

[0026] Explanation of the reference numerals: 10, substrate; 11, probe; 12, fixture; 20, target bonding structure; 30, initial bonding structure; 31, routing structure; 311, routing layer; 32, peripheral dielectric layer; 40, step structure; 41, step layer; 50, continuous sputtering layer; 51, boss structure. DETAILED DESCRIPTION

[0027] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0029] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0030] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0031] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0032] In addition, in order to clearly indicate the multiple layers and regions in the drawings, the thickness of each layer and each region in the drawings are enlarged to clearly illustrate the relative positions between the layers and the distribution of each region. When a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, the expression includes not only the case where it is "directly" above the other part, but also the case where there are other layers in between. And, it is understood that when a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, it generally refers to the side located directly above the other part.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.

[0034] See also Figure 1 to Figure 2 Since the hybrid bonding process has a weaker control over the total thickness variation (TTV) of the semiconductor structure edge, the edge of the bonded semiconductor structure has a higher step. At this time, the diameter of the semiconductor structure is usually 299mm, and there is a step of 100um height on the edge. Therefore, in the subsequent electroplating process, how to deposit the sputtered layer on the 100um vertical step without breaking has become a difficult problem in the industry. Figure 1 As shown, the wafer fixture 12 is fixed to the side of the step, and the subsequent sputtering layer deposition is discontinuous due to the height of the step. Figure 2 As shown, usually, the fixing member 12 is moved inward so that the probe 11 can smoothly and continuously deposit the sputtered layer. However, this method requires a large change in the hardware of the device.

[0035] See also Figure 3 According to some embodiments, a method for preparing a semiconductor structure is provided, the method comprising:

[0036] Step S10, providing a substrate;

[0037] Step S30, forming an initial bonding structure on the substrate, wherein the size of the initial bonding structure is smaller than the size of the substrate;

[0038] Step S50, removing part of the initial bonding structure in the circumferential direction to form a step structure, and the remaining initial bonding structure constitutes a target bonding structure;

[0039] Step S70 , forming a continuous sputtering layer, wherein the continuous sputtering layer covers the top surface of the step structure, the top surface of the target bonding structure and the exposed top surface of the substrate.

[0040] In the method for preparing the semiconductor structure, a portion of the initial bonding structure is removed circumferentially to form a step structure, and the remaining initial bonding structure constitutes a target bonding structure; and then a continuous sputtering layer is formed to cover the top surface of the step structure, the top surface of the target bonding structure, and the exposed top surface of the substrate. Since the step structure formed after the circumferential removal of a portion of the initial bonding structure reduces the height difference between the initial bonding structure and the substrate, the connection between the formed target bonding structure and the substrate is smoother, so that when forming a continuous sputtering layer, the top surface of the step structure, the top surface of the target bonding structure, and the exposed top surface of the substrate can be continuously covered, avoiding the breakage of the continuous construction layer.

[0041] In some embodiments, the step structure includes at least one step layer; and the total thickness of the target bonding structure is a preset multiple of the thickness of the step layer.

[0042] In some embodiments, the preset multiple ranges from 5 times to 20 times.

[0043] In some embodiments, the step structure includes multiple step layers; step S50, circumferentially removing a portion of the initial bonding structure to form the step structure, includes:

[0044] Step S51, removing part of the initial bonding structure in a circumferential direction step by step to sequentially form multiple step layers; wherein the target size of each step layer is the same.

[0045] In some embodiments, the target size of the step layer is in the range of 15 nm to 25 nm.

[0046] In some embodiments, the initial bonding structure includes a wiring structure and a peripheral dielectric layer surrounding the wiring structure; step S50, circumferentially removing a portion of the initial bonding structure to form a step structure, includes:

[0047] Step S52 : removing part of the peripheral dielectric layer in a circumferential direction to form a step structure, wherein the step structure surrounds the wiring structure, and the remaining peripheral dielectric layer and the wiring structure constitute a target bonding structure.

[0048] In some embodiments, the routing structure includes routing layers arranged in a spaced relationship parallel to the substrate; and the method further includes:

[0049] Step S90: Based on the continuous sputtering layer, a boss structure arranged at intervals along a direction parallel to the substrate is formed, and the boss structure is correspondingly located on the top surface of the routing layer.

[0050] In the above embodiments of the present disclosure, unless otherwise specified herein, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0051] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiment, Figures 3 to 8 The method is described in detail.

[0052] like Figure 4 As shown, in step S10, a substrate 10 is provided.

[0053] As an example, in the embodiment of the present disclosure, the substrate 10 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10 or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator. Those skilled in the art can select the type of substrate 10 according to the type of transistor formed on the substrate 10, so the type of substrate 10 should not limit the scope of protection of the present disclosure.

[0054] like Figure 4 As shown, in step S30 , an initial bonding structure 30 is formed on the substrate 10 , and the size of the initial bonding structure 30 is smaller than the size of the substrate 10 .

[0055] In some embodiments, the initial bonding structure 30 may be formed by removing a portion of the substrate 10. For example, the width D1 of the initial bonding structure 30 along the first direction is smaller than the width D0 of the substrate 10 along the first direction. The first direction is a direction parallel to the substrate 10, that is, Figure 4 The X direction is shown.

[0056] For example, the initial bonding structure 30 may be formed by removing a portion of the substrate 10 using an etching process. For example, the initial bonding structure 30 may be formed by removing a portion of the substrate 10 using a dry etching process or a wet etching process. For example, a plasma etching process may be used. Plasma etching refers to the use of a high-frequency glow discharge reaction to activate the reaction gas into active particles. These active particles diffuse to the etched portion to react with the etched material to form volatile products that are removed, thereby increasing the process rate.

[0057] For example, a bonding process can also be used to form an initial bonding structure 30 on the substrate 10. For example, a metal welding process, a thermal compression bonding process, ultrasonic welding, adhesive bonding, molecular beam epitaxy (MBE), chemical vapor deposition (CVD), laser bonding or a hybrid bonding process can be used to form the initial bonding structure 30 on the substrate 10. For example, the hybrid bonding process is used to form the initial bonding structure 30 on the substrate 10, which can effectively connect different semiconductor materials (such as silicon, gallium arsenide, gallium nitride, etc.) and non-semiconductor materials (such as glass, ceramics, metals, etc.) to meet specific electrical and thermal performance requirements. Since the hybrid bonding process allows designers to freely select and optimize different connection methods (such as metal welding, bonding, pressing, etc.) according to needs, it can adapt to various design and manufacturing requirements, so the hybrid bonding process has high flexibility. By precisely controlling the interface and connection quality between different materials, the overall performance and reliability of the device can be enhanced, signal loss can be reduced, and heat dissipation characteristics can be improved.

[0058] like Figures 4 to 6 As shown, in step S50 , a portion of the initial bonding structure 30 is removed circumferentially to form a step structure 40 , and the remaining initial bonding structure 30 constitutes the target bonding structure 20 .

[0059] For example, in this step, anisotropic etching can be used to back-etch the initial bonding structure 30 to form a step structure 40. Anisotropic etching can selectively etch the material in a preset crystal direction or crystal plane direction, while leaving only a few or almost no etching marks in other directions. Using anisotropic etching for back-etching in this step can make the morphology of the resulting structure more precise and controllable.

[0060] In some embodiments, the step structure 40 includes at least one step layer 41 ; the total thickness of the target bonding structure 20 is a preset multiple of the thickness of the step layer 41 .

[0061] In some embodiments, the preset multiple ranges from 5 times to 20 times. For example, the preset multiple ranges from 5 times, 10 times, 15 times or 20 times, etc.

[0062] In some embodiments, the step structure 40 includes multiple step layers 41. For example, the number of step layers 41 in the step structure 40 can be set according to a preset multiple. For example, the number of step layers 41 can be 2 to 5. For example, the number of step layers 41 can be 2, 3, 4 or 5. In the embodiment of the present application, Figure 6 The following is an exemplary description using two step layers 41. It should be noted that those skilled in the art can flexibly select the number of step layers 41 according to the actual size and actual needs of the initial bonding structure 30, and the present application does not impose any specific limitation on this.

[0063] For example, the total thickness of the target bonding structure 20 is in the range of 80 um to 120 um. For example, the total thickness of the target bonding structure 20 is in the range of 80 um, 90 um, 100 um, 110 um or 120 um.

[0064] In an embodiment where the step structure 40 includes multiple step layers 41, step S50, circumferentially removing a portion of the initial bonding structure 30 to form the step structure 40, includes:

[0065] Step S51 , removing part of the initial bonding structure 30 in a circumferential direction step by step to sequentially form a plurality of step layers 41 ; wherein the target size of each step layer 41 is the same.

[0066] For example, step S51 , removing part of the initial bonding structure 30 in a stepwise circumferential direction to sequentially form a plurality of stepped layers 41 , may include the following steps.

[0067] like Figure 5 As shown, step S511, removing part of the initial bonding structure 30 in the circumferential direction to form a first step layer 41;

[0068] like Figure 6 As shown, in step S512 , the structure obtained in step S511 is circumferentially removed to form a second step layer 41 .

[0069] In some embodiments, step S512 may be performed multiple times to form more than two step layers 41. For example, after each step layer 41 is formed, a preset cleaning process may be performed, and the preset cleaning process may include a wet cleaning process and a dry cleaning process; the wet cleaning process uses a specific chemical solution and deionized water to clean the wafer surface without damage, and the wet cleaning mainly includes RCA cleaning method, dilution chemical method, IMEC cleaning method or single wafer cleaning method, etc. For example, the single wafer cleaning method not only has a better cleaning effect, but also can reduce the consumption of chemicals and improve the cost-effectiveness of the wafer by recycling the chemical solution and deionized water during the cleaning process.

[0070] In the above embodiment, by removing part of the initial bonding structure 30 in a stepwise circumferential direction, multiple step layers 41 can be formed in sequence, and the thickness of each step layer 41 can be controlled layer by layer, thereby achieving high-precision control of the structural feature size. Thus, a step structure 40 with multiple step layers 41 is formed to further reduce the height difference of each step layer 41. In addition, removing part of the initial bonding structure 30 in a stepwise circumferential direction can effectively reduce the stress generated during the manufacturing process and reduce material defects or deformation caused by stress.

[0071] The target size of the step layer 41 can be understood as the width D2 of the step layer 41 along the first direction, and the second direction is the direction parallel to the substrate 10, that is, Figure 6 The target size of each step layer 41 is the same, that is, the width D2 of each step layer 41 is the same, so that in the process of depositing the subsequent structure, the deposition width of each step layer 41 is the same, thereby further reducing the risk of subsequent film breakage.

[0072] In some embodiments, the target size of the step layer 41 ranges from 15 nm to 25 nm. For example, the target size of the step layer 41 is 15 nm, 20 nm, or 25 nm, etc. For example, the width D2 of the step layer 41 ranges from 15 nm to 25 nm. For example, the width D2 of the step layer 41 is 15 nm, 20 nm, or 25 nm, etc.

[0073] For example, the target size of the step layer 41 can also be understood as the thickness of the step layer 41 along the second direction, where the second direction is a direction perpendicular to the substrate 10, that is, Figure 6 At this time, the target size of each step layer 41 is the same, that is, the thickness of each step layer 41 is the same, so that in the process of forming the subsequent structure, the height difference of each step layer 41 is the same, thereby further reducing the risk of subsequent film breakage.

[0074] In some embodiments, the step layer 41 has a thickness ranging from 8 nm to 12 nm. For example, the target size of the step layer 41 is 8 nm, 9 nm, 10 nm, 11 nm, or 12 nm.

[0075] In some embodiments, the initial bonding structure 30 includes a wiring structure 31 and a peripheral dielectric layer 32 surrounding the wiring structure 31 .

[0076] For example, the wiring structure 31 can be made of a conductive material. The conductive material includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0077] For example, the peripheral dielectric layer 32 can be made of an insulating material. For example, the peripheral dielectric layer 32 can include, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, anti-ferroelectric material, carbide (silicon carbide), or a combination thereof. For example, the high-k material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0078] In an embodiment where the initial bonding structure 30 includes a wiring structure 31 and a peripheral dielectric layer 32 surrounding the wiring structure 31, step S50, circumferentially removing a portion of the initial bonding structure 30 to form a step structure 40, includes:

[0079] Step S52 : removing part of the peripheral dielectric layer 32 in the circumferential direction to form a step structure 40 . The step structure 40 surrounds the wiring structure 31 . The remaining peripheral dielectric layer 32 and the wiring structure 31 constitute the target bonding structure 20 .

[0080] like Figure 7 As shown, in step S70 , a continuous sputtering layer 50 is formed, and the continuous sputtering layer 50 covers the top surface of the step structure 40 , the top surface of the target bonding structure 20 , and the exposed top surface of the substrate 10 .

[0081] For example, the continuous sputtering layer 50 can be formed by a physical vapor deposition process. For example, the continuous sputtering layer 50 can be formed by an electroplating sputtering process, in which ions are reduced and deposited on the surface of the substrate by an electrochemical reaction. When current passes through the electrolyte, the ions are reduced and attached to the electrode to form a thin film, and high-energy particles (usually argon ions) bombard the target material, causing the target material atoms to fall off and deposit on the surface of the substrate.

[0082] In the above embodiment, since the step structure 40 has multiple step layers 41, the height difference of each step layer 41 of the step structure 40 is reduced, so that when the continuous sputtering layer 50 is formed, the continuous sputtering layer 50 can continuously cover the top surface of the step structure 40, the top surface of the target bonding structure 20 and the exposed top surface of the substrate 10, effectively avoiding the breakage of the continuous sputtering layer 50.

[0083] For example, before executing step S70, the step of cleaning the obtained structure can also be included. By cleaning, impurities on the surface of the obtained structure can be removed to avoid affecting subsequent processes, thereby ensuring the performance of the device. Specifically, the obtained structure can be cleaned with a cleaning solution, and the obtained structure can be placed in a cleaning tank where the cleaning solution is stored for cleaning. The cleaning solution and cleaning process used to clean the obtained structure are known to those skilled in the art, and will not be described here. It should be noted that after cleaning the obtained structure, a step of drying the obtained structure is also required. The method for drying the obtained structure is well known to those skilled in the art, and will not be described here.

[0084] In some embodiments, the routing structure 31 includes routing layers 311 arranged at intervals in a direction parallel to the substrate 10 , and the routing layers 311 arranged at intervals are insulated from each other.

[0085] In an embodiment where the routing structure 31 includes a routing layer 311, the method further includes:

[0086] like Figure 8 As shown, in step S90 , based on the continuous sputtering layer 50 , boss structures 51 arranged at intervals in a direction parallel to the substrate 10 are formed, and the boss structures 51 are correspondingly located on the top surface of the wiring layer 311 .

[0087] In some embodiments, the boss structure 51 includes a solder ball. For example, in the step, the boss structure 51 can be formed by removing a portion of the continuous sputtering layer 50 .

[0088] In the method for preparing the semiconductor structure, a portion of the initial bonding structure 30 is removed circumferentially to form a step structure 40, and the remaining initial bonding structure 30 constitutes the target bonding structure 20; and then a continuous sputtering layer 50 is formed to cover the top surface of the step structure 40, the top surface of the target bonding structure 20, and the exposed top surface of the substrate 10. Since the step structure 40 formed after the circumferential removal of a portion of the initial bonding structure 30 reduces the height difference between the initial bonding structure 30 and the substrate 10, the connection between the formed target bonding structure 20 and the substrate 10 is smoother, so that when the continuous sputtering layer 50 is formed, the top surface of the step structure 40, the top surface of the target bonding structure 20, and the exposed top surface of the substrate 10 can be continuously covered, thereby avoiding the breakage of the continuous construction layer, and there is no need to change the hardware of the semiconductor device.

[0089] See also Figure 8 According to some embodiments, the present application also provides a semiconductor structure, which is prepared using the semiconductor structure preparation method in any of the above embodiments.

[0090] In the above-mentioned semiconductor structure, since the step structure 40 reduces the height difference between the target bonding structure 20 and the substrate 10, the connection between the formed target bonding structure 20 and the substrate 10 is smoother, so that when forming the continuous sputtering layer 50, the top surface of the step structure 40, the top surface of the target bonding structure 20 and the exposed top surface of the substrate 10 can be continuously covered, thereby avoiding the breakage of the continuous construction layer.

[0091] In some embodiments, the step structure 40 includes at least one step layer 41 , and the total thickness of the target bonding structure 20 is a preset multiple of the thickness of the step layer 41 .

[0092] In some embodiments, the preset multiple ranges from 5 times to 20 times. For example, the preset multiple ranges from 5 times, 10 times, 15 times or 20 times, etc.

[0093] For example, the target size of each step layer 41 is the same. The target size of the step layer 41 can be understood as the width of the step layer 41 along the first direction. In some embodiments, the target size of the step layer 41 ranges from 15nm to 25nm. For example, the target size of the step layer 41 is 15nm, 20nm, or 25nm, etc.

[0094] In some embodiments, the target bonding structure 20 includes a routing structure 31, and the step structure 40 surrounds the routing structure 31; the routing structure 31 includes a routing layer 311 arranged at intervals along a direction parallel to the substrate 10; the semiconductor structure also includes a boss structure 51 arranged at intervals along a direction parallel to the substrate 10; the boss structure 51 is correspondingly located on the top surface of the routing layer 311.

[0095] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming an initial bonding structure on the substrate, wherein the size of the initial bonding structure is smaller than the size of the substrate; Removing part of the initial bonding structure in a circumferential direction to form a step structure, and the remaining initial bonding structure constitutes a target bonding structure; A continuous sputtering layer is formed, wherein the continuous sputtering layer covers the top surface of the step structure, the top surface of the target bonding structure, and the exposed top surface of the substrate.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step structure includes at least one step layer; The total thickness of the target bonding structure is a preset multiple of the thickness of the step layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The preset multiple ranges from 5 times to 20 times.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: The step structure includes multiple step layers; and the circumferential removal of a portion of the initial bonding structure to form the step structure includes: Part of the initial bonding structure is removed in steps and circumferentially to sequentially form the plurality of step layers; wherein the target size of each step layer is the same.

5. The method for preparing a semiconductor structure according to any one of claims 2 to 4, characterized in that: The target size range of the step layer is 15nm-25nm.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The initial bonding structure includes a wiring structure and a peripheral dielectric layer surrounding the wiring structure; The circumferentially removing part of the initial bonding structure to form a step structure comprises: A portion of the peripheral dielectric layer is removed circumferentially to form the step structure, the step structure surrounds the wiring structure, and the remaining peripheral dielectric layer and the wiring structure constitute the target bonding structure.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The routing structure includes routing layers arranged at intervals in a direction parallel to the substrate; the method further includes: Based on the continuous sputtering layer, boss structures are formed which are arranged at intervals in a direction parallel to the substrate, and the boss structures are correspondingly located on the top surface of the routing layer.

8. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 7.

9. The semiconductor structure according to claim 8, characterized in that: The step structure includes at least one step layer, and the total thickness of the target bonding structure is a preset multiple of the thickness of the step layer.

10. The semiconductor structure according to claim 9, characterized in that: The target bonding structure includes a wiring structure, and the step structure surrounds the wiring structure; the wiring structure includes wiring layers arranged at intervals in a direction parallel to the substrate; The semiconductor structure further includes boss structures arranged at intervals in a direction parallel to the substrate; the boss structures are correspondingly located on the top surface of the wiring layer.

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