Copper-cylinder-free wafer PLP packaging method
Through the copper-free column wafer PLP packaging method, the problems of difficulty in absorbing copper-free column wafers and chip offset during the packaging process are solved, and an efficient and accurate packaging process is achieved, improving product quality and packaging efficiency.
Patent Information
- Application Number
- CN202510186441.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-20
- Publication Date
- 2025-05-13
AI Technical Summary
The existing PLP packaging technology is mainly aimed at wafers with existing copper columns, which leads to difficulties in absorbing copper column-free wafers during packaging, resulting in chip offset problems and affecting production quality.
A copper-free column wafer PLP packaging method is proposed, including transferring the chip on the copper-free column wafer to the substrate, obtaining the actual position of the chip and its pins, generating positioning drawings, forming a plastic sealing layer, laser drilling to expose the pins, and performing line production to complete the packaging.
This method can directly package copper-free column wafers, saving time, improving packaging efficiency, reducing chip offset problems, improving line production accuracy and product quality.
Smart Images
Figure CN119993847A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a copper pillar-free wafer PLP packaging method. Background Art
[0002] In short, packaging is to put the IC bare die produced by the foundry on a substrate that serves as a carrier, use wires to interconnect the IC on the die with the pins, lead out the pins, and then fix and package them into a whole. It can protect the chip, which is equivalent to the shell of the chip. It can not only fix and seal the chip, but also enhance its electrical and thermal performance.
[0003] Panel-level packaging (PLP packaging) is one of the advanced packaging forms. Due to its potential cost-effectiveness and higher manufacturing efficiency, it has attracted widespread attention in the market. The process is generally to attach two or more chips in the patch process, and make a complete panel through a molding process. Then, a protective film is attached to the circuit surface of the chip, and copper leads are plated on it by grinding and electroplating to spread it out. Multiple chips are connected so that they can communicate with each other. Finally, copper through holes are made and electroplating is performed to complete the entire packaging structure.
[0004] However, existing PLP packaging is performed on wafers that have been manufactured with copper pillars (Bumping). The copper pillars will cause difficulty in chip absorption during the PLP packaging process, causing offset problems, thereby affecting production quality. Summary of the invention
[0005] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a PLP packaging method for copper-free wafers to solve the technical problem of how to perform PLP packaging on copper-free wafers.
[0006] The present application provides a copper pillar-free wafer PLP packaging method, the method comprising:
[0007] Providing a copper pillar-free wafer and a substrate, and transferring all chips on the copper pillar-free wafer to the substrate;
[0008] Obtaining the actual position of the chip and its pins on the substrate and generating a positioning drawing;
[0009] forming a plastic packaging layer on the substrate to wrap the chip;
[0010] Grinding the plastic sealing layer to a preset thickness, wherein the preset thickness is greater than the thickness of the chip;
[0011] According to the positioning drawing, laser drilling is performed on the plastic packaging layer to expose the pins of the chip;
[0012] Circuits are fabricated based on the exposed pins of the chip to complete the final chip packaging.
[0013] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0014] The step of transferring all the chips on the copper-post-free wafer to the substrate comprises: transferring all the chips on the copper-post-free wafer to the substrate with a double-sided adhesive film.
[0015] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0016] The obtaining of the actual position of the chip and its pins on the substrate and generating a positioning drawing includes:
[0017] Acquiring the actual position of the chip and its pins on the substrate based on scanning positioning;
[0018] The actual position is compensated according to the conventional offset value and expansion / contraction value of the chip after plastic packaging, and a final positioning drawing of the chip and its pins is generated.
[0019] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0020] The step of laser drilling holes in the plastic packaging layer according to the positioning drawing to expose the pins of the chip includes:
[0021] An alignment hole is arranged on the substrate, and a window is opened in the plastic encapsulation layer based on the alignment hole to expose the chip located at the corner of the plastic encapsulation layer, wherein in a direction perpendicular to the substrate, the area of the plastic encapsulation layer is smaller than the area of the substrate;
[0022] Based on the alignment result of the graphic frame formed by the pins of the exposed chips and the positioning drawing, the plastic packaging layer is laser drilled to form pin holes on the plastic packaging layer to expose the pins of all chips.
[0023] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0024] The alignment hole is located at a corner of the substrate, and the corner of the substrate corresponds to the corner of the plastic packaging layer.
[0025] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0026] The circuit manufacturing based on the exposed pins of the chip includes: using a plasma surface treatment process to clean the pin holes and the surface of the plastic packaging layer.
[0027] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0028] The circuit manufacturing based on the exposed pins of the chip includes: depositing a layer of copper on the surface of the plastic packaging layer to form a seed layer; the seed layer is connected to the exposed pins of the chip through the pin holes.
[0029] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0030] The circuit manufacturing based on the exposed pins of the chip also includes: forming a photoresist film on the seed layer by image transfer to perform epitaxy on the pin holes to form epitaxial holes.
[0031] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0032] The circuit fabrication based on the exposed pins of the chip further includes: fabricating the circuit on the epitaxial hole by electroplating, and removing the photoresist film and the seed layer outside the circuit after the circuit is formed.
[0033] One or more of the above embodiments of the present application have at least one or more of the following beneficial effects:
[0034] The present application performs PLP packaging on incoming wafers without copper pillars, generates positioning drawings for the chip and its pins, and laser drills the plastic-sealed chip according to the drawings to expose the chip pins, thereby enabling circuit processing to be performed and completing the chip packaging structure. Compared with the existing PLP packaging process that is aimed at wafers with existing copper pillars, the PLP packaging process of the present application can directly package wafers without copper pillars, eliminating the need to make copper pillars after the wafer leaves the factory, saving a lot of chip packaging time, and improving the overall chip packaging efficiency; at the same time, chips without copper pillars are easy to absorb, transfer and fix during the production process, reducing the chip offset problem during the packaging process, improving the accuracy of chip circuit production, and improving product production quality.
[0035] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The disclosure of the present application will become more easily understood with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present application. In addition, similar numbers in the drawings are used to represent similar components, among which:
[0037] Figure 1It is a schematic flow chart of the main steps of a copper pillar-free wafer PLP packaging method according to an embodiment of the present application;
[0038] Figure 2 is a schematic diagram of a packaging structure after chip transfer according to an embodiment of the present application;
[0039] Figure 3 is a schematic diagram of a packaging structure during chip scanning according to an embodiment of the present application;
[0040] Figure 4 is a schematic diagram of a packaging structure of a chip after plastic packaging according to an embodiment of the present application;
[0041] Figure 5 is a schematic diagram of a chip packaging structure after the plastic packaging layer is ground according to an embodiment of the present application;
[0042] Figure 6 is a schematic diagram of a top view of a chip packaging structure after a window is opened according to an embodiment of the present application;
[0043] Figure 7 is a schematic diagram of a chip packaging structure after laser drilling according to an embodiment of the present application;
[0044] Figure 8 is a schematic diagram of a chip packaging structure after copper deposition according to an embodiment of the present application;
[0045] Fig. 9 is a schematic diagram of a chip packaging structure after image transfer according to an embodiment of the present application;
[0046] Fig.10 is a schematic diagram of a chip packaging structure after electroplating according to an embodiment of the present application;
[0047] Fig.11 It is a schematic diagram of the chip packaging structure after circuit formation according to an embodiment of the present application.
[0048] The markings in the figure are:
[0049] 100, chip; 101, pin hole; 102, epitaxial hole;
[0050] 200, substrate; 201, double-sided adhesive film; 202, alignment hole;
[0051] 300, plastic sealing layer; 400, seed layer; 500, photoresist film; 600, metal. DETAILED DESCRIPTION
[0052] Some embodiments of the present application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present application and are not intended to limit the protection scope of the present application.
[0053] As described in the background technology, the existing PLP packaging is carried out for wafers that have been made with copper pillars (Bump i ng), that is, the incoming wafers already have copper pillars. The PLP packaging process can directly plastic-encapsulate the chip and then grind it to expose the pins to make the circuit. However, the chip with copper pillars is difficult to absorb during the transfer process, which may cause chip offset problems, thereby affecting the production quality; at the same time, since the existing PLP packaging is for wafers that already have copper pillars, the wafer must first undergo a process for making copper pillars before packaging, which increases the overall packaging cost and time and affects the packaging efficiency. Based on this, the present application proposes a PLP packaging method for copper-free wafers to solve the above problems.
[0054] See attached Figure 1 , Figure 1 FIG. 1 is a schematic flow chart of the main steps of a copper pillar-free wafer PLP packaging method according to an embodiment of the present application. Figure 1 As shown, a copper pillar-free wafer PLP packaging method in an embodiment of the present invention mainly includes the following steps S101 to S106:
[0055] Step S101, providing a copper pillar-free wafer and a substrate, and transferring all chips on the copper pillar-free wafer to the substrate;
[0056] In one embodiment, see Figure 2 The incoming material is a copper-post-free wafer. All chips 100 on the copper-post-free wafer are transferred to a substrate 200 having a double-sided adhesive film 201. That is, when transferring the chips 100, the double-sided adhesive film 201 with strong viscosity is used to adhere the chips to the substrate 200. After the initial adhesion, the chips 100 can be pressed by using a pressure machine to effectively fix the chips 100 on the substrate 200, and no position deviation will occur in the subsequent production process, laying the foundation for subsequent accurate positioning.
[0057] Step S102, obtaining the actual position of the chip and its pins on the substrate, and generating a positioning drawing;
[0058] In one embodiment, see Figure 3, based on the scanning positioning method, the actual position of the chip 100 and its pins on the substrate 200 is obtained. The scanning positioning method can use an optical scanning instrument to scan the chip 100 on the substrate 200, and the actual position drawing can be generated after scanning; however, usually because the chip material usually has a thermal expansion coefficient, when the temperature changes, the size of the chip 100 will also change accordingly. Therefore, the chip 100 may expand and shrink during plastic packaging. At the same time, during the plastic packaging process, due to factors such as pressure extrusion, the chip 100 may produce a certain offset. If the offset and expansion and contraction factors are not considered in the positioning process, it may cause the subsequent copper-free chip positioning and punching position to be inaccurate, and its pins cannot be found, and the circuit production is difficult or impossible. Therefore, the actual position of the chip 100 and the chip pins can be compensated according to the conventional offset value and expansion and contraction value of the chip 100 after plastic packaging, and the final positioning drawing of the chip and its pins is generated to ensure the accuracy of the subsequent positioning drilling.
[0059] Step S103, forming a plastic packaging layer on the substrate to wrap the chip;
[0060] Specifically, refer to Figure 4 The chip 100 is molded and shaped using a molding compound, and a molding layer 300 that wraps the chip 100 is formed on the substrate 200 .
[0061] Step S104, grinding the plastic sealing layer to a preset thickness, wherein the preset thickness is greater than the thickness of the chip;
[0062] Specifically, refer to Figure 5 Since the chip 100 has no lead-out copper pillars, in order to lead out the pins of the chip 100 for easy circuit production, the thickness of the plastic layer 300 should be greater than the thickness of the chip 100 to facilitate subsequent punching to lead out the pins of the chip 100.
[0063] Step S105, laser drilling the plastic packaging layer to expose the pins of the chip according to the positioning drawing;
[0064] In one embodiment, reference Figure 6 , an alignment hole 202 is set on the substrate 200, and a window is opened in the plastic encapsulation layer 300 based on the alignment hole 202 to expose the chip 100 located at the corner of the plastic encapsulation layer 300, wherein in the direction perpendicular to the substrate 200, the area of the plastic encapsulation layer 300 is smaller than the area of the substrate 200, so as to perform alignment window opening, and a laser machine can be used for window opening. Specifically, the alignment hole 202 is located at the corner of the substrate 200, that is, there is an alignment hole 202 at each corner of the four substrates 200, and the corner of the substrate 200 corresponds to the corner of the plastic encapsulation layer 300. The position of the alignment hole 202 and the plastic encapsulation layer 300 is relatively fixed, so the window opening position can be determined by the alignment hole 202, and the four chips 100 located at the corner can be exposed for subsequent positioning and drilling. Reference Figure 7 Based on the alignment result of the graphic frame formed by the pins of the exposed chip 100 and the positioning drawing, the plastic encapsulation layer 300 is laser drilled to form pin holes 101 on the plastic encapsulation layer 300 to expose the pins of all chips. Specifically, a laser drilling machine is used to use the graphic frame formed by multiple pins on the four corner chips as the alignment reference, and the plastic encapsulation layer 300 is drilled in combination with the positioning drawing to expose the pins of other chips, forming the following. Figure 7 structure.
[0065] Step S106: circuit fabrication is performed based on the exposed pins of the chip to complete the final chip packaging.
[0066] In one embodiment, a plasma surface treatment process (Plasma) is used to clean the pin hole 101 of the chip 100 and the surface of the plastic packaging layer 300 to make their surfaces free of pollution. Plasma surface cleaning is mainly based on a large number of active particles generated by plasma discharge. Under certain conditions, these active particles will react with pollutants on the surface of the cleaned object to achieve a cleaning effect.
[0067] In one embodiment, reference Figure 8 , a layer of copper is deposited on the surface of the plastic encapsulation layer 300 to form a seed layer 400; the seed layer 400 is connected to the exposed pins of the chip through the pin holes 101. Chemical copper plating can provide a uniform thin layer as the seed layer 400, which is then electroplated for thickening. Specifically, the seed layer 400 covers the surface of the non-conductive plastic encapsulation layer 300, so that a conductive path can be formed on the wall of the pin hole 101 and the upper surface of the plastic encapsulation layer 300, which serves as a conductive substrate for the subsequent electroplating process. Copper deposition provides a uniform initial conductive layer, so that the electroplated copper can quickly thicken the wire.
[0068] In one possible implementation, reference Fig. 9 , a photoresist film 500 is formed on the seed layer 400 by an image transfer method to perform epitaxial extension on the pin hole 101 to form an epitaxial hole 102. Specifically, after laser drilling, the pin position of the chip 100 is determined, but the pin hole 101 is relatively shallow and small, which is not conducive to the production of the circuit. Image transfer is required to form the photoresist film 500 formed on the seed layer 400 through a photolithography process to epitaxially enlarge the pin hole 101, that is, to form a precise pattern on the photoresist through a photolithography process, and the pin position and shape corresponding to this line of patterns conform to the position and shape of the pin hole 101.
[0069] In one possible implementation, reference Fig.10, a photoresist film 500 is formed on the seed layer 400 by image transfer to perform epitaxy on the pin hole 101. After the epitaxial hole 102 is formed, a circuit is made on the epitaxial hole 102 by electroplating, that is, metal 600 is accurately deposited in the epitaxial hole 102. Metals with good conductivity and corrosion resistance, such as copper, gold or aluminum, need to be selected to ensure electrical performance and mechanical strength; in multi-layer packaging, image transfer and electroplating deposition of metal for pin epitaxy may be performed alternately for many times, and each layer needs to be accurately aligned and deposited. The two together ensure the electrical performance and reliability of the chip package; reference Fig.11 After the circuit is formed, the photoresist film 500 and the seed layer 400 outside the circuit can be removed.
[0070] Based on the above implementation mode, reference Figure 1-Figure 11 , a possible packaging process of the copper pillar-free wafer PLP packaging method of the present application:
[0071] Chip transfer: transfer all chips 100 on the copper pillar-free wafer to a substrate 200 with a double-sided adhesive film 201;
[0072] Chip scanning: Use optical scanning equipment to locate the actual position of the chip 100 and its pins on the substrate 200, and perform position compensation based on the conventional offset value and expansion and contraction value of the chip after plastic packaging to generate a positioning drawing of the chip and its pins;
[0073] Plastic encapsulation: forming a plastic encapsulation layer 300 wrapping the chip 100 on the substrate 200, and performing plastic encapsulation shaping;
[0074] Grinding: Grinding the plastic encapsulation layer 300 to a preset thickness, which is greater than the thickness of the chip 100;
[0075] Opening windows: Using the circular holes on the substrate 200 as the alignment holes 202, a laser machine is used to open windows to expose the chips located in the plastic packaging layer 300 at the four corners of the board;
[0076] Laser drilling: A laser drilling machine is used to form a graphic frame formed by multiple pins on the four corner chips as a positioning reference, and laser drilling is performed in combination with the positioning drawing to form pin holes 101 on the plastic packaging layer 300 to expose the pins of the chip 100;
[0077] Plasma: Use Plasma to clean the pin hole 101 and the surface of the plastic sealing layer 300;
[0078] Copper deposition: depositing a layer of copper on the surface of the plastic packaging layer 300 to form a seed layer 400;
[0079] Circuit production: a photoresist film 500 is formed on the seed layer 400 by image transfer to perform epitaxy on the pin hole 101 to form an epitaxial hole 102; a metal is deposited in the epitaxial hole 102 by electroplating to complete the metal epitaxy of the pin; further, multi-layer circuit production can be performed alternately multiple times by image transfer and electroplating;
[0080] Circuit forming: removing the photoresist film 500 and the seed layer 400 outside the circuit;
[0081] Complete packaging: perform chip surface packaging and remove the substrate 200.
[0082] Based on the above steps S101-S106, the embodiment of the present application performs PLP packaging on incoming wafers without copper pillars, generates positioning drawings for the chips and their pins, and performs laser drilling on the plastic-sealed chips according to the drawings to expose the pins of the chips, so that the circuit process can be carried out to complete the chip packaging structure. Compared with the existing PLP packaging process that is aimed at wafers with existing copper pillars, the PLP packaging process of the present application can directly package wafers without copper pillars, eliminating the need to make copper pillars after the wafers leave the factory, saving a lot of chip packaging time, and improving the overall chip packaging efficiency; at the same time, chips without copper pillars are easy to absorb, transfer and fix during the production process, reducing the chip offset problem during the packaging process, improving the accuracy of chip circuit production, and improving product production quality.
[0083] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art can understand that in order to achieve the effects of the present invention, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present invention.
[0084] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0085] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. A copper pillar-free wafer PLP packaging method, characterized in that: The method comprises: Providing a copper pillar-free wafer and a substrate, and transferring all chips on the copper pillar-free wafer to the substrate; Obtaining the actual position of the chip and its pins on the substrate and generating a positioning drawing; forming a plastic packaging layer on the substrate to wrap the chip; Grinding the plastic sealing layer to a preset thickness, wherein the preset thickness is greater than the thickness of the chip; According to the positioning drawing, laser drilling is performed on the plastic packaging layer to expose the pins of the chip; Circuits are fabricated based on the exposed pins of the chip to complete the final chip packaging.
2. The copper pillar-free wafer PLP packaging method according to claim 1, characterized in that: The step of transferring all the chips on the copper-post-free wafer to the substrate comprises: transferring all the chips on the copper-post-free wafer to the substrate with a double-sided adhesive film.
3. The copper pillar-free wafer PLP packaging method according to claim 1, characterized in that: The obtaining of the actual position of the chip and its pins on the substrate and generating a positioning drawing includes: Acquiring the actual position of the chip and its pins on the substrate based on scanning positioning; The actual position is compensated according to the conventional offset value and expansion / contraction value of the chip after plastic packaging, and a final positioning drawing of the chip and its pins is generated.
4. The copper pillar-free wafer PLP packaging method according to any one of claims 1 to 3, characterized in that: The step of laser drilling holes in the plastic packaging layer according to the positioning drawing to expose the pins of the chip includes: An alignment hole is arranged on the substrate, and a window is opened in the plastic encapsulation layer based on the alignment hole to expose the chip located at the corner of the plastic encapsulation layer, wherein in a direction perpendicular to the substrate, the area of the plastic encapsulation layer is smaller than the area of the substrate; Based on the alignment result of the graphic frame formed by the pins of the exposed chips and the positioning drawing, the plastic packaging layer is laser drilled to form pin holes on the plastic packaging layer to expose the pins of all chips.
5. The copper pillar-free wafer PLP packaging method according to claim 4, characterized in that: The alignment hole is located at a corner of the substrate, and the corner of the substrate corresponds to the corner of the plastic packaging layer.
6. The copper pillar-free wafer PLP packaging method according to claim 4, characterized in that: The circuit manufacturing based on the exposed pins of the chip includes: using a plasma surface treatment process to clean the pin holes and the surface of the plastic packaging layer.
7. The copper pillar-free wafer PLP packaging method according to claim 4, characterized in that: The circuit manufacturing based on the exposed pins of the chip includes: depositing a layer of copper on the surface of the plastic packaging layer to form a seed layer; the seed layer is connected to the exposed pins of the chip through the pin holes.
8. The copper pillar-free wafer PLP packaging method according to claim 7, characterized in that: The circuit manufacturing based on the exposed pins of the chip also includes: forming a photoresist film on the seed layer by image transfer to perform epitaxy on the pin holes to form epitaxial holes.
9. The copper pillar-free wafer PLP packaging method according to claim 8, characterized in that: The circuit fabrication based on the exposed pins of the chip further includes: fabricating the circuit on the epitaxial hole by electroplating, and removing the photoresist film and the seed layer outside the circuit after the circuit is formed.