Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device and a manufacturing method thereof, including: providing a substrate, wherein a preset area for forming an isolation trench is included in the substrate, and the top corner on one side of the substrate close to the preset area is a right angle; performing amorphous ion implantation on the preset area to form an amorphous ion implantation area on one side close to the substrate surface in the preset area, the amorphous ion implantation area extends into the substrate on both sides of the preset area, and makes the top corner rounded; oxidizing the amorphous ion implantation area to form a first oxide layer; removing a part of the first oxide layer located above the preset area, and removing the substrate in the preset area to form the isolation trench, the top corner is located on both sides of the top opening of the isolation trench, and the remaining first oxide layer covers the top corner. The present application reduces or avoids the probability of forming recessed defects in the shallow trench isolation structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In a general semiconductor manufacturing process, an etching process is usually immediately performed after an oxide layer and a silicon nitride layer are deposited on a silicon substrate to form a shallow trench isolation (STI) structure in the silicon substrate. Then, an insulating oxide layer is filled in the shallow trench isolation structure first, and then the silicon nitride layer on the silicon substrate is removed, so that a part of the insulating oxide layer located in the top corner region of the shallow trench isolation structure is exposed.

[0003] However, when a part of the insulating oxide layer located in the top corner region of the shallow trench isolation structure is exposed, during the subsequent wet etching process (Wet), hydrofluoric acid (HF) will consume the insulating oxide layer (the material of the insulating oxide layer is, for example, SiO2) at the top corner region and cause a divot to form in the top corner region of the shallow trench isolation structure. When there is a divot in the top corner region of the shallow trench isolation structure, polycrystalline silicon (Poly) residues are likely to be generated in the divot during the subsequent polycrystalline silicon (Poly) manufacturing process, or other side effects (SideEffect) may occur, thus seriously affecting the yield and stability of the semiconductor device. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof, which reduce or avoid the probability of divot defects in the shallow trench isolation structure and improve the yield and stability of the semiconductor device.

[0005] The present application provides a manufacturing method of a semiconductor device, including:

[0006] Providing a substrate, wherein a preset area for forming isolation trenches is included in the substrate, and the top corner on one side of the substrate close to the preset area is a right angle;

[0007] Performing amorphizing ion implantation into the preset area to form an amorphizing ion implantation area on one side of the preset area close to the substrate surface, the amorphizing ion implantation area extending into the substrate on both sides of the preset area and rounding the top corner;

[0008] Oxidizing the amorphizing ion implantation area and forming a first oxide layer;

[0009] Remove the portion of the first oxide layer located above the preset region, and remove the substrate within the preset region to form the isolation trench. The top corner is located on both sides of the top opening of the isolation trench, and the remaining first oxide layer covers the top corner.

[0010] In one embodiment, the process of performing amorphizing ion implantation into the preset region to form an amorphizing ion implantation region on one side close to the substrate surface within the preset region includes:

[0011] Perform a first ion implantation process with a first implantation angle in the preset region to form a first ion implantation region;

[0012] Perform a second ion implantation process with a second implantation angle in the preset region to form a second ion implantation region. The amorphizing ion implantation region includes the first ion implantation region and the second ion implantation region;

[0013] Wherein, the inclination direction of the first implantation angle is the same as the magnitude of the second implantation angle but the inclination directions are opposite, and the first ion implantation region and the second ion implantation region at least partially overlap.

[0014] In one embodiment, along the direction perpendicular to the surface of the substrate and deep into the substrate, the cross-sectional width of the first ion implantation region and the cross-sectional width of the second ion implantation region gradually decrease.

[0015] In one embodiment, the amorphizing ions implanted during the amorphizing ion implantation process include germanium ions.

[0016] In one embodiment, use a furnace tube oxidation process to oxidize the amorphizing ion implantation region to form the first oxide layer;

[0017] During the process of oxidizing the amorphizing ion implantation region to form the first oxide layer, a portion on the surface side of the substrate is oxidized together and forms a part of the first oxide layer.

[0018] In one embodiment, along the direction perpendicular to the surface of the substrate, the cross-sectional shape of the top corner is arc-shaped.

[0019] In one embodiment, after forming the isolation trench, the manufacturing method of the semiconductor device further includes;

[0020] Fill the isolation trench to form a second oxide layer to form a shallow trench isolation structure including the isolation trench and the oxide layer. The oxide layer includes the second oxide layer and the portion of the first oxide layer located above the top corner;

[0021] Remove a part of the oxide layer on the side away from the isolation trench to expose the substrate on the side of the top corner away from the isolation trench, and the remaining oxide layer fills the isolation trench.

[0022] In one embodiment, after forming the first oxide layer and before forming the isolation trench, the manufacturing method of the semiconductor device further includes:

[0023] Form a hard mask layer on the first oxide layer;

[0024] The process of removing the part of the first oxide layer above the preset area further includes: removing the part of the hard mask layer above the preset area, so that the isolation trench penetrates through the hard mask layer;

[0025] After filling and forming a second oxide layer in the isolation trench and before removing the part of the oxide layer on the side away from the isolation trench, the manufacturing method of the semiconductor device further includes:

[0026] Remove the hard mask layer.

[0027] Correspondingly, the present application also provides a semiconductor device, including:

[0028] A substrate;

[0029] An isolation trench located in the substrate, and the substrate on both sides of the isolation trench is provided with a smoothed top corner;

[0030] A first oxide layer located on the substrate, and the first oxide layer covers the top corner.

[0031] In one embodiment, the semiconductor device further includes:

[0032] A second oxide layer located in the isolation trench, and the surface of the second oxide layer is higher than the surface of the first oxide layer, or the surface of the second oxide layer is flush with the surface of the first oxide layer.

[0033] An unexpected effect of the present application is that: by forming an amorphous ion implantation region in a preset area of the substrate, the top corner near the preset area in the substrate is smoothed; by oxidizing the amorphous ion implantation region to form a first oxide layer and forming an isolation trench in the preset area, the top corners on both sides of the isolation trench are smoothed and covered by the first oxide layer, reducing or avoiding the risk of depression defects in the subsequently formed shallow trench isolation structure, thereby helping to improve the performance and stability of the semiconductor device. Description of the Drawings

[0034] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0035] Figure 1 It is a schematic structural diagram corresponding to the step of providing a semiconductor substrate in the manufacturing method of the STI structure in the related art.

[0036] Figure 2 It is a schematic structural diagram corresponding to the step of forming a trench in the manufacturing method of the STI structure in the related art.

[0037] Figure 3 It is a schematic structural diagram corresponding to the step of filling an isolation layer in the trench in the manufacturing method of the STI structure in the related art.

[0038] Figure 4 It is a schematic structural diagram corresponding to the step of removing the silicon nitride layer in the manufacturing method of the STI structure in the related art.

[0039] Figure 5 It is a schematic structural diagram corresponding to the step of etching the oxide layer and the isolation layer to form the STI structure in the manufacturing method of the STI structure in the related art.

[0040] Figure 6 It is a flowchart of the manufacturing method of the semiconductor device provided in one embodiment of the present application.

[0041] Figure 7 It is a schematic structural diagram corresponding to the step of providing a substrate in the manufacturing method of the semiconductor device provided in one embodiment of the present application.

[0042] Figure 8 It is a schematic structural diagram corresponding to the process of performing amorphizing ion implantation in the manufacturing method of the semiconductor device provided in one embodiment of the present application.

[0043] Figure 9 It is a schematic structural diagram corresponding to the step of forming an amorphizing ion implantation region in the manufacturing method of the semiconductor device provided in one embodiment of the present application.

[0044] Figure 10 It is a schematic structural diagram corresponding to the step of growing a first oxide layer on the amorphizing ion implantation region and the substrate in the manufacturing method of the semiconductor device provided in one embodiment of the present application.

[0045] Figure 11Schematic structural diagram corresponding to the step of forming a hard mask layer on a first oxide layer in the manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0046] Figure 12 Schematic structural diagram corresponding to the step of forming an isolation trench in the manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0047] Figure 13 Schematic structural diagram corresponding to the step of filling and forming a second oxide layer in the isolation trench in the manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0048] Figure 14 Schematic structural diagram corresponding to the step of removing the hard mask layer in the manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0049] Figure 15 Schematic structural diagram corresponding to the step of etching the first oxide layer and the second oxide layer and forming a shallow trench isolation structure in the manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0050] Wherein, the reference numerals include: 100 - semiconductor substrate; 110 - oxide layer; 120 - silicon nitride layer; 130 - photoresist layer; 131 - anti-reflection layer; 140 - trench; 150 - isolation layer; 151 - recessed defect; X1 - STI structure; 200 - substrate; 200a - preset area; 201 - amorphized ion implantation area; 201a - first ion implantation area; 201b - second ion implantation area; 210 - mask layer; 220 - first oxide layer; 230 - hard mask layer; 240 - isolation trench; 250 - second oxide layer; X2 - shallow trench isolation structure; B - top corner. Detailed Description of the Embodiment

[0051] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0053] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be denoted as the second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0054] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatial relationship terms include different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0055] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0056] In the manufacturing method of general semiconductor devices, recessed defects are likely to form at the top corner regions of the STI structure, which have a negative impact on the performance of semiconductor devices. Exemplarily, the formation process of the recessed defects can be referred to Figures 1 to 5 the manufacturing process of the semiconductor devices described above.

[0057] First, refer to Figure 1 , a semiconductor substrate 100 is provided, an oxide layer 110 and a silicon nitride layer 120 are covered on the semiconductor substrate 100, and a patterned photoresist layer 130 is formed on the silicon nitride layer 120. Optionally, other semiconductor structures are formed between the silicon nitride layer 120 and the patterned photoresist layer 130. For example, an anti-reflection layer 131 can be formed between the silicon nitride layer 120 and the patterned photoresist layer 130 to reduce light reflection.

[0058] Next, refer to Figure 2 , the silicon nitride layer 120, the oxide layer 110 and the semiconductor substrate 100 are etched using the patterned photoresist layer 130 as a mask to form a trench 140 that penetrates the silicon nitride layer 120 and the oxide layer 110 and extends into the semiconductor substrate 100. Subsequently, the patterned photoresist layer 130 is removed.

[0059] Subsequently, refer to Figure 3 , an isolation layer 150 is filled in the trench 140, and the isolation layer 150 extends to cover the silicon nitride layer 120 on both sides of the trench 140. Optionally, the material of the isolation layer 150 includes silicon oxide or other oxide materials.

[0060] Next, refer to Figure 4 , the silicon nitride layer 120, a part of the oxide layer 110 and the part of the isolation layer 150 located on the silicon nitride layer 120 are etched and removed; refer to Figure 5 , the remaining oxide layer 110 and a part of the isolation layer 150 are removed by a wet etching process to expose the semiconductor substrate 100 on both sides of the trench 140 and form an STI structure X1, where the STI structure X1 includes the trench 140 and the isolation layer 150.

[0061] However, after etching away the silicon nitride layer 120, part of the oxide layer 110, and part of the isolation layer 150, since the thickness of the remaining oxide layer 110 is less than the thickness of the surface portion of the isolation layer 150 that is higher than the semiconductor substrate 100, during the subsequent wet etching process, the oxide layer 110 will be removed prior to the isolation layer 150, exposing the top corner of the trench 140. During the subsequent wet etching process, the top and side walls of the portion of the isolation layer 150 that is higher than the semiconductor substrate 100 are etched, resulting in the formation of a recessed defect 151 at the top corner. If the depth of the recessed defect 151 is too deep, problems such as polysilicon residue are likely to occur during the subsequent polysilicon (Poly) process, and other side effects may also occur, which may even seriously affect the performance stability of the semiconductor device in severe cases.

[0062] To solve the above problems, the present application provides a semiconductor device and a manufacturing method thereof, which helps to reduce or avoid the probability of recesses appearing at the top corners of the shallow trench isolation structure, thereby improving the yield and stability of the semiconductor device.

[0063] Figure 6 The flowchart of the manufacturing method of the semiconductor device provided by one embodiment of the present application. Refer to Figure 6 One embodiment of the present application provides a manufacturing method of a semiconductor device, which includes the following steps S01 to S04.

[0064] Step S01: Provide a substrate, the substrate includes a preset area for forming isolation trenches, and the top corner on the side of the substrate close to the preset area is a right angle.

[0065] Step S02: Perform amorphizing ion implantation on the preset area to form an amorphizing ion implantation area on the side close to the substrate surface within the preset area. The amorphizing ion implantation area extends into the substrate on both sides of the preset area and rounds the top corner.

[0066] Step S03: Oxidize the amorphizing ion implantation area to form a first oxide layer.

[0067] It should be noted that since an amorphizing ion implantation area is formed on the side close to the substrate surface within the preset area in step S02, and the amorphizing ion implantation area extends into the substrate on both sides of the preset area and rounds the top corner, accordingly, the portion of the amorphizing ion implantation area that extends into the substrate covers the top corner. Correspondingly, the first oxide layer formed by oxidizing the amorphizing ion implantation area also covers the above top corner.

[0068] Step S04: Remove the part of the first oxide layer above the preset area, and remove the substrate within the preset area to form the isolation trench. The top corners are located on both sides of the top opening of the isolation trench, and the remaining first oxide layer covers the top corners. It should be noted that when the first oxide layer covers the top corners, the first oxide layer can play a protective role in the subsequent process of forming the shallow trench isolation structure, thereby reducing or avoiding the generation of depression defects in the oxide layer of the shallow trench isolation structure.

[0069] The manufacturing method of the semiconductor device as described above rounds the top corners near the preset area in the substrate by forming an amorphized ion implantation area within the preset area of the substrate; by oxidizing the amorphized ion implantation area to form a first oxide layer and forming an isolation trench within the preset area, the top corners on both sides of the isolation trench are rounded and covered by the first oxide layer, reducing or avoiding the risk of generating depression defects in the subsequently formed shallow trench isolation structure, thereby contributing to improving the performance and stability of the semiconductor device.

[0070] Refer to Figure 7 , in one embodiment, a substrate 200 is provided. The substrate 200 includes a preset area 200a for forming an isolation trench, and the top corner B on one side of the substrate 200 close to the preset area 200a is a right angle. Optionally, the substrate 200 is a silicon substrate.

[0071] Refer to Figure 8 , in one embodiment, amorphized ion implantation is performed into the preset area 200a of the substrate 200 to form an amorphized ion implantation area 201 on one side of the preset area 200a close to the surface of the substrate 200. The amorphized ion implantation area 201 extends into the substrate 200 on both sides of the preset area 200a and rounds the top corner B.

[0072] Exemplarily, refer to Figure 8 and Figure 9 , the process of forming the amorphized ion implantation area 201 in the preset area 200a of the substrate 200 includes: forming a patterned mask layer 210 on the substrate, and the patterned mask layer 210 exposes the preset area 200a in the substrate 200; using the mask layer 210 as a mask to perform a first ion implantation process with a first implantation angle in the preset area 200a (i.e., Figure 8 the process represented by the solid arrow in Figure 8The process indicated by the dashed arrow in the figure) is performed to form a second ion implantation region 201b. The amorphized ion implantation region 201 includes the first ion implantation region 201a and the second ion implantation region 201b; the mask layer 210 is removed. Optionally, the tilt direction of the first implantation angle is opposite to the tilt direction of the second implantation angle, the magnitudes of the first implantation angle and the second implantation angle are the same, and the first ion implantation region 201a and the second ion implantation region 201b partially overlap.

[0073] Continue to refer to Figure 8 and Figure 9 In one embodiment, along the direction perpendicular to the surface of the substrate 200, the cross-sectional width of the first ion implantation region 201a and the cross-sectional width of the second ion implantation region 201b gradually decrease, and the cross-sectional morphologies of the first ion implantation region 201a and the second ion implantation region 201b are in a cone shape with the tip facing downwards.

[0074] In other embodiments of the present application, the relative positions and morphologies of the first ion implantation region and the second ion implantation region can be adjusted according to actual needs. For example, the first ion implantation region and the second ion implantation region can completely overlap, and the relevant parameters of the first ion implantation process and the second ion implantation process can be adjusted according to actual needs, as long as it is ensured that "the amorphized ion implantation region can extend into the substrate on both sides of the preset region and smooth the top corners in the substrate", and the present application does not limit this.

[0075] In other embodiments of the present application, the amorphized ion implantation region can be formed by several ion implantation processes, and the specific morphology of the amorphized ion implantation region can be adjusted by adjusting the process parameters of each ion implantation process to form an amorphized ion implantation region that meets the process requirements.

[0076] In one embodiment, the amorphized ion is an ion that can perform ion implantation in the substrate to form an amorphized ion implantation region. The amorphized ions include germanium (Ge) ions, arsenic (As) ions, boron (B) ions, phosphorus (P) ions, etc. Those skilled in the art can select appropriate amorphized ions according to actual process requirements for the ion implantation process to form an amorphized ion implantation region.

[0077] Refer to Figure 10, in one embodiment, the amorphized ion implantation region 201 is oxidized to form a first oxide layer 220. Optionally, the first oxide layer 220 is formed by a furnace oxidation process. Optionally, during the process of oxidizing the amorphized ion implantation region 201 by the furnace oxidation process to form the first oxide layer 220, a part of the substrate 200 on one side of the surface of the substrate 200 is oxidized together and forms a part of the first oxide layer 220. That is, the first oxide layer 220 is formed within the amorphized ion implantation region 201 and extends to cover the surface of the substrate 200.

[0078] It should be noted that since the thickness of the grown first oxide layer 220 is positively correlated with the implantation depth and implantation concentration of the amorphized ion implantation region 201 in the substrate 200, therefore, the thickness of the part of the first oxide layer 220 formed within the amorphized ion implantation region 201 is greater than the thickness of the part formed on the substrate 200. At the same time, since the amorphized ion implantation region covers the top corners B on both sides of the preset region 200a, therefore, the part of the first oxide layer 220 located above the top corner B is also thicker than the part of the first oxide layer 220 located on the surface of the substrate 200, which is beneficial to protecting other structures in the isolation trench from damage during the subsequent etching process by using the first oxide layer.

[0079] Refer to Figure 11 , in one embodiment, after forming the first oxide layer 220, the manufacturing method of the semiconductor device further includes forming a hard mask layer 230 on the first oxide layer 220. Optionally, the material of the hard mask layer 230 includes silicon nitride.

[0080] Continue to refer to Figure 11 , in one embodiment, the hard mask layer 230 is formed on the first oxide layer 220 by a chemical vapor deposition process. It should be noted that since the hard mask layer 230 is formed by a deposition process, therefore, the top surface morphology of the hard mask layer 230 inherits the top surface morphology of the first oxide layer 220.

[0081] Refer to Figure 12 , in one embodiment, the part of the first oxide layer 220 located above the preset region 200a is removed, and the substrate 200 within the preset region 200a is removed to form an isolation trench 240. At this time, the top corner B is located on both sides of the top opening of the isolation trench 240, and the remaining first oxide layer 220 covers the top corner B. Optionally, in the direction perpendicular to the surface of the substrate 200, the cross-sectional shape of the top corner B is arc-shaped.

[0082] It should be noted that during the formation of the isolation trench, the part of the first oxide layer above the preset area is removed, so that a part of the remaining first oxide layer is above the top corner, and the other part covers the substrate surface. At the same time, since the part of the first oxide layer above the top corner is thicker than the part of the first oxide layer on the substrate surface, and the first oxide layer can play a protective role in subsequent process steps, it helps to reduce or avoid the formation of recessed defects in the subsequently formed shallow trench isolation structure.

[0083] Continuing to refer to FIG. 12, in one embodiment, a dry etching process is used to remove a part of the first oxide layer 220 and the substrate 200 within the preset area 200a to form an isolation trench 240. At the same time, when a hard mask layer 230 is formed on the first oxide layer 220, the above dry etching process also removes the part of the hard mask layer 230 above the preset area, so as to avoid removing the parts of the first oxide layer 220 on both sides of the preset area during the formation of the isolation trench 240, so as to carry out subsequent process steps.

[0084] Refer to Figure 13 , in one embodiment, a second oxide layer 250 is filled in the isolation trench 240 to form a shallow trench isolation structure X2 including the isolation trench 240 and an oxide layer. The oxide layer includes the second oxide layer 250 and the part of the first oxide layer 220 above the top corner B (that is, the oxide layer includes Figure 13 the second oxide layer 250 in FIG. and the part of the first oxide layer 220 within the dashed box). Optionally, the material of the second oxide layer 250 includes silicon oxide.

[0085] Continuing to refer to Figure 13 , in one embodiment, the process of forming the second oxide layer 250 includes: filling an oxidation material (not shown in the figure) in the isolation trench 240, and the oxidation material extends to cover other semiconductor structures on both sides of the isolation trench 240, and performing a planarization process on the oxidation material to form the second oxide layer 250 that fills the isolation trench 240. Optionally, a chemical vapor deposition process (Chemical Vapor Deposition, CVD) is used to fill the oxidation material; a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP) is used for the planarization process.

[0086] It should be noted that when a hard mask layer 230 is formed on the first oxide layer 220, the hard mask layer 230 can protect the first oxide layer 220 during the planarization process of the second oxide layer 250, so as to ensure that the first oxide layer 220 has a sufficient thickness to protect the shallow trench isolation structure from damage during subsequent wet etching processes.

[0087] Referring to Figure 13 and Figure 14 When a hard mask layer 230 is formed on the first oxide layer 220, after the second oxide layer 250 is formed, the method for manufacturing a semiconductor device further includes: removing the hard mask layer 230.

[0088] Referring to Figure 14 and Figure 15 In one embodiment, a part of the oxide layer on the side away from the isolation trench 240 is removed to expose the substrate 200 on the side of the top corner B away from the isolation trench 240, and the remaining oxide layer (including the second oxide layer 250 and the first oxide layer 220) fills the isolation trench 240. Optionally, a wet etching process (Wet Etch) is used to remove the part of the oxide layer on the side away from the isolation trench 240, so as to expose the substrates 200 on both sides of the shallow trench isolation structure X2.

[0089] It should be noted that during the above wet etching process, the overall thickness of the first oxide layer 220 and the thickness of the second oxide layer 250 both decrease, and the first oxide layer 220 always covers the top corner B and the side wall of the second oxide layer 250 on the side close to the top corner B during the above wet etching process, so as to reduce or avoid the risk of recessed defects in the part of the oxide layer located in the isolation trench 240.

[0090] Continuing to refer to Figure 15 In one embodiment, along the direction perpendicular to the surface of the substrate 200, the cross-sectional width of the oxide layer (i.e., the combined structure of the first oxide layer 220 and the second oxide layer 250) shows a trend of increasing first and then decreasing, and the cross-sectional width of the part of the oxide layer located above the top corner region B is the largest, and the part of the oxide layer located above the top corner B (i.e., the first oxide layer 220) can protect the second oxide layer 250 from damage during the etching process related to the shallow trench isolation structure X2.

[0091] Correspondingly, the present application also provides a semiconductor device. Referring to Figure 15 In one embodiment, the semiconductor device includes a substrate 200, an isolation trench 240, and a first oxide layer 220. Among them, the isolation trench 240 is located in the substrate 200, and the substrates 200 on both sides of the isolation trench 240 are provided with a smoothed top corner B. The first oxide layer 220 is located on the substrate 200, and the first oxide layer 220 covers the top corner B.

[0092] It should be noted that by providing rounded top corners on the substrate on both sides of the isolation trench, leakage of semiconductor devices can be reduced or avoided. On this basis, by providing a first oxide layer covering the top corners, the relevant structures of the isolation trench can be protected by the first oxide layer from damage in subsequent processes, thereby reducing or avoiding the risk of recess defects in the subsequently formed shallow trench isolation structure, and effectively improving the performance and stability of the semiconductor device.

[0093] Continuing to refer to Figure 15 , in one embodiment, the semiconductor device further includes a second oxide layer 250 located in the isolation trench 240, and the second oxide layer 250 at least fills the isolation trench 240. Optionally, the surface of the second oxide layer 250 is higher than the surface of the first oxide layer 220, or the surface of the second oxide layer 250 is flush with the surface of the first oxide layer 220. At this time, the isolation trench 240, the first oxide layer 220, and the second oxide layer 250 together form the shallow trench isolation structure X2 of the semiconductor device.

[0094] In one embodiment, the material of the substrate 200 includes silicon material; the materials of the first oxide layer 220 and the second oxide layer 250 both include silicon oxide.

[0095] Comparing Figure 5 and Figure 15 it can be seen that in a general semiconductor device, the oxide layer 110 in the STI structure X1 is removed prior to the isolation layer 150, resulting in the exposure of the top corners of the trench 140, and the top and side walls of the portion of the isolation layer 150 that is higher than the semiconductor substrate 100 are damaged during the subsequent etching process, thereby forming a recess defect 151 at the top corners; while in the semiconductor device provided in the present application, by providing rounded top corners B and providing a first oxide layer 220 on the top corners B, the first oxide layer 220 is used to protect the second oxide layer 250 from damage during the etching process related to the shallow trench isolation structure X2, effectively reducing or avoiding the risk of recess defects in the shallow trench isolation structure X2.

[0096] In one embodiment, the above-mentioned semiconductor device is fabricated using the manufacturing method of the semiconductor device provided in the present application. In other embodiments of the present application, the semiconductor device can also be fabricated using other methods according to actual needs, and the manufacturing method of the semiconductor device can also be used to fabricate other semiconductor structures with the same or similar structures to improve the performance and stability of the semiconductor device.

[0097] The unexpected effect of this application is that by forming an amorphized ion implantation region within a preset region of the substrate, the top corners near the preset region within the substrate are smoothed; by oxidizing the amorphized ion implantation region to form a first oxide layer and forming an isolation trench within the preset region, the top corners on both sides of the isolation trench are smoothed and covered by the first oxide layer, reducing or avoiding the risk of recessed defects in the subsequently formed shallow trench isolation structure, thereby contributing to improving the performance and stability of semiconductor devices.

[0098] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0099] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0100] The above-described embodiments merely represent several implementation manners of this application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application patent shall be subject to the appended claims.

Claims

1. A method of manufacturing a semiconductor device, characterized in that, Including: Providing a substrate, wherein a preset area for forming isolation trenches is included in the substrate, and the top corner on one side of the substrate close to the preset area is a right angle; Performing amorphizing ion implantation on the preset area to form an amorphizing ion implantation area on one side of the preset area close to the substrate surface, the amorphizing ion implantation area extending into the substrate on both sides of the preset area and rounding the top corner; Oxidizing the amorphizing ion implantation area to form a first oxide layer, and the thickness of the first oxide layer is positively correlated with the implantation depth and implantation concentration of the amorphizing ion implantation area; Forming a hard mask layer on the first oxide layer; Removing the parts of the first oxide layer and the hard mask layer located above the preset area, and removing the substrate within the preset area to form the isolation trench, the top corner being located on both sides of the top opening of the isolation trench, and the remaining first oxide layer covering the top corner, the part of the first oxide layer located above the top corner being thicker than the part of the first oxide layer located on the substrate surface; Wherein, the amorphizing ion implantation area includes a first ion implantation area and a second ion implantation area that at least partially overlap, and in the direction perpendicular to the surface of the substrate, the cross-sectional morphologies of the first ion implantation area and the second ion implantation area are in the shape of a cone with the tip facing downwards.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The process of performing amorphizing ion implantation on the preset area to form an amorphizing ion implantation area on one side of the preset area close to the substrate surface includes: Performing a first ion implantation process with a first implantation angle on the preset area to form a first ion implantation area; Performing a second ion implantation process with a second implantation angle on the preset area to form a second ion implantation area, the amorphizing ion implantation area including the first ion implantation area and the second ion implantation area; Wherein, the inclination direction of the first implantation angle is the same as the magnitude of the second implantation angle and the inclination directions are opposite.

3. The manufacturing method of the semiconductor device according to claim 2, characterized in that, In the direction perpendicular to the surface of the substrate, the cross-sectional width of the first ion implantation area and the cross-sectional width of the second ion implantation area gradually decrease.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The amorphizing ions implanted during the amorphizing ion implantation process include germanium ions.

5. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Using a furnace tube oxidation process to oxidize the amorphizing ion implantation area to form the first oxide layer; During the process of oxidizing the amorphizing ion implantation area to form the first oxide layer, a part on the side of the surface of the substrate is oxidized together to form a part of the first oxide layer.

6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, In the direction perpendicular to the surface of the substrate, the cross-sectional shape of the top corner is arc-shaped.

7. The manufacturing method of the semiconductor device according to claim 1, characterized in that, After forming the isolation trench, the manufacturing method of the semiconductor device further includes; Filling the isolation trench to form a second oxide layer to form a shallow trench isolation structure including the isolation trench and the oxide layer, the oxide layer including the second oxide layer and the part of the first oxide layer located above the top corner; Remove a portion of the oxide layer on the side away from the isolation trench to expose the substrate on the side of the top corner away from the isolation trench, and the remaining oxide layer fills the isolation trench.

8. The method for manufacturing a semiconductor device according to claim 7, wherein after filling and forming a second oxide layer in the isolation trench and before removing the portion of the oxide layer on the side away from the isolation trench, the method for manufacturing the semiconductor device further includes: removing the hard mask layer.

9. A semiconductor device manufactured by using the manufacturing method of the semiconductor device according to any one of claims 1 to 8, characterized in that, comprising: a substrate; an isolation trench located in the substrate, and the substrate on both sides of the isolation trench is provided with a rounded top corner; a first oxide layer located on the substrate, and the first oxide layer covers the top corner, and the portion of the first oxide layer above the top corner is thicker than the portion of the first oxide layer on the substrate surface.

10. The semiconductor device according to claim 9, wherein, The semiconductor device further includes: a second oxide layer located in the isolation trench, and the surface of the second oxide layer is higher than the surface of the first oxide layer, or the surface of the second oxide layer is flush with the surface of the first oxide layer.

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