Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure, and relates to the field of semiconductors, and the manufacturing method comprises the steps: providing a semiconductor substrate which comprises a source region and a drain region, and the source region and the drain region are silicon-germanium semiconductor layers; an interlayer dielectric layer covering the semiconductor substrate is formed, a first through hole in the interlayer dielectric layer exposes the source region, and a second through hole in the interlayer dielectric layer exposes the drain region; carrying out pre-amorphization treatment on the surfaces of the source region and the drain region by adopting silicon ions to form an amorphous layer; performing ozone treatment on the surface of the amorphous layer to form a barrier diffusion layer; the amorphous layer is subjected to metallization processing, a silicon germanide layer is formed, a first metal structure is formed in the through hole, the first metal structure comprises a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole, so that uniform germanium silicide is formed, the contact characteristic is improved, and the performance of the device is improved. The problem that germanium-rich germanium-silicon crystal grains and germanium-deficient Co (Si < 1-x > Ge < x >) island structures are easy to appear in the silicon germanization process is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] As the feature size of advanced integrated circuits shrinks rapidly towards the deep submicron level, in order to reduce the RC delay of interconnects and improve reliability, W and Cu are widely used in contact plugs in MOL (Middle-of-Line) and interconnects in BEOL (Back-End-of-Line), respectively. However, as the feature size of integrated circuits enters the 7 / 5 nanometer and below technology nodes, the parasitic resistance of semiconductor devices using W or Cu as contact plugs or interconnects has exceeded their own channel resistance, resulting in a significant increase in the RC delay of interconnects in semiconductor devices, which seriously restricts the improvement of semiconductor device performance.

[0003] When Co is used as a plug or interconnect, it does not require a high-resistivity nucleation layer, has a smaller electron mean free path and a higher melting point, and is not as sensitive to size effects as W and Cu. Therefore, compared with W and Cu, Co has a slower increase in resistivity in a reduced through hole and is one of the most promising interconnect metals to replace W and Cu. However, when Co is used as a plug in a semiconductor device including a silicon germanium source and drain region, germanium-rich silicon germanium grains and germanium-deficient Co (Si1-xGex) island structures are likely to appear between the Co plug and the silicon germanium source and drain region, which deteriorates the interface morphology and interface characteristics of the semiconductor layer and the metal layer. Summary of the invention

[0004] In view of the above problems, the present application provides a method for manufacturing a semiconductor structure and a semiconductor structure to reduce the RC delay of interconnection lines in semiconductor devices, improve the performance of semiconductor devices, and solve the problem that germanium-rich silicon germanium grains and germanium-deficient Co (Si1-xGex) island structures are prone to appear at the interface between the semiconductor layer and the metal layer, and improve the interface morphology and interface characteristics of the semiconductor layer and the metal layer. The specific scheme is as follows:

[0005] A method for manufacturing a semiconductor structure, the method comprising:

[0006] Providing a semiconductor substrate, wherein the semiconductor substrate comprises a source region and a drain region, a gate structure is formed on the surface of the semiconductor substrate, and the source region and the drain region are silicon germanium semiconductor layers;

[0007] forming an interlayer dielectric layer covering the semiconductor substrate and the gate structure, wherein the interlayer dielectric layer has a plurality of through holes, the plurality of through holes including a first through hole and a second through hole, the first through hole exposing the source region, and the second through hole exposing the drain region;

[0008] Using silicon ions, pre-amorphizing the surfaces of the source region and the drain region to form an amorphous layer at the bottom layer of the through hole;

[0009] Performing ozone treatment on the surface of the amorphous layer to form a diffusion barrier layer;

[0010] The amorphous layer is metallized to undergo a silicon-germanium reaction to form a silicon-germanium layer, and a first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole.

[0011] Optionally, the amorphous layer is subjected to metallization treatment so that the amorphous layer undergoes a silicon-germanium reaction to form a silicon-germanium layer, and a first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole, including:

[0012] forming a Co-Ti alloy layer covering at least the bottom of the through hole and the sidewall of the through hole;

[0013] forming a Co metal layer filling the through hole on a side of the Co-Ti alloy layer away from the through hole;

[0014] The Co-Ti alloy layer and the amorphous layer are heat treated so that the amorphous layer undergoes a silicon-germanium reaction to form a silicon-germanium layer at the bottom of the through hole and a first metal structure located in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole.

[0015] Optionally, heat treating the Co-Ti alloy layer and the amorphous layer includes:

[0016] The Co-Ti alloy layer and the amorphous layer are heat treated at a preset temperature for a preset time, wherein the preset temperature ranges from 400° C. to 600° C., and the preset time ranges from 10s to 60s.

[0017] Optionally, the amorphous layer is subjected to metallization treatment so that the amorphous layer undergoes a silicon-germanium reaction to form a silicon-germanium layer, and a first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole, including:

[0018] forming a contact metal layer on the surface of the through hole;

[0019] Performing heat treatment on the contact metal layer and the amorphous layer so that the amorphous layer undergoes a silicon germanium reaction to form a silicon germanium layer;

[0020] removing a portion of the contact metal layer located on a side wall of the through hole;

[0021] A first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on a sidewall of the through hole and a Co metal layer filling the through hole.

[0022] Optionally, also include:

[0023] forming a second metal structure on a side of the interlayer dielectric layer away from the semiconductor substrate, wherein the second metal structure comprises a stacked Co-Ti alloy layer and a Co metal layer;

[0024] The second metal structure includes a source and a drain. The source is electrically connected to the source region through a portion of the first metal structure located in the first through hole. The drain is electrically connected to the drain region through a portion of the first metal structure located in the second through hole.

[0025] A semiconductor structure comprising:

[0026] A semiconductor substrate, wherein the semiconductor substrate comprises a source region and a drain region, a gate structure is formed on the surface of the semiconductor substrate, and the source region and the drain region are silicon germanium semiconductor layers;

[0027] an interlayer dielectric layer covering the semiconductor substrate and the gate structure, wherein the interlayer dielectric layer has a plurality of through holes, wherein the plurality of through holes include a first through hole and a second through hole, wherein the first through hole exposes the source region, and the second through hole exposes the drain region;

[0028] a silicon germanium layer at the bottom of the through hole;

[0029] a barrier diffusion layer located on a side of the silicon germanium layer away from the semiconductor substrate;

[0030] a first metal structure located in the through hole, the first metal structure comprising a Co-Ti alloy layer located on a sidewall of the through hole and a Co metal layer filling the through hole;

[0031] Wherein, the semiconductor structure is manufactured by using any of the above-mentioned methods for manufacturing a semiconductor structure.

[0032] Optionally, the thickness of the diffusion barrier layer ranges from 5 angstroms to 20 angstroms.

[0033] Optionally, the Co-Ti alloy layer is Co 1-y Ti yThe alloy layer, wherein y is between 0.2 and 0.7; the thickness of the Co-Ti alloy layer ranges from 1 nm to 3 nm.

[0034] The manufacturing method of the semiconductor structure provided in the embodiment of the present application adopts a stack of a Co-Ti alloy layer and a Co metal layer as a through-hole plug. The Co metal layer does not require a nucleation layer with a high resistivity, has a smaller electron mean free path and a higher melting point, and is not as sensitive to size effects as W and Cu, and is suitable for the development trend of integrated circuits with continuously decreasing line widths; moreover, the Co-Ti alloy layer can simultaneously play multiple roles such as a liner layer, a barrier layer, and an adhesion layer, so that under the premise that the top-view area of ​​the through-hole is fixed, the thickness of other film layers between the Co metal layer and the side wall of the through-hole can be reduced, which is beneficial to increasing the filling area of ​​the Co metal layer, thereby facilitating increasing the effective area of ​​the Co interconnection, reducing the resistivity of the through-hole plug, and improving the performance of the semiconductor structure.

[0035] In addition, the method for manufacturing the semiconductor structure provided in the embodiment of the present application, before manufacturing the first metal structure including the stack of the Co-Ti alloy layer and the Co metal layer, firstly uses silicon ions to pre-amorphize the source region and the drain region to form an amorphous layer with a high silicon content, and then performs ozone treatment on the amorphous layer to form a diffusion barrier layer to reduce the out-diffusion of germanium in the source region and the drain region, so that the interface between the semiconductor layer and the metal layer does not have germanium-rich silicon germanium grains and germanium-deficient Co (Si 1- x Ge x ) island structure phenomenon, so that the silicon germanium layer has better interface morphology and interface characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0037] Figure 1 When the Ti content in the Co-Ti alloy layer is 35%, the Co-Ti alloy layer and Si 1-x Ge x A partial cross-sectional view of a structure formed by layers;

[0038] Figure 2 for Figure 1 Schematic diagram of the curve of the content of each element in the structure shown at position A as a function of depth;

[0039] Figure 3 for Figure 1 Schematic diagram of the curve of the content of each element in the structure shown at position B with depth;

[0040] Figure 4 When the Ti content in the Co-Ti alloy layer is 50%, the Co-Ti alloy layer and Si 1-x Ge x A partial cross-sectional view of a structure formed by layers;

[0041] Figure 5 for Figure 4 Schematic diagram of the curve of the content of each element in the structure shown at the C position with depth;

[0042] Figure 6 for Figure 4 Schematic diagram of the curve of the content of each element in the structure shown at position D with depth;

[0043] Figure 7 A flowchart of a method for manufacturing a semiconductor structure provided by one embodiment of the present application;

[0044] Figure 8-Figure 15 A schematic diagram of some structures involved in the manufacturing process of a semiconductor structure provided in one embodiment of the present application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0046] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0047] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0048] As described in the background technology section, the parasitic resistance of semiconductor devices currently using W or Cu as contact plugs or interconnects has exceeded their own channel resistance, resulting in a significant increase in the RC delay of the interconnects in the semiconductor device, which seriously restricts the improvement of the performance of the semiconductor device. When Co is used as a plug in a semiconductor device including a silicon germanium source and drain region, germanium-rich silicon germanium grains and germanium-deficient Co (Si1-xGex) island structures are likely to appear between the Co plug and the silicon germanium source and drain region, which deteriorates the interface morphology and interface characteristics of the semiconductor layer and the metal layer.

[0049] Specifically, when making a W plug, chemical vapor deposition (CVD) is usually used to deposit W, so as to form a W plug with good conformality in a high aspect ratio through hole. However, due to the inherent high stress of the W film and the selective deposition on a specific film, when forming a W plug in a through hole, a stack of an adhesion layer (glue layer) and a nucleation layer (nucleation layer) or a liner layer and a barrier layer (barrier layer) is required between the through hole surface and the W plug. The most commonly used is a stack of a Ti layer and a TiN layer, in which the Ti layer is used as a liner layer and the TiN layer is used as a barrier layer.

[0050] Similar to W, the deposition of Cu interconnects also requires a stack of barrier layers and wetting layers. The most commonly used is a stack of TaN layers and Ta layers, where the TaN layer acts as a barrier layer to prevent Cu ions from diffusing into the surrounding dielectric and forming an oxide layer charge that reduces device life; the Ta layer acts as a wetting layer to promote Cu nucleation and improve Cu's gap filling capability and anti-electromigration properties.

[0051] However, as the line width continues to decrease, electron surface scattering and grain boundary scattering cause the resistivity of W and Cu to increase rapidly due to the size effect.

[0052] Moreover, since the resistivity of Ti / TiN is higher than that of W, under the same trench width condition, reducing the thickness of the Ti / TiN stack can effectively increase the area of ​​the via plug and increase the current density of the via plug, thereby reducing the total resistance of the via plug. However, excessively reducing the thickness of the Ti / TiN stack will lead to poor via filling capability of the W plug, causing reliability issues such as degradation of electromigration characteristics and reduced characteristic life, which poses great challenges in continuous miniaturization.

[0053] Similarly, the resistivity of Ta / TaN is higher than that of Cu. Under the same trench width conditions, reducing the thickness of the Ta / TaN stack can effectively increase the area of ​​the interconnection line, increase the current density, and thus reduce the total resistance of the metal interconnection line. However, excessively reducing the thickness of Ta / TaN will lead to poor through-hole filling ability of Cu interconnection lines, causing reliability issues such as degradation of electromigration characteristics and reduced characteristic life, which poses great challenges in continuous miniaturization.

[0054] When Co is used as a plug, in order to maximize the effective area of ​​Co interconnection, a single-layer Co-Ti alloy is usually used instead of the traditional Ti / TiN double-layer structure, so that the Co-Ti alloy can play multiple roles such as liner layer, barrier layer, and adhesion layer at the same time. It should be noted that, under the premise of a fixed top-view area of ​​the through hole, the smaller the thickness of the other film layers between the Co metal layer and the side wall of the through hole, the larger the filling area of ​​the Co metal layer, which is more conducive to increasing the effective area of ​​Co interconnection. As a single-layer liner / barrier layer, a single-layer Co-Ti alloy can achieve smooth low-resistance contact with the Si substrate.

[0055] However, compared with silicon, Ge 1-x Ge x Moreover, the higher the Ge content, the easier it is to agglomerate, which makes the solid solubility of Ge in many materials low and easier to precipitate. Therefore, even at extremely low annealing temperatures, Co-Ti alloys and P + Type Si 1-x Ge x The source / drain regions of the quartz crystals undergo germanium-siliconization reactions, and are prone to forming germanium-rich germanium-silicon grains and germanium-deficient Co(Si 1-x Ge x ) island structure, which deteriorates the interface morphology and interface characteristics of the source / drain semiconductor layer and the metal layer.

[0056] like Figure 1-Figure 3 As shown, Figure 1 When the Ti content in the Co-Ti alloy layer is 35%, the Co-Ti alloy layer and Si 1-x Ge x A partial cross-sectional view of the structure formed by the layers, Figure 2 for Figure 1 Schematic diagram of the curve of the content of each element in the structure shown at position A with depth. Figure 3 for Figure 1 Schematic diagram of the curve of the content of each element in the structure shown at position B as a function of depth, where the horizontal axis is depth and the vertical axis is distribution. Figure 2 and Figure 3It can be seen that in the depth range of 100nm-120nm, the Ge content at position A is much smaller than the Ge content at position B. It can be seen that the Co-Ti alloy layer and Si 1-x Ge x In the structure formed by the layer, at least in some areas, at the same depth position, the Ge content at different horizontal positions is different, and there are Ge-rich Si-Ge grains and Ge-deficient Co(Si 1-x Ge x ) island structure, where the low Ge content area corresponds to the Ge-deficient Co(Si 1-x Ge x ) island structure, the area with high Ge content corresponds to the Ge-rich SiGe grains.

[0057] Similarly, Figure 4-Figure 6 As shown, Figure 4 When the Ti content in the Co-Ti alloy layer is 50%, the Co-Ti alloy layer and Si 1- x Ge x A partial cross-sectional view of the structure formed by the layers, Figure 5 for Figure 4 Schematic diagram of the curve of the content of each element in the structure shown at the C position with depth, Figure 6 for Figure 4 Schematic diagram of the curve of the content of each element in the structure shown at position D as a function of depth, where the horizontal axis is depth and the vertical axis is distribution. Figure 5 and Figure 6 It can be seen that in the depth range of 100nm-120nm, the Ge content at the C position is much smaller than the Ge content at the D position. 1-x Ge x In the structure formed by the layer, at least in some areas, at the same depth position, the Ge content at different horizontal positions is different, and there are Ge-rich Si-Ge grains and Ge-deficient Co(Si 1-x Ge x ) island structure.

[0058] In view of this, the present application provides a semiconductor structure and a method for manufacturing the same, such as Figure 7 As shown, the production method includes:

[0059] S1: Figure 8 As shown, a semiconductor substrate 10 is provided, wherein the semiconductor substrate 10 includes a source region S and a drain region D. A gate structure G is formed on the surface of the semiconductor substrate 10. The source region S and the drain region D are silicon germanium semiconductor layers. Optionally, the source region and the drain region can be P-type heavily doped Si 1-x Ge x; Wherein, the value range of x is 0.1-0.6, including the endpoint value.

[0060] Optionally, in one embodiment of the present application, the semiconductor structure includes at least one semiconductor unit, one semiconductor unit corresponds to one transistor, and the following continues: Figure 1 As shown, the semiconductor unit includes a semiconductor layer 11 and a shallow trench isolation structure (STI) 12 located around the semiconductor layer 11. Specifically, in an embodiment of the present application, the semiconductor layer can be a Si substrate, a Ge substrate, a SiGe substrate, a SOI substrate or a GeOI substrate, etc., which is not limited in the present application and depends on the specific situation.

[0061] S2: Fig. 9 As shown, an interlayer dielectric layer 20 is formed to cover the semiconductor substrate 10 and the gate structure G. The interlayer dielectric layer 20 has a plurality of through holes, and the plurality of through holes include a first through hole 21 and a second through hole 22. The first through hole 21 exposes the source region S, and the second through hole 22 exposes the drain region D.

[0062] S3: Fig.10 As shown, silicon ions are used to perform pre-amorphization treatment on the surfaces of the source region S and the drain region D, and an amorphous layer 30 is formed at the bottom layer of the through hole (including the first through hole 21 and the second through hole 22).

[0063] It should be noted that the use of silicon ions to perform pre-amorphization treatment on the surfaces of the source region and the drain region is to convert the single crystal structure of the surface of the source region and the drain region into amorphous by injection, and to dope the Si element, such as performing silicon ion implantation on the source region and the drain region exposed by the through hole to form a silicon-rich amorphous layer at the bottom of the through hole, so that the surface of the amorphous layer has a higher silicon content, thereby reducing the outward diffusion of germanium in the source region and the drain region, and at the same time being conducive to the subsequently formed silicon germanium layer having a better interface morphology.

[0064] Optionally, in one embodiment of the present application, when silicon ions are implanted into the source region and the drain region exposed by the through hole, the silicon ions may be directly implanted, or an oxidation sacrificial layer may be deposited first and then the silicon ions are implanted. The present application does not limit this and it depends on the specific circumstances.

[0065] Specifically, in one embodiment of the present application, the ion implantation tilt angle when the source region and the drain region exposed by the through hole are implanted with silicon ions may be 7° or other tilt angles, and the implantation dose may range from 1 to 10 -14 cm -2 ~1*10 -16 cm-2 The injection energy may range from 0.5keV to 20keV, which is not limited in the present application and depends on the specific circumstances.

[0066] Optionally, in one embodiment of the present application, the thickness of the amorphous layer ranges from 2 nm to 5 nm, but the present application does not limit this, as long as a silicon germanium layer can be completely formed through a silicon germanium reaction later.

[0067] S4: Fig.11 As shown, the surface of the amorphous layer 30 is treated with ozone to form a diffusion barrier layer 40 .

[0068] It should be noted that oxidation treatment of the surface of the amorphous layer can destroy the dangling bonds on the surface of the amorphous layer, thereby slowing down the diffusion rate of Co in the subsequent silicon germanium reaction, avoiding the formation of Co burr structure, and also alleviating the out-diffusion of Ge.

[0069] It should also be noted that, in this embodiment, the barrier diffusion layer is an ultra-thin barrier diffusion layer, so as to prevent the diffusion of Ge and allow the diffusion of metal ions, thereby not affecting the silicon germanium reaction of the amorphous layer. If the amorphous layer is oxidized by oxygen to form the barrier diffusion layer, a higher oxidation temperature is required, and the thickness of the formed barrier diffusion layer is larger, resulting in the difficulty in controlling the thickness of the barrier diffusion layer.

[0070] In the embodiment of the present application, the amorphous layer is oxidized by ozone, and the oxidation can be performed at room temperature, so that the thickness of the formed diffusion barrier layer is relatively thin. Optionally, in an embodiment of the present application, the thickness of the diffusion barrier layer ranges from 5 angstroms to 20 angstroms, but the present application does not limit this, and it depends on the specific situation.

[0071] It should be noted that the ozone treatment is in the form of chemical corrosion, which specifically includes: firstly removing the natural oxide layer on the surface by wet etching; and then placing the semiconductor structure in ozone to form a diffusion layer on the surface of the amorphous layer.

[0072] Optionally, in one embodiment of the present application, the etching solution used when removing the natural oxide layer on the surface by wet etching can be diluted hydrofluoric acid or BOE solution (Buffered Oxide Etch), wherein the BOE solution is a mixture of hydrofluoric acid (49%) and water, or a mixture of ammonium fluoride and water; the time for the semiconductor structure to be in ozone can be 5s to 1min, and the flow rate can be 3ppm to 20ppm (ppm is the unit of concentration). The present application does not limit this, and it depends on the specific situation.

[0073] S5: performing metallization treatment on the amorphous layer so that the amorphous layer undergoes a silicon-germanium reaction to form a silicon-germanium layer, and forming a first metal structure in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole.

[0074] Optionally, in one embodiment of the present application, the amorphous layer is metallized so that the amorphous layer undergoes a silicon-germanium reaction to form a silicon-germanium layer, and a first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole, including:

[0075] like Fig.12 As shown, a Co-Ti alloy layer 51 is formed to at least cover the bottom of the through hole and the sidewall of the through hole;

[0076] A Co metal layer 52 is formed on the side of the Co-Ti alloy layer 51 away from the through hole to fill the through hole;

[0077] like Fig.13 As shown, the Co-Ti alloy layer 51 and the amorphous layer 30 are heat treated so that the amorphous layer 30 undergoes a silicon-germanium reaction to form a silicon-germanium layer 60 located at the bottom of the through hole and a first metal structure 50 located in the through hole, wherein the first metal structure 50 includes a Co-Ti alloy layer 53 located on the side wall of the through hole and a Co metal layer 52 filling the through hole.

[0078] It should be noted that, in this embodiment, Fig.13 and Fig.14 As shown, if the first metal structure 50 also extends to cover the surface of the interlayer dielectric layer 20 away from the semiconductor substrate 10, the method also includes removing the portion of the first metal structure 50 located on the surface of the interlayer dielectric layer 20 away from the semiconductor substrate 10. Optionally, a chemical mechanical polishing process can be used to remove the portion of the first metal structure 50 located on the surface of the interlayer dielectric layer 20 away from the semiconductor substrate 10. The present application does not limit this and it depends on the specific circumstances.

[0079] Optionally, in one embodiment of the present application, heat treating the Co-Ti alloy layer and the amorphous layer includes: heat treating the Co-Ti alloy layer and the amorphous layer at a preset temperature for a preset time, wherein the preset temperature ranges from 400°C to 600°C, and the preset time ranges from 10s to 60s.

[0080] Specifically, in one embodiment of the present application, the heat treatment process may be a rapid thermal annealing process or a laser annealing process, etc. The present application does not limit this and it depends on the specific circumstances.

[0081] In another embodiment of the present application, the amorphous layer is metallized so that the amorphous layer undergoes a silicon-germanium reaction to form a silicon-germanium layer, and a first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the sidewall of the through hole and a Co metal layer filling the through hole, including:

[0082] Forming a contact metal layer on the surface of the through hole, optionally, the contact metal layer may be a Ni metal layer or a Ti metal layer;

[0083] Performing heat treatment on the contact metal layer and the amorphous layer so that the amorphous layer undergoes a silicon germanium reaction to form a silicon germanium layer;

[0084] removing a portion of the contact metal layer located on a side wall of the through hole;

[0085] A first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on a sidewall of the through hole and a Co metal layer filling the through hole.

[0086] It should be noted that, in this embodiment, the Co-Ti alloy layer is mainly used as a barrier diffusion layer for the Co metal layer. The more negative the amorphous phase of the Co-Ti alloy layer is, the more stable the Co-Ti alloy layer is, and the better the barrier effect on the diffusion of the Co element in the Co metal layer is. 1-y Ti y The alloy layer, wherein y is between 0.2 and 0.7, so that the Co-Ti alloy layer has an amorphous phase; the thickness of the Co-Ti alloy layer ranges from 1 nm to 3 nm, but this application does not limit this, depending on the specific situation. It should also be noted that in this embodiment, when y is between 0.2 and 0.7, the value of y can be 0.2 or 0.7.

[0087] It should be noted that the above embodiment is described by taking the stack of Co-Ti alloy layer and Co metal layer as a through-hole plug as an example. In other embodiments of the present application, the stack of Co-Ti alloy layer and Co metal layer can also be used as an interconnection line.

[0088] Optionally, in one embodiment of the present application, if the stack of the Co-Ti alloy layer and the Co metal layer is also used as an interconnection line, the manufacturing method further includes: Fig.15As shown, a second metal structure 60 is formed on the side of the interlayer dielectric layer 50 away from the semiconductor substrate 10, and the second metal structure 60 includes a stacked Co-Ti alloy layer 61 and a Co metal layer 62; wherein the second metal structure 60 includes a source and a drain, the source is electrically connected to the source region S through the portion of the first metal structure 50 located in the first through hole, and the drain is electrically connected to the drain region D through the portion of the first metal structure 50 located in the second through hole.

[0089] It should be noted that, in this embodiment, the first metal structure cannot be directly used as the source and drain. Therefore, when the source and drain are subsequently patterned to be electrically insulated, the process requirements for surface flatness are relatively high. Therefore, in this embodiment, even if the source and drain are made of stacked Co-Ti alloy layers and Co metal layers, the first metal structure needs to be flattened before the second metal structure is made as the source and drain.

[0090] As can be seen from the above, the manufacturing method of the semiconductor structure provided in the embodiment of the present application adopts a stack of a Co-Ti alloy layer and a Co metal layer as a through-hole plug. The Co metal layer does not require a nucleation layer with a high resistivity, has a smaller electron mean free path and a higher melting point, and is not as sensitive to size effects as W and Cu, and is suitable for the development trend of integrated circuits with continuously decreasing line widths; moreover, the Co-Ti alloy layer can simultaneously play multiple roles such as a liner layer, a barrier layer, and an adhesion layer, so that under the premise that the top-view area of ​​the through-hole is fixed, the thickness of other film layers between the Co metal layer and the side wall of the through-hole can be reduced, which is beneficial to increase the filling area of ​​the Co metal layer, thereby facilitating an increase in the effective area of ​​the Co interconnection, reducing the resistivity of the through-hole plug, and improving the performance of the semiconductor structure.

[0091] Moreover, in the method for manufacturing the semiconductor structure provided in the embodiment of the present application, before manufacturing the first metal structure including the stack of the Co-Ti alloy layer and the Co metal layer, the source region and the drain region are pre-amorphized by using silicon ions to form an amorphous layer with a high silicon content, and then the amorphous layer is treated with ozone to form a diffusion barrier layer to reduce the out-diffusion of germanium in the source region and the drain region, so that the interface between the semiconductor layer and the metal layer does not have germanium-rich silicon-germanium grains and germanium-deficient Co(Si 1- x Ge x ) island structure phenomenon, so that the silicon germanium layer has better interface morphology and interface characteristics.

[0092] Accordingly, the present application also provides a semiconductor structure, which can be manufactured using the manufacturing method provided in any of the above embodiments. Fig.14 As shown, the semiconductor structure provided in the embodiment of the present application includes:

[0093] A semiconductor substrate, wherein the semiconductor substrate comprises a source region and a drain region, a gate structure is formed on the surface of the semiconductor substrate, and the source region and the drain region are silicon germanium semiconductor layers;

[0094] an interlayer dielectric layer covering the semiconductor substrate and the gate structure, wherein the interlayer dielectric layer has a plurality of through holes, wherein the plurality of through holes include a first through hole and a second through hole, wherein the first through hole exposes the source region, and the second through hole exposes the drain region;

[0095] a silicon germanium layer at the bottom of the through hole;

[0096] a barrier diffusion layer located on a side of the silicon germanium layer away from the semiconductor substrate;

[0097] A first metal structure is located in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on a sidewall of the through hole and a Co metal layer filling the through hole.

[0098] Optionally, in one embodiment of the present application, the semiconductor structure includes at least one semiconductor unit, one semiconductor unit corresponds to one transistor, and the following continues: Fig.14 As shown, the semiconductor unit includes a semiconductor layer 11 and a shallow trench isolation structure (Shallow Trench Isolation, STI for short) 12 located around the semiconductor layer 11 .

[0099] Specifically, in one embodiment of the present application, the transistor is a P-type MOS tube, the semiconductor layer can be a Si substrate, a Ge substrate, a SiGe substrate, an SOI substrate or a GeOI substrate, etc.; the source region and the drain region can be a P-type heavily doped Si substrate. 1-x Ge x , wherein the value range of x is 0.1-0.6, including the endpoint value. This application does not limit this, and it depends on the specific situation.

[0100] It should be noted that, in the present embodiment, the silicon germanium layer and the barrier diffusion layer are formed based on an amorphous layer formed by pre-amorphizing the source region and the drain region using silicon ions. It should be noted that the surface of the source region and the drain region is pre-amorphized using silicon ions to form a silicon-rich amorphous layer at the bottom of the through hole, so that the surface of the amorphous layer has a higher silicon content, thereby reducing the out-diffusion of germanium in the source region and the drain region, and at the same time, it is beneficial for the silicon germanium layer to have a better interface morphology. Moreover, the barrier diffusion layer is obtained by ozone treatment of the amorphous layer to destroy the dangling bonds on the surface of the amorphous layer, thereby slowing down the diffusion rate of Co in the process of forming the silicon germanium layer, avoiding the formation of a Co burr structure, and also alleviating the out-diffusion of Ge.

[0101] It should be noted that, in this embodiment, the diffusion barrier layer is an ultra-thin diffusion barrier layer, so as to prevent the diffusion of Ge and allow the diffusion of metal ions, thereby not affecting the silicon germanium reaction of the amorphous layer. Optionally, in an embodiment of the present application, the thickness of the diffusion barrier layer ranges from 5 angstroms to 20 angstroms, but the present application does not limit this, and it depends on the specific situation.

[0102] It should also be noted that, in this embodiment, the Co-Ti alloy layer is mainly used as a barrier diffusion layer for the Co metal layer. The more negative the amorphous phase of the Co-Ti alloy layer is, the more stable the Co-Ti alloy layer is, and the better the barrier effect on the diffusion of the Co element in the Co metal layer is. 1-y Ti y alloy layer, wherein y is between 0.2 and 0.7, including 0.2 and 0.7, so that the Co-Ti alloy layer has an amorphous phase; the thickness of the Co-Ti alloy layer ranges from 1nm to 3nm, but this application does not limit this, depending on the specific circumstances.

[0103] It should be noted that the above embodiment is described by taking the stack of Co-Ti alloy layer and Co metal layer as a through-hole plug as an example. In other embodiments of the present application, the stack of Co-Ti alloy layer and Co metal layer can also be used as an interconnection line.

[0104] Therefore, based on any of the above embodiments, in one embodiment of the present application, Fig.15 As shown, the semiconductor structure also includes: a second metal structure 60 located on the side of the interlayer dielectric layer 50 away from the semiconductor substrate 10, the second metal structure 60 includes a stacked Co-Ti alloy layer 61 and a Co metal layer 62; wherein the second metal structure 60 includes a source and a drain, the source is electrically connected to the source region S through the portion of the first metal structure 50 located in the first through hole, and the drain is electrically connected to the drain region D through the portion of the first metal structure 50 located in the second through hole.

[0105] In summary, in the semiconductor structure provided in the embodiment of the present application, a stack of a Co-Ti alloy layer and a Co metal layer is used as a through-hole plug. The Co metal layer does not require a nucleation layer with a high resistivity, has a smaller electron mean free path and a higher melting point, and is not as sensitive to size effects as W and Cu, and is suitable for the development trend of integrated circuits with decreasing line widths; moreover, the Co-Ti alloy layer can simultaneously play multiple roles such as a liner layer, a barrier layer, and an adhesion layer, so that under the premise that the top-view area of ​​the through-hole is fixed, the thickness of other film layers between the Co metal layer and the side wall of the through-hole can be reduced, which is beneficial to increasing the filling area of ​​the Co metal layer, thereby facilitating increasing the effective area of ​​the Co interconnection, reducing the resistivity of the through-hole plug, and improving the performance of the semiconductor structure.

[0106] In addition, in the semiconductor structure provided in the embodiment of the present application, the silicon germanium layer and the barrier diffusion layer are formed based on an amorphous layer formed by pre-amorphizing the source region and the drain region using silicon ions, thereby reducing the outdiffusion of germanium in the source region and the drain region, so that the interface between the semiconductor layer and the metal layer will not have germanium-rich silicon germanium grains and germanium-deficient Co (Si 1-x Ge x ) island structure phenomenon, so that the silicon germanium layer has better interface morphology and interface characteristics; moreover, the barrier diffusion layer is obtained by ozone treatment of the amorphous layer to destroy the dangling bonds on the surface of the amorphous layer, thereby slowing down the diffusion rate of Co in the process of forming the silicon germanium layer, avoiding the formation of Co burr structure, and also alleviating the external diffusion of Ge, further making the silicon germanium layer have better interface morphology and interface characteristics.

[0107] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0108] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure marks throughout the embodiments of the specification identify the same structure. It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such articles or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the article or equipment including the above elements.

[0109] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The preparation method comprises: Providing a semiconductor substrate, wherein the semiconductor substrate comprises a source region and a drain region, a gate structure is formed on the surface of the semiconductor substrate, and the source region and the drain region are silicon germanium semiconductor layers; forming an interlayer dielectric layer covering the semiconductor substrate and the gate structure, wherein the interlayer dielectric layer has a plurality of through holes, the plurality of through holes including a first through hole and a second through hole, the first through hole exposing the source region, and the second through hole exposing the drain region; Using silicon ions, pre-amorphizing the surfaces of the source region and the drain region to form an amorphous layer at the bottom layer of the through hole; Performing ozone treatment on the surface of the amorphous layer to form a diffusion barrier layer; The amorphous layer is metallized to cause a silicon-germanium reaction to occur in the amorphous layer to form a silicon-germanium layer, and a first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The amorphous layer is subjected to metallization treatment so that the amorphous layer undergoes a silicon-germanium reaction to form a silicon-germanium layer, and a first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole, including: forming a Co-Ti alloy layer covering at least the bottom of the through hole and the sidewall of the through hole; forming a Co metal layer filling the through hole on a side of the Co-Ti alloy layer away from the through hole; The Co-Ti alloy layer and the amorphous layer are heat treated so that the amorphous layer undergoes a silicon-germanium reaction to form a silicon-germanium layer at the bottom of the through hole and a first metal structure located in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The heat treatment of the Co-Ti alloy layer and the amorphous layer comprises: The Co-Ti alloy layer and the amorphous layer are heat treated at a preset temperature for a preset time, wherein the preset temperature ranges from 400° C. to 600° C., and the preset time ranges from 10s to 60s.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The amorphous layer is subjected to metallization treatment so that the amorphous layer undergoes a silicon-germanium reaction to form a silicon-germanium layer, and a first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on the side wall of the through hole and a Co metal layer filling the through hole, including: forming a contact metal layer on the surface of the through hole; Performing heat treatment on the contact metal layer and the amorphous layer so that the amorphous layer undergoes a silicon germanium reaction to form a silicon germanium layer; removing a portion of the contact metal layer located on a side wall of the through hole; A first metal structure is formed in the through hole, wherein the first metal structure includes a Co-Ti alloy layer located on a sidewall of the through hole and a Co metal layer filling the through hole.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Also includes: forming a second metal structure on a side of the interlayer dielectric layer away from the semiconductor substrate, wherein the second metal structure comprises a stacked Co-Ti alloy layer and a Co metal layer; The second metal structure includes a source and a drain. The source is electrically connected to the source region through a portion of the first metal structure located in the first through hole. The drain is electrically connected to the drain region through a portion of the first metal structure located in the second through hole.

6. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate comprises a source region and a drain region, a gate structure is formed on the surface of the semiconductor substrate, and the source region and the drain region are silicon germanium semiconductor layers; an interlayer dielectric layer covering the semiconductor substrate and the gate structure, wherein the interlayer dielectric layer has a plurality of through holes, wherein the plurality of through holes include a first through hole and a second through hole, wherein the first through hole exposes the source region, and the second through hole exposes the drain region; a silicon germanium layer at the bottom of the through hole; a barrier diffusion layer located on a side of the silicon germanium layer away from the semiconductor substrate; a first metal structure located in the through hole, the first metal structure comprising a Co-Ti alloy layer located on a sidewall of the through hole and a Co metal layer filling the through hole; Wherein, the semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1-5.

7. The semiconductor structure according to claim 6, characterized in that: The thickness of the diffusion barrier layer ranges from 5 angstroms to 20 angstroms.

8. The semiconductor structure according to claim 6, characterized in that: The Co-Ti alloy layer is Co 1-y Ti y The alloy layer, wherein y is between 0.2 and 0.7; the thickness of the Co-Ti alloy layer ranges from 1 nm to 3 nm.

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