Chip, manufacturing method thereof and electronic equipment

Abstract

The invention provides a chip, a manufacturing method thereof and electronic equipment, the chip comprises a transistor, a metal silicide layer, an etching stop layer, an interlayer dielectric layer and a plurality of first contact holes, the metal silicide layer is at least arranged on a source electrode and a drain electrode of the transistor, and the first contact holes penetrate through the etching stop layer and the interlayer dielectric layer; the chip further comprises a barrier layer, the barrier layer is arranged between the metal silicide layer and the etching stop layer, and under the etching condition of the etching stop layer, the etching rate of the etching stop layer is larger than that of the barrier layer. Therefore, when the etching stop layer is etched, the barrier layer can be prevented from being etched, so that the barrier layer can play a role in stopping etching, the metal silicide layer is prevented from being etched, the metal silicide layer is protected, a source electrode and a drain electrode in the transistor cannot be influenced even if the metal silicide layer is thin, and the reliability of the transistor is improved. And the source electrode and the drain electrode are protected, so that the manufacturing yield of the chip is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip, a manufacturing method thereof, and an electronic device. Background Art

[0002] The chip includes: a substrate, and a transistor, an etch stop layer and an interlayer dielectric layer sequentially arranged on the substrate. The etch stop layer and the interlayer dielectric layer are provided with penetrating contact holes. When metal is deposited in the contact hole, the metal can be electrically connected to the top gate, source and drain in the transistor, so as to transmit signals to the top gate, source and drain to realize the function of the transistor. Taking the source as an example, in order to increase the electrical connection effect between the metal in the contact hole and the source and reduce the contact resistance, a metal silicide layer can be arranged between the source and the etch stop layer. The conductivity of the metal silicide layer is between that of metal and silicon, and it can be used as a transition layer for the contact between the metal and the semiconductor, which is conducive to forming an ohmic contact between the metal and the semiconductor layer, thereby reducing the contact resistance.

[0003] However, when forming contact holes, over-etching may occur, causing the metal silicide layer to be etched. When the metal silicide layer is thin, the metal silicide layer may be etched through to affect the top gate, source, and drain, resulting in a decrease in the chip manufacturing yield. Summary of the invention

[0004] The present application provides a chip, a manufacturing method thereof and an electronic device, which are used to solve the problem that when the metal silicide layer is thin, the metal silicide layer may be etched through and affect the electrodes in the transistor, thereby improving the manufacturing yield of the chip.

[0005] In the first aspect, the embodiment of the present application provides a chip, which may include: a transistor, a metal silicide layer, an etch stop layer, an interlayer dielectric layer and a plurality of first contact holes stacked in sequence, the transistor includes a source and a drain, the metal silicide layer is at least arranged on the source and the drain, the first contact hole penetrates the etch stop layer and the interlayer dielectric layer, the source overlaps with the orthographic projection of at least one of the plurality of first contact holes on the substrate, that is, the source overlaps with the orthographic projection of part of the first contact holes on the substrate; the drain overlaps with the orthographic projection of at least one of the plurality of first contact holes on the substrate, that is, the drain overlaps with the orthographic projection of part of the first contact holes on the substrate. The chip may also include a barrier layer, the barrier layer is arranged between the metal silicide layer and the etch stop layer, and under the etching conditions of the etch stop layer, the etching rate of the etch stop layer is greater than the etching rate of the barrier layer. In this way, when the first contact hole is formed, because under the etching conditions of the etch stop layer, the etching rate of the etch stop layer is greater than the etching rate of the barrier layer, when the etch stop layer is etched, it is helpful to avoid etching the barrier layer, and the larger the etching selectivity of the etch stop layer relative to the barrier layer, the smaller the etching probability of the barrier layer, so that the barrier layer can stop the etching, avoid etching the metal silicide layer, and protect the metal silicide layer. Even if the metal silicide layer is thin, it will not affect the source and drain in the transistor, and it plays a protective role on the source and drain, thereby improving the manufacturing yield of the chip.

[0006] Optionally, the barrier layer may be provided in the following manner:

[0007] The first type: the barrier layer is made of a conductive material, so that the barrier layer is a barrier layer, and the barrier layer is exposed in the first contact hole, so the exposed barrier layer can be regarded as the bottom of the first contact hole. In this way, when a conductive layer is deposited in the first contact hole and the metal silicide layer has conductivity, the conductive layer can be electrically connected to the source and the drain through the barrier layer and the metal silicide layer, so that signals can be transmitted to the source and the drain, which is conducive to realizing the function of the transistor. Among them, the material for making the barrier layer includes at least one of the following: metal, conductive metal oxide, conductive polymer material. For example, the metal can be but not limited to: a conductive metal element, or a conductive metal alloy, or a combination of a conductive metal element and a conductive metal alloy; the conductive metal oxide can be but not limited to indium tin oxide, etc.; the conductive polymer material can be but not limited to doped polyacetylene, etc. As long as the barrier layer can be obtained, the specific manufacturing material is not specifically limited here.

[0008] The second type: the barrier layer is made of non-conductive material, so that the barrier layer is a barrier layer. At this time, the barrier layer is provided with a second contact hole corresponding to each first contact hole, the second contact hole penetrates the barrier layer, and the second contact hole is connected with the corresponding first contact hole; wherein the metal silicide layer can be exposed in the second contact hole, so the exposed metal silicide layer can be regarded as the bottom of the second contact hole; under the etching conditions of the barrier layer, the etching rate of the barrier layer is greater than the etching rate of the metal silicide layer. In this way, when a conductive layer is deposited in the first contact hole and the second contact hole, and the metal silicide layer has conductivity, the conductive layer can be electrically connected to the source and the drain through the metal silicide layer, so that a signal can be transmitted to the source and the drain, which is conducive to realizing the function of the transistor. Among them, the barrier layer is made of at least one of the following materials: non-conductive metal oxide, non-conductive polymer material. For example, the non-conductive metal oxide can be but not limited to tungsten oxide, etc., and the non-conductive polymer material can be but not limited to polyethylene, etc. As long as the barrier layer can be obtained, the specific manufacturing material is not specifically limited here.

[0009] Furthermore, at least part of the metal in the material for making the barrier layer is the same as the metal in the metal silicide layer, that is, when at least one metal is included in the material for making the barrier layer, the metal included in the barrier layer can be the same as the metal in the metal silicide layer. For example, if the metal in the metal silicide layer contains Co, then the metal in the barrier layer contains at least Co; if the metal in the metal silicide layer contains Ni, then the metal in the barrier layer contains at least Ni; if the metal in the metal silicide layer contains Ti, then the metal in the barrier layer contains at least Ti. Of course, the metal in the metal silicide layer is not limited to Co, Ni and Ti, but can also be other metals, which are not listed here one by one. In this way, the barrier layer and the metal silicide layer can contain the same metal elements, which can improve the manufacturing quality of the barrier layer, and can also reduce the introduction of impurities, thereby avoiding some unknown and uncontrollable problems, thereby improving the reliability of the chip.

[0010] In addition, the thickness of the barrier layer can be set to 2nm to 5nm, for example, the thickness of the barrier layer is set to 2nm, 3nm, 4nm or 5nm. When the thickness of the barrier layer is large, it will not only increase the difficulty of manufacturing the barrier layer, but also increase the thickness of the chip, resulting in increased manufacturing cost and volume of the chip; when the thickness of the barrier layer is small, the manufacturing quality of the barrier layer may be reduced. If the barrier layer has defects such as holes and gaps, the defects in the barrier layer may damage the metal silicide layer when forming the contact hole, resulting in the inability to effectively protect the metal silicide layer. Therefore, setting the thickness of the barrier layer in an appropriate range can not only effectively protect the metal silicide layer, but also reduce the manufacturing cost and avoid increasing the volume of the chip.

[0011] Optionally, the transistor may further include a top gate, and the metal silicide layer is also disposed on the top gate, so a barrier layer is also disposed on the metal silicide layer corresponding to the top gate, and the top gate overlaps with the orthographic projection of at least one of the plurality of first contact holes on the substrate, that is, the top gate overlaps with the orthographic projection of some of the first contact holes on the substrate. In this way, when forming the first contact hole corresponding to the top gate, the barrier layer on the top gate can stop etching, and when etching the etch stop layer, etching of the metal silicide layer can be avoided, thereby protecting the metal silicide layer. Even if the metal silicide layer is thin, it will not affect the top gate in the transistor, thereby protecting the top gate, thereby further improving the chip manufacturing yield. It should be understood that the setting methods of the barrier layer on the metal silicide layer corresponding to the top gate, the barrier layer on the metal silicide layer corresponding to the source, and the barrier layer on the metal silicide layer corresponding to the drain are all the same, so the setting method of the barrier layer on the metal silicide layer corresponding to the top gate can be referred to the introduction in the above-mentioned related content, and the repeated parts will not be repeated.

[0012] For the etch stop layer and the interlayer dielectric layer: the etch stop layer and the interlayer dielectric layer can be made of non-conductive materials, for example, the etch stop layer can be made of but not limited to SiO2, the interlayer dielectric layer can be made of but not limited to Si3N4, or the etch stop layer can be made of but not limited to Si3N4, the interlayer dielectric layer can be made of but not limited to SiO2, and of course, other non-conductive materials can also be used, which are not listed here one by one. In this way, the etching rate difference between the barrier layer and the etch stop layer can be larger, and the etching rate difference between the etch stop layer and the interlayer dielectric layer is slightly smaller, so when the interlayer dielectric layer is etched to form the first contact hole, the etch stop layer is likely to be etched, but it is difficult to etch the barrier layer, so that the barrier layer can stop etching, protect the metal silicide layer, and then protect the source and drain, thereby improving the chip manufacturing yield.

[0013] It is worth noting that since the barrier layer can stop etching and protect the metal silicide layer, the metal silicide layer can be set thinner. For example, the thickness of the metal silicide layer can be set to 2nm to 5nm, so as to form a continuous metal silicide layer and avoid the problem of breakage caused by agglomeration when the metal silicide layer is thicker. This can improve the performance and product yield of the chip, reduce the difficulty and cost of production, and help reduce the size of the chip.

[0014] In the second aspect, the embodiments of the present application also provide a chip manufacturing method, which is used to manufacture the chip as described in the first aspect and any one of the embodiments of the first aspect. The manufacturing method may include: forming a transistor on a substrate, the transistor including a source and a drain; forming a metal silicide layer at least on the source and the drain; forming a barrier layer on the metal silicide layer; forming an etch stop layer and an interlayer dielectric layer in sequence on the substrate formed with the barrier layer; under the etching conditions of the etch stop layer, the etching rate of the etch stop layer is greater than the etching rate of the barrier layer; forming a plurality of first contact holes penetrating the etch stop layer and the interlayer dielectric layer, the source overlaps with the orthographic projection of at least one of the plurality of first contact holes on the substrate, and the drain overlaps with the orthographic projection of at least one of the plurality of first contact holes on the substrate. In this way, when the first contact hole is formed, because under the etching conditions of the etch stop layer, the etching rate of the etch stop layer is greater than the etching rate of the barrier layer, when the etch stop layer is etched, it is helpful to avoid etching the barrier layer, and the larger the etching selectivity of the etch stop layer relative to the barrier layer, the smaller the etching probability of the barrier layer, so that the barrier layer can stop the etching, avoid etching the metal silicide layer, and protect the metal silicide layer. Even if the metal silicide layer is thin, it will not affect the source and drain in the transistor, and it plays a protective role on the source and drain, thereby improving the manufacturing yield of the chip.

[0015] Optionally, forming the metal silicide layer may specifically include: when the transistor further includes a top gate, forming metal silicide layers on the source, the drain and the top gate, respectively. In this way, a metal silicide layer and a barrier layer are sequentially arranged on the top gate, and the barrier layer on the top gate can stop etching, and when the etching stop layer is etched, the metal silicide layer can be avoided from being etched, thereby protecting the metal silicide layer. Even if the metal silicide layer is thin, it will not affect the top gate in the transistor, thereby protecting the top gate, thereby further improving the manufacturing yield of the chip.

[0016] Optionally, the manufacturing method may further include: before forming the first contact hole and after forming the interlayer dielectric layer, heat treating the substrate formed with the interlayer dielectric layer to form a continuous metal silicide layer, thereby reducing the contact resistance between the source, drain, top gate and the conductive layer in the first contact hole, and improving the performance and product yield of the chip. Wherein, when Co is contained in the metal silicide layer, the metal silicide layer may undergo two heat treatments when it is formed. At this time, the metal silicide layer is formed on the source and drain, which may specifically include: forming an amorphous silicon layer and a Co layer on the source and drain in sequence, and then performing a rapid annealing treatment so that the amorphous silicon layer and the Co layer react to form a cobalt silicide layer with a high resistance phase. The rapid annealing treatment is the first heat treatment. Then, before forming the first contact hole and after forming the interlayer dielectric layer, the substrate formed with the interlayer dielectric layer is subjected to heat treatment. This heat treatment can be regarded as the second heat treatment, that is, high-temperature rapid annealing treatment, so that the high-resistance phase cobalt silicide layer is converted into a low-resistance phase cobalt silicide layer, and the low-resistance phase cobalt silicide layer is used as a metal silicide layer. Of course, when other metals are contained in the metal silicide layer, the metal silicide layer may be obtained by undergoing one heat treatment. For example, before forming the first contact hole and after forming the interlayer dielectric layer, the substrate formed with the interlayer dielectric layer can be subjected to heat treatment. Therefore, the formation process of the metal silicide layer can be designed according to actual conditions and is not limited here.

[0017] Optionally, forming the barrier layer may specifically include forming the barrier layer using a non-conductive material; in this case, the manufacturing method may further include: after forming the barrier layer and before forming the etching stop layer, forming a plurality of second contact holes penetrating the barrier layer, the second contact holes being arranged correspondingly to and connected to the first contact holes, and under the etching conditions of the barrier layer, the etching rate of the barrier layer is greater than the etching rate of the metal silicide layer. In this way, when the first contact hole and the second contact hole are connected and a conductive layer is deposited inside, and the metal silicide layer has conductivity, the conductive layer can be electrically connected to the source and the drain through the metal silicide layer, so that a signal can be transmitted to the source and the drain, which is conducive to realizing the function of the transistor. Moreover, since under the etching conditions of the barrier layer, the etching rate of the barrier layer is greater than the etching rate of the metal silicide layer, when etching the barrier layer, etching of the metal silicide layer can be avoided, and the greater the etching selectivity of the barrier layer relative to the metal silicide layer, the smaller the etching probability of the metal silicide layer, and thus damage to the source and the drain can be avoided, thereby improving the manufacturing yield of the chip.

[0018] Of course, if the formation of the barrier layer includes the use of a conductive material to form the barrier layer, then there is no need to set a second contact hole in the barrier layer, so that the barrier layer is exposed in the first contact hole, and the exposed barrier layer can be regarded as the bottom of the first contact hole. At this time, the conductive layer in the first contact hole can be electrically connected to the source and the drain through the barrier layer and the metal silicide layer, so that signals can be transmitted to the source and the drain, and the process of setting the second contact hole can be omitted, thereby simplifying the manufacturing process and reducing the manufacturing cost.

[0019] It should be understood that since the principle of solving the problem when making chips by this manufacturing method is similar to the principle of solving the problem by the aforementioned chip, the implementation and technical effects of this manufacturing method can refer to the implementation and technical effects of the aforementioned chip, and the repeated parts will not be repeated.

[0020] In a third aspect, an embodiment of the present application further provides an electronic device, which may include: a circuit board and a chip as described in the first aspect and any one of the embodiments of the first aspect, wherein the chip is disposed on the circuit board. In this way, on the basis of improving the manufacturing yield of the chip, the manufacturing yield of the electronic device can be improved, and the performance of the electronic device can also be improved. It should be understood that since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the aforementioned chip, the implementation and technical effects of the electronic device can refer to the implementation and technical effects of the aforementioned chip, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0024] Figure 4 A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0025] Figure 5 A flowchart of a chip manufacturing method provided in an embodiment of the present application;

[0026] Figure 6 A flowchart of another chip manufacturing method provided in an embodiment of the present application.

[0027] Reference numerals:

[0028] 10-substrate, 11-source, 12-drain, 13a-bottom gate, 13b-top gate, 14-channel, 15-gate insulating layer, 16-sidewall, 20-metal silicide layer, 30-barrier layer, 30a-non-conductive barrier layer, 40-etching stop layer, 50-interlayer dielectric layer, 61-first contact hole, 62-second contact hole, 70-conductive layer, m1-transistor, 100-housing, 200-circuit board, 300-chip. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0030] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0031] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its application scenario is first described below.

[0032] The chip provided in the embodiment of the present application can be widely used in various electronic devices, and the electronic devices may include various terminal devices and electronic devices. Among them, the terminal devices may include but are not limited to smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (PCs), wearable devices, smart broadband and other devices. Electronic devices may include but are not limited to wireless networks, fixed networks, servers and other telecommunication equipment, as well as chip modules, memory and other devices, which are not listed here one by one.

[0033] Figure 1 The schematic diagram of the structure of the chip when it is used in an electronic device is shown as an example. Figure 1As shown, the electronic device includes a housing 100 and a circuit board 200 disposed in the housing 100, and a chip 300 is disposed on the circuit board 200. The chip 300 includes: a substrate, and a transistor, an etch stop layer and an interlayer dielectric layer sequentially disposed on the substrate. The etch stop layer and the interlayer dielectric layer are provided with penetrating contact holes. When metal is deposited in the contact hole, the metal can be electrically connected to the top gate, source and drain in the transistor, so as to transmit signals to the top gate, source and drain to realize the function of the transistor. Taking the source as an example, in order to increase the electrical connection effect between the metal in the contact hole and the source and reduce the contact resistance, a metal silicide layer can be provided between the source and the etch stop layer. The conductivity of the metal silicide layer is between that of metal and silicon, and can be used as a transition layer for the contact between the metal and the semiconductor, which is conducive to forming an ohmic contact between the metal and the semiconductor layer, thereby reducing the contact resistance.

[0034] The metal silicide layer can be made of nickel silicide, which has a low formation temperature, small silicon consumption and no line width effect, but the thermal stability of nickel silicide is low and it will degrade at a temperature above 500°C. This feature limits the use of nickel silicide in high-temperature process scenarios. Compared with nickel silicide, cobalt silicide (i.e., CoSi2) has good high-temperature thermal stability, good conductivity, and low mismatch rate with silicon. Among them, when forming cobalt silicide, metal cobalt is first deposited on amorphous silicon, and then low-temperature rapid annealing is performed to form a high-resistance phase of CoSi, and then high-temperature rapid annealing is performed to form a low-resistance phase of CoSi2. However, cobalt silicide is prone to agglomeration in the process of forming the low-resistance phase CoSi2, resulting in the breakage of CoSi2, which seriously affects the device performance and product yield. In order to solve the problem of cobalt silicide breakage, the thickness of the metal cobalt deposition is usually controlled to reduce the grain size of the cobalt silicide, prevent the formation of an excessively thick high-resistance phase CoSi, and help form a continuous cobalt silicide layer after high-temperature rapid annealing. However, when making contact holes in the etch stop layer and the interlayer dielectric layer, over-etching may occur. When the metal silicide layer is thin, the metal silicide layer may be etched away to affect the top gate, source, and drain, resulting in a decrease in the chip manufacturing yield.

[0035] Based on this, the embodiments of the present application provide a chip, a manufacturing method thereof, and an electronic device, which can avoid affecting the electrodes in the transistor even when the thickness of the metal silicide layer is small, thereby improving the manufacturing yield of the chip. The specific structure and manufacturing method of the chip provided in the embodiments of the present application are described in detail below in conjunction with specific embodiments.

[0036] Figure 2 The schematic diagram of the structure of the chip provided in the embodiment of the present application is exemplarily shown. Figure 2As shown, the chip includes: a substrate 10, and a transistor, a metal silicide layer 20, a barrier layer 30, an etch stop layer 40 and an interlayer dielectric layer 50 stacked in sequence on the substrate 10. The transistor can be a bottom-gate transistor, so the transistor can include: a source 11, a drain 12, a bottom gate 13a and a channel 14, the bottom gate 13a is arranged between the channel 14 and the substrate 10, the source 11 and the drain 12 are respectively arranged on opposite sides of the channel 14, and the source 11 and the drain 12 are respectively connected to the channel 14, and a gate insulating layer 15 is arranged between the bottom gate 13a and the channel 14, and the channel 14 and the bottom gate 13a can be isolated by the gate insulating layer 15. Among them, the metal silicide layer 20 is arranged on the source 11 and the drain 12. In other words, the metal silicide layer 20 is arranged on the source 11 and the drain 12, and the metal silicide layer 20 is not arranged at other positions; the barrier layer 30 is arranged on the metal silicide layer 20, and the barrier layer 30 is not arranged in the area where the metal silicide layer 20 is not arranged. At this time, there are metal silicide layer 20 and barrier layer 30 between the source 11 and the etch stop layer 40, and there are also metal silicide layer 20 and barrier layer 30 between the drain 12 and the etch stop layer 40. The chip also includes a first contact hole 61, which penetrates the etching stop layer 40 and the interlayer dielectric layer 50, and there can be multiple first contact holes 61, some of which overlap with the orthographic projection of the source 11 on the substrate 10, and some of which overlap with the orthographic projection of the drain 12 on the substrate 10; the blocking layer 30 can be made of conductive material, so that the blocking layer 30 can be a conductive blocking layer, and the first contact hole 61 corresponding to the source 11 can expose the blocking layer 30, so that the exposed part of the blocking layer 30 can be regarded as the bottom of the first contact hole 61 corresponding to the source 11, and the first contact hole 61 corresponding to the drain 12 can also expose the blocking layer 30, so that the exposed part of the blocking layer 30 can be regarded as the bottom of the first contact hole 61 corresponding to the drain 12. In this way, if under the etching conditions of the etch stop layer 40, the etching rate of the etch stop layer 40 is greater than the etching rate of the barrier layer 30, then when the etch stop layer 40 is etched, it is helpful to avoid etching the barrier layer 30, and the greater the etching selectivity of the etch stop layer 40 relative to the barrier layer 30, the smaller the etching probability of the barrier layer 30, so that the barrier layer 30 can stop the etching, avoid etching the metal silicide layer 20, and protect the metal silicide layer 20. Even if the metal silicide layer 20 is thin, it will not affect the source 11 and the drain 12 in the transistor, and it plays a protective role on the source 11 and the drain 12, thereby improving the manufacturing yield of the chip.Moreover, when a conductive layer is deposited in the first contact hole 61 and the metal silicide layer 20 is conductive, the conductive layer can be electrically connected to the source 11 and the drain 12 through the barrier layer 30 and the metal silicide layer 20, thereby transmitting signals to the source 11 and the drain 12, which is beneficial to realizing the function of the transistor.

[0037] The barrier layer 30 is made of at least one of the following materials: metal, conductive metal oxide, and conductive polymer material. For example, the metal may be, but is not limited to, a conductive metal element, a conductive metal alloy, or a combination of a conductive metal element and a conductive metal alloy; the conductive metal oxide may be, but is not limited to, indium tin oxide, etc.; the conductive polymer material may be, but is not limited to, doped polyacetylene, etc. As long as the barrier layer 30 can be obtained, the specific material is not specifically limited here.

[0038] Furthermore, when the material for making the barrier layer 30 includes at least one metal, the metal included in the barrier layer 30 may be the same as the metal in the metal silicide layer 20. For example, if the metal in the metal silicide layer 20 includes Co, then the metal in the barrier layer 30 includes at least Co; if the metal in the metal silicide layer 20 includes Ni, then the metal in the barrier layer 30 includes at least Ni; if the metal in the metal silicide layer 20 includes Ti, then the metal in the barrier layer 30 includes at least Ti. Of course, the metal in the metal silicide layer 20 is not limited to Co, Ni and Ti, but may also be other metals, which are not listed here one by one. In this way, the barrier layer 30 and the metal silicide layer 20 may include the same metal element, which can improve the manufacturing quality of the barrier layer 30, and can also reduce the introduced impurities, thereby avoiding some unknown and uncontrollable problems, thereby improving the reliability of the chip.

[0039] Furthermore, the thickness d1 of the barrier layer 30 can be set to 2nm to 5nm, for example, the thickness d1 of the barrier layer 30 is set to 2nm, 3nm, 4nm or 5nm. When the thickness d1 of the barrier layer 30 is large, it will not only increase the difficulty of manufacturing the barrier layer 30, but also increase the thickness d1 of the chip, resulting in an increase in the manufacturing cost and volume of the chip; when the thickness d1 of the barrier layer 30 is small, the manufacturing quality of the barrier layer 30 may be reduced. If the barrier layer 30 has defects such as holes and gaps, the defects in the barrier layer 30 may damage the metal silicide layer 20 when forming the first contact hole 61, resulting in the inability to effectively protect the metal silicide layer 20. Therefore, setting the thickness d1 of the barrier layer 30 in a suitable range can not only effectively protect the metal silicide layer 20, but also reduce the manufacturing cost and avoid an increase in the volume of the chip.

[0040] In addition, both the etch stop layer 40 and the interlayer dielectric layer 50 can be made of non-conductive materials, for example, the etch stop layer 40 can be made of, but not limited to, SiO2, and the interlayer dielectric layer 50 can be made of, but not limited to, Si3N4, or the etch stop layer 40 can be made of, but not limited to, Si3N4, and the interlayer dielectric layer 50 can be made of, but not limited to, SiO2. Of course, other non-conductive materials can also be used, which are not listed here one by one. In this way, the etching rate difference between the barrier layer 30 and the etch stop layer 40 can be large, and the etching rate difference between the etch stop layer 40 and the interlayer dielectric layer 50 can be slightly smaller. Therefore, when the interlayer dielectric layer 50 is etched to form the first contact hole 61, the etch stop layer 40 is likely to be etched, but it is difficult to etch the barrier layer 30. Therefore, the barrier layer 30 can stop etching, protect the metal silicide layer 20, and then protect the source 11 and the drain 12, thereby improving the chip manufacturing yield.

[0041] It is worth noting that since the barrier layer 30 can stop etching and protect the metal silicide layer 20, the metal silicide layer 20 can be set to be thinner. For example, the thickness of the metal silicide layer 20 can be set to 2nm to 5nm, so as to form a continuous metal silicide layer 20 and avoid the problem of breakage caused by agglomeration when the metal silicide layer 20 is thicker, thereby improving the performance and product yield of the chip, reducing the difficulty and cost of manufacturing, and helping to reduce the size of the chip.

[0042] Figure 3 The schematic diagram of the structure of the chip provided in the embodiment of the present application is exemplarily shown. Figure 3 As shown, the structure of the chip in this embodiment is similar to that described above. Figure 2The structures of the chips described in the illustrated embodiments are basically similar, except that the transistor is a top gate transistor or a double gate transistor, that is, the transistor includes a top gate structure. Optionally, the top gate structure includes: a top gate 13b, a sidewall 16, and a gate insulating layer 15 disposed between the top gate 13b and the channel 14, the channel 14 and the top gate 13b can be isolated by the gate insulating layer 15, the sidewall 16 is disposed on the side of the top gate 13b, the top gate 13b and the source 11 can be isolated by the sidewall 16, and the top gate 13b and the drain 12 can be isolated to avoid short circuit between the top gate 13b and the source 11, and to avoid short circuit between the top gate 13b and the drain 12. The substrate 10 can be a silicon substrate, in which case the channel 14, the source 11 and the drain 12 can be formed in the substrate 10, and the source 11 and the drain 12 are respectively disposed on opposite sides of the channel 14, and the source 11 and the drain 12 are both connected to the channel 14. In addition to the metal silicide layer 20 and the barrier layer 30 being sequentially disposed on the source electrode 11 and the drain electrode 12, the metal silicide layer 20 and the barrier layer 30 are also sequentially disposed on the top gate 13b, and part of the first contact hole 61 overlaps with the orthographic projection of the top gate 13b on the substrate 10, and the barrier layer 30 is exposed in the first contact hole 61 corresponding to the top gate 13b, so the exposed part of the barrier layer 30 can be regarded as the bottom of the first contact hole 61 corresponding to the top gate 13b. In this way, when forming the first contact hole 61 corresponding to the top gate 13b, the barrier layer 30 on the top gate 13b can stop etching, and when etching the etching stop layer 40, the metal silicide layer 20 can be avoided from being etched, and the metal silicide layer 20 is protected. Even if the metal silicide layer 20 is thin, it will not affect the top gate 13b in the transistor, and the top gate 13b is protected, thereby further improving the manufacturing yield of the chip.

[0043] The specific implementation of the metal silicide layer 20 and the barrier layer 30 located on the top gate 13b is the same as that described above. Figure 2 The specific implementation of the metal silicide layer 20 and the barrier layer 30 described in the embodiment shown is the same, so the specific implementation of the metal silicide layer 20 and the barrier layer 30 located on the top gate 13b can be referred to above. Figure 2 The relevant descriptions in the embodiment shown in the figure will not be repeated. Figure 2 The similarities of the structure of the chip introduced in the embodiment shown can also be seen in the above Figure 2 The related introduction in the illustrated embodiment will not be repeated any more.

[0044] Figure 4 The schematic diagram of the structure of the chip provided in the embodiment of the present application is exemplarily shown. Figure 4 As shown, the structure of the chip in this embodiment is similar to the above Figure 2 and Figure 3The structure of the chip described in any of the embodiments shown is basically similar, that is, Figure 4 The structure of the chip shown in (a) is similar to the above Figure 2 The structure of the chips shown is basically similar. Figure 4 The structure of the chip shown in (b) is similar to the above Figure 3 The structures of the chips shown are basically similar, except that the barrier layer 30 is made of non-conductive material, so the barrier layer 30 can be a non-conductive barrier layer. Optionally, the barrier layer 30 is provided with second contact holes 62 corresponding to each first contact hole 61, the second contact hole 62 penetrates the barrier layer 30, and the second contact hole 62 is connected with the corresponding first contact hole 61; wherein the metal silicide layer 20 can be exposed in the second contact hole 62, so the exposed metal silicide layer 20 can be regarded as the bottom of the second contact hole 62; under the etching conditions of the barrier layer 30, the etching rate of the barrier layer 30 is greater than the etching rate of the metal silicide layer 20. In this way, when a conductive layer is deposited in the first contact hole 61 and the second contact hole 62, and the metal silicide layer 20 has conductivity, the conductive layer can be electrically connected to the source 11 and the drain 12 through the metal silicide layer 20, so that a signal can be transmitted to the source 11 and the drain 12, which is conducive to realizing the function of the transistor. The barrier layer 30 is made of at least one of the following materials: a non-conductive metal oxide and a non-conductive polymer material. For example, the non-conductive metal oxide may be, but not limited to, tungsten oxide, etc., and the non-conductive polymer material may be, but not limited to, polyethylene, etc. As long as the barrier layer 30 can be obtained, the specific material is not specifically limited.

[0045] It should be understood that the structure of the chip in this embodiment is similar to that described above. Figure 2 and Figure 3 The similarities between the structures of the chips described in any of the embodiments shown can be found in the above Figure 2 and Figure 3 The related introduction in any of the embodiments shown will not be repeated any more.

[0046] Figure 5 The schematic diagram of the chip manufacturing method provided in the embodiment of the present application is exemplarily shown. Figure 5 As shown, the production method may include:

[0047] Step 1: Figure 5 As shown in (a) in FIG. 8 , a transistor m1 is formed on a substrate 10 .

[0048] The transistor m1 may be a bottom-gate transistor, a top-gate transistor or a double-gate transistor. Figure 5The top-gate transistor is used as an example, but this does not mean that the transistor m1 can only be a top-gate transistor. In addition, the substrate 10 can be made of polysilicon material. In this case, the source 11, drain 12 and channel 14 in the top-gate transistor can all be formed in the substrate 10, and polysilicon is used as the channel 14. The source 11 and drain 12 can be obtained by doping the polysilicon on both sides of the channel 14. The top gate 13b in the top-gate transistor can be set on the substrate 10 to form a Figure 5 In addition, there may be at least one transistor m1 disposed on the substrate 10, and a metal silicide layer and a conductive barrier layer are formed on the source 11, the drain 12 and the top gate 13b of each transistor m1.

[0049] Step 2: Figure 5 As shown in (b) in FIG. 1 , an amorphous silicon layer (ie, an a-Si layer) and a Co layer are sequentially formed on the source 11 , the drain 12 and the top gate 13 b of the transistor.

[0050] Before forming the amorphous silicon layer, a patterning method can be used to form a mask layer with a predetermined pattern on the substrate with the transistor, through which the source, drain and top gate can be exposed, and other positions can be shielded; at this time, the amorphous silicon layer and the Co layer are deposited in sequence, and then the mask layer is etched away, so that the amorphous silicon layer and the Co layer exist on the source, drain and top gate, and the amorphous silicon layer and the Co layer do not exist in other positions. The mask layer can be made of photoresist or other materials, which can be selected according to actual needs and are not limited here.

[0051] If the source, drain and top gate are all made of doped polysilicon material, the source, drain and top gate can be ion implanted by pre-amorphization ion implantation, so that the polysilicon in part of the source, drain and top gate is converted into amorphous silicon, while the polysilicon in the source that has not been converted continues to serve as the source, the polysilicon in the drain that has not been converted continues to serve as the drain, and the polysilicon in the top gate that has not been converted continues to serve as the top gate, thereby forming an amorphous silicon layer located above the source, drain and top gate. Optionally, the implantation conditions may include: the ion implantation source may be Ge ions or Xe ions, the ion implantation energy may be between 2keV and 10keV, and the ion implantation dose may be 10 14 atom / cm 2 Up to 10 15 atom / cm 2 Of course, the implantation conditions are not limited thereto, and other ion implantation sources, other ion implantation energies, and other ion implantation doses may also be selected, and the specific design may be based on actual needs and is not limited here.

[0052] When forming the Co layer, physical vapor deposition can be used, and the thickness of the produced Co layer can be controlled to be 20nm to 40nm. Of course, the metal layer located on the amorphous silicon layer is not limited to the Co layer, but can also be a Ni layer or a Ti layer. Here, Co is used as an example for illustration.

[0053] Step 3: Figure 5 As shown in (c) in FIG. 1 , a rapid thermal annealing process is performed to cause Co to react with Si to form a CoSi layer of a high-resistance phase, which can be regarded as an initial layer, and the unreacted Co layer on the initial layer is removed.

[0054] In the case of rapid thermal annealing, specific annealing conditions may include: annealing temperature of 380° C. to 540° C., annealing time of 30 min to 120 min. Of course, the annealing conditions are not limited thereto, and may also be other conditions designed according to actual needs, which are not limited here.

[0055] Step 4: Figure 5 As shown in (d), Co is used but not limited to form a Co layer on the initial layer. The Co layer serves as a conductive barrier layer, and the thickness of the Co layer can be controlled to be 2 nm to 5 nm.

[0056] It is worth noting that when forming the Co layer as a conductive barrier layer, the Co layer is only formed on the initial layer, and the Co layer is not formed in other positions. At this time, the manufacturing method for forming the Co layer may include: using a patterning method to form a mask layer with a predetermined pattern on a substrate having an initial layer, through which the initial layer can be exposed and other positions are blocked; at this time, physical vapor deposition is used to deposit the Co layer in an entire layer; and then the mask layer is etched away, so that there is a Co layer on the initial layer, and there is no Co layer in other positions. Of course, other methods that can achieve regional selective deposition can also be used when forming the Co layer, so that the Co layer is only deposited on the initial layer, and the Co layer is not deposited in other positions, which is not limited here.

[0057] Step 5: Continue as Figure 5 As shown in (d), a Si3N4 layer is deposited on the substrate 10 formed with a Co layer by chemical vapor deposition. The Si3N4 layer can be used as an etching stop layer, and the thickness of the Si3N4 layer is controlled to be 20nm to 30nm.

[0058] Step 6. Continue as Figure 5 As shown in (d), the Si3N4 layer is etched to obtain a plurality of initial holes 60 penetrating the Si3N4 layer, each initial hole 60 exposes the Co layer, and each initial hole 60 overlaps with the orthographic projection of the source 11, the drain 12 and the top gate 13b on the substrate 10.

[0059] Among them, before etching, a patterning method can be used to form a mask layer with a predetermined pattern on the Si3N4 layer. Through the mask layer, the position where the initial hole needs to be formed can be exposed, while other positions can be covered. Therefore, when etching is performed, only the exposed position can be etched, and the unexposed position will not be etched, so that each initial hole can be made in the Si3N4 layer; after that, the mask layer is removed to facilitate the continued production of other structures.

[0060] Step 7. Continue as Figure 5 As shown in (d), a high-temperature rapid annealing treatment is performed so that the high-resistance phase CoSi layer as the initial layer is converted into a low-resistance phase CoSi2 layer, and the low-resistance phase CoSi2 layer serves as a metal silicide layer.

[0061] In the case of high temperature rapid annealing, specific annealing conditions may include: annealing temperature of 600° C. to 900° C., annealing time of 5s to 30s. Of course, the annealing conditions are not limited thereto, and may also be other conditions designed according to actual needs, which are not limited here.

[0062] Furthermore, the execution order of step 6 and step 7 can be interchanged, that is, step 7 is executed first and then step 6, which is not limited here.

[0063] Step 8. Continue as Figure 5 As shown in (d) in the figure, a SiO2 layer is deposited entirely on the Si3N4 layer by chemical vapor deposition, and the SiO2 layer serves as an interlayer dielectric layer. The SiO2 layer is also filled in the initial hole 60.

[0064] Step 9: Figure 5 As shown in (e), the SiO2 layer and the SiO2 in the initial hole 60 are etched to obtain a plurality of first contact holes 61 penetrating the SiO2 layer and the initial hole 60, each first contact hole 61 is arranged one-to-one corresponding to each initial hole, and each first contact hole 61 exposes the Co layer, and each first contact hole 61 overlaps with the orthographic projection of the source 11, the drain 12 and the top gate 13b on the substrate 10, respectively.

[0065] Similarly, the method used in making the first contact hole is the same as the method used in making the initial hole, which will not be described in detail here.

[0066] Step 10. Continue as Figure 5 As shown in (e) of FIG. 5 , a conductive layer 70 is deposited in the first contact hole 61 by using a physical vapor deposition method, so that the conductive layer 70 in the first contact hole 61 is in contact with the Co layer.

[0067] In this way, since the conductive barrier layer has a conductive function, when the metal silicide layer also has a conductive function, the conductive layer in the first contact hole corresponding to the top gate can be electrically connected to the top gate through the conductive barrier layer and the metal silicide layer, the conductive layer in the first contact hole corresponding to the source can be electrically connected to the source through the conductive barrier layer and the metal silicide layer, and the conductive layer in the first contact hole corresponding to the drain can be electrically connected to the drain through the conductive barrier layer and the metal silicide layer, thereby providing corresponding electrical signals to the top gate, source, and drain, respectively, to realize the function of the transistor.

[0068] Moreover, when forming the first contact hole, the SiO2 layer and the Si3N4 layer are mainly consumed, and compared with the Co layer, the SiO2 layer and the Si3N4 layer have higher etching selectivity, so the conductive barrier layer can stop the etching, and avoid etching the metal silicide layer when etching the etch stop layer, thereby protecting the metal silicide layer. Even if the metal silicide layer is thin, it will not affect the source, drain and top gate in the transistor, thereby protecting the source, drain and top gate, thereby improving the chip manufacturing yield.

[0069] In addition, when forming the conductive barrier layer, a regional selective deposition method is adopted, and a conductive barrier layer is only formed on the initial layer, while a conductive barrier layer is not formed in other positions. Therefore, the conductive barrier layer only protects the metal silicide layer located thereunder, and will not affect other structures, thereby further improving the chip manufacturing yield.

[0070] Figure 6 The schematic diagram of the chip manufacturing method provided in the embodiment of the present application is exemplarily shown. Figure 6 As shown, the manufacturing method in this embodiment is the same as that in the above Figure 5 The manufacturing methods described in the illustrated embodiments are basically similar, with the following differences:

[0071] (1) Modify step 4 in the manufacturing method of the previous embodiment as follows: Figure 6 As shown in (d), a non-conductive material is used to form a non-conductive barrier layer 30a on the initial layer, and the thickness of the non-conductive barrier layer 30a can be controlled to be 2nm to 5nm. The method for making the non-conductive barrier layer 30a is the same as the method for making the Co layer in the previous embodiment. For details, please refer to the relevant description in the previous embodiment, which will not be described in detail here.

[0072] (2) Between step 4 and step 5 in the manufacturing method of the previous embodiment, step s1 is added, and step s1 is: continue as follows Figure 6As shown in (d) in FIG. 1 , the non-conductive barrier layer 30a is etched to obtain a plurality of second contact holes 62 penetrating the non-conductive barrier layer 30a, each of which exposes the metal silicide layer 20, and each of which overlaps with the orthographic projections of the source 11, the drain 12, and the top gate 13b on the substrate 10. Since the etching rate of the non-conductive barrier layer 30a is greater than the etching rate of the metal silicide layer 20 under the etching conditions of the non-conductive barrier layer 30a, the metal silicide layer 20 can stop etching when the non-conductive barrier layer 30a is etched, so that the metal silicide layer 20 can protect the source 11, the drain 12, and the top gate 13b below.

[0073] (3) In step 6 of the manufacturing method of the previous embodiment, each of the initial holes 60 obtained can be arranged in one-to-one correspondence with each of the second contact holes 62 and be connected.

[0074] (4) In step 8 of the manufacturing method of the previous embodiment, SiO 2 is filled not only in the initial hole 60 but also in the second contact hole 60 .

[0075] (5) Modify step 9 in the manufacturing method of the previous embodiment as follows: Figure 6 As shown in (e) in FIG. 1 , a conductive layer 70 is deposited in the first contact hole 61 and the second contact hole 62 by physical vapor deposition, so that the conductive layer 70 in the first contact hole 61 and the corresponding second contact hole 62 is in contact with the metal silicide layer 20 .

[0076] It should be understood that the manufacturing method in this embodiment is the same as that in the above Figure 5 The similarities between the manufacturing methods described in the illustrated embodiments can be found in the above Figure 5 The related introduction in the illustrated embodiment will not be repeated any more.

[0077] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip, characterized in that: include: A transistor, a metal silicide layer, an etch stop layer, an interlayer dielectric layer and a plurality of first contact holes are stacked in sequence, the transistor comprising a source and a drain, the metal silicide layer is at least arranged on the source and the drain, the first contact hole penetrates the etch stop layer and the interlayer dielectric layer, the source overlaps with an orthographic projection of at least one of the plurality of first contact holes on the substrate, and the drain overlaps with an orthographic projection of at least one of the plurality of first contact holes on the substrate; The chip further comprises a barrier layer, wherein the barrier layer is disposed between the metal silicide layer and the etch stop layer. Under the etching conditions of the etch stop layer, the etching rate of the etch stop layer is greater than the etching rate of the barrier layer.

2. The chip according to claim 1, characterized in that: The barrier layer is made of conductive material, and the barrier layer is exposed in the first contact hole.

3. The chip according to claim 2, characterized in that: The barrier layer is made of at least one of the following materials: metal, conductive metal oxide, and conductive polymer material.

4. The chip according to any one of claims 1 to 3, characterized in that: The barrier layer is made of non-conductive material, and second contact holes corresponding to the first contact holes are arranged in the barrier layer, the second contact holes penetrate the barrier layer, and the second contact holes are connected to the corresponding first contact holes; Under the etching conditions of the barrier layer, the etching rate of the barrier layer is greater than the etching rate of the metal silicide layer.

5. The chip according to claim 4, characterized in that: The barrier layer is made of at least one of the following materials: non-conductive metal oxide and non-conductive polymer material.

6. The chip according to claim 3 or 5, characterized in that: At least part of the metal in the material used to make the barrier layer is the same as the metal in the metal silicide layer.

7. The chip according to any one of claims 1 to 6, characterized in that: The metal in the metal silicide layer includes Co.

8. The chip according to any one of claims 1 to 7, characterized in that: The thickness of the barrier layer is 2 nm to 5 nm.

9. The chip according to any one of claims 1 to 8, characterized in that: The transistor further includes a top gate, the metal silicide layer is further disposed on the top gate, and the top gate overlaps with an orthographic projection of at least one first contact hole among the plurality of first contact holes on the substrate.

10. The chip according to any one of claims 1 to 9, characterized in that: The etching stop layer and the interlayer dielectric layer are both made of non-conductive materials.

11. A method for manufacturing a chip according to any one of claims 1 to 10, characterized in that: include: forming a transistor on the substrate, the transistor comprising a source and a drain; forming a metal silicide layer at least on the source and the drain; forming a barrier layer on the metal silicide layer; Sequentially forming an etching stop layer and an interlayer dielectric layer on the substrate having the barrier layer formed thereon; Under the etching conditions of the etch stop layer, the etching rate of the etch stop layer is greater than the etching rate of the barrier layer; A plurality of first contact holes are formed penetrating the etch stop layer and the interlayer dielectric layer, wherein the source electrode overlaps with the orthographic projection of at least one of the plurality of first contact holes on the substrate, and the drain electrode overlaps with the orthographic projection of at least one of the plurality of first contact holes on the substrate.

12. The method according to claim 11, characterized in that Forming a metal silicide layer specifically includes: When the transistor further includes a top gate, the metal silicide layer is formed on the source, the drain and the top gate respectively.

13. The method according to claim 11 or 12, characterized in that Also includes: Before forming the first contact hole and after forming the interlayer dielectric layer, the substrate on which the interlayer dielectric layer is formed is subjected to a heat treatment.

14. The method according to any one of claims 11 to 13, characterized in that: Forming a barrier layer specifically includes: using a non-conductive material to form the barrier layer; It also includes: after forming the barrier layer and before forming the etch stop layer, forming a plurality of second contact holes penetrating the barrier layer, the second contact holes are arranged corresponding to and connected to the first contact holes, and under the etching conditions of the barrier layer, the etching rate of the barrier layer is greater than the etching rate of the metal silicide layer.

15. An electronic device, characterized in that: include: A circuit board and a chip as claimed in any one of claims 1 to 10, wherein the chip is arranged on the circuit board.

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