WAT test structure

Abstract

The invention discloses a WAT test structure, and belongs to the technical field of semiconductors, the WAT test structure comprises a substrate, the predetermined depth of the substrate is provided with at least one DNPPD region, the top of the DNPPD region is respectively provided with an SDP and an SDN, the SDP and the SDN are used for connecting out for an electrical test, the DNPPD region is also provided with a second DPW, at least one P-type ion doping region is arranged between the second DPW and the SDP, and the SDN is used for connecting out the SDP and the SDN. At least one N-type ion doping region is arranged between the SDN and the DNPPD region to connect the SDP and the second DPW, and at least one N-type ion doping region is arranged between the SDN and the DNPPD region to connect the SDN and the DNPPD region. The SDP and the SDN on the DNPPD area are connected out, the resistance of the DNPPD area is tested, and the ion implantation angles of the thick glue layers in the pixel structures of different sizes are evaluated through the resistance value.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a WAT ​​test structure. Background Art

[0002] CMOS Image Sensor (CIS) is a semiconductor device that converts optical images into electrical signals. It is widely used in digital cameras, smart phones, medical equipment and other fields. As an important layer of CIS, the thick layer (DNPPD / DPW) has a great impact on pixel performance. However, in the current CIS process flow, the thick layer has problems such as long tape-out cycle, low efficiency of thick layer evaluation, inline indicators that are difficult to reflect the difference in PR morphology, and many influencing factors that cannot be distinguished, making it difficult to fix the optimal conditions. The photoresist (PR), critical dimension (CD) and ion implantation (IMP) of the thick layer have an important impact on its performance. Among them, the ion implantation angle of the thick layer directly affects the shape and size of the pixel, and then affects key parameters such as photosensitivity, quantum efficiency and dark current. Controlling and monitoring the accuracy and consistency of the ion implantation angle is the key to achieving excellent image quality.

[0003] With the trend of miniaturization and high pixel of CIS in digital cameras and smart phones, the pixel size is constantly shrinking, and the precision requirements for ion implantation angle control are getting higher and higher. At the same time, the ion implanter often produces deviations after a certain period of operation, which seriously affects the accuracy of the ion implantation angle, so it is also necessary to monitor the ion implantation angle. In the prior art, the control and monitoring of the ion implantation angle requires secondary ion mass spectrometry (SIMS) comparison of standard wafers to compare the distribution curves of the implanted impurities in the substrate. By comparing the SIMS curves of different ion implantation angles or the same ion implantation angle at different times, the accuracy of the ion implantation angle of the current ion implanter is shown. However, it takes at least 10 hours to accurately determine the ion implantation angle using SIMS analysis, which affects the utilization and production capacity of the ion implanter, and the wafer cost is relatively high.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a WAT ​​test structure to solve the problem of long time consumption in measuring the ion implantation angle.

[0006] In order to solve the above technical problems, the present invention provides a WAT ​​test structure, including a substrate, at least one DNPPD region is arranged at a predetermined depth of the substrate, SDP and SDN are arranged on the top of the DNPPD region respectively, for connection for electrical testing, a second DPW is also arranged in the DNPPD region, at least one P-type ion doping region is arranged between the second DPW and the SDP to connect the SDP and the second DPW, and at least one N-type ion doping region is arranged between the SDN and the DNPPD region to connect the SDN and the DNPPD region.

[0007] Preferably, an NFD is arranged between the SDN and the DNPPD area, the top of the NFD at least covers a partial area of ​​the SDN, and the bottom of the NFD is connected to the DNPPD area.

[0008] Preferably, N3V and NPPDTX are further arranged between the SDN and the DNPPD area, the N3V at least covers the overlapping area of ​​the NFD and the SDN, and the NPPDTX is arranged at the junction of the NFD and the DNPPD area.

[0009] Preferably, the CD value of the NFD is greater than the CD value of the SDN, and the CD values ​​of the NPPDTX and the N3V are both greater than the CD value of the NFD.

[0010] Preferably, an ISO is arranged between the second DPW and the SDP, the top of the ISO at least covers a partial area of ​​the SDP, and the bottom of the ISO is connected to the second DPW.

[0011] Preferably, a PPPD is further arranged between the second DPW and the SDP, the PPPD at least covers the overlapping area of ​​the ISO and the SDP, and the CD value of the PPPD is greater than the CD value of the ISO, and the bottom of the ISO is lower than the bottom of the PPPD.

[0012] Preferably, the CD value of the ISO is greater than the CD value of the SDP.

[0013] Preferably, STIs are also provided on both sides of the SDP.

[0014] Preferably, the SDP and SDN are both connected through a metal interconnection structure.

[0015] Preferably, a plurality of DNPPD regions are arranged at a predetermined depth of the substrate, the DNPPD regions are isolated by a first DPW, and the SDPs and SDNs at the tops of the plurality of DNPPD regions are connected correspondingly to connect the plurality of DNPPD regions in series.

[0016] In the WAT test structure provided by the present invention, the SDP and SDN on the DNPPD area are connected, the resistance of the DNPPD area is tested, the ion implantation angle of the thick glue layer in the pixel structure of different sizes is evaluated by the resistance value, and ions are additionally injected on the SDP and SDN to form corresponding doping areas, so that the DNPPD area is connected to the SDN60, and the second DPW is connected to the SDP, so as to avoid the difficulty in connecting the SDP and SDN due to the small number of IMP layers, which affects the WAT test. Other device areas are designed in a conventional manner and can be equipped with ShortFlow for initial screening and confirmation, so as to solve the problem that the influencing factors of the CIS thick glue layer are many and cannot be distinguished, thereby achieving the purpose of shortening the tape-out cycle and improving the evaluation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0018] Figure 1 is a schematic diagram of a top view of the structure of an embodiment of the present invention;

[0019] Figure 2 is a schematic cross-sectional structural diagram of an SDP region according to an embodiment of the present invention;

[0020] Figure 3 is a schematic cross-sectional structural diagram of an SDN area according to an embodiment of the present invention;

[0021] Figure 4 This is the relationship between DNPPD series resistance and thick glue IMP angle;

[0022] Figure 5 is the fitting curve of DNPPD series resistance and Inline CD.

[0023] In the attached figure:

[0024] 10. Substrate; 20. DNPPD region; 30. First DPW; 40. Second DPW; 50. SDP; 51. PPPD; 52. ISO; 60. SDN; 61. N3V; 62. NFD; 63. NPPDTX; 70. STI; 80. Metal interconnect structure. DETAILED DESCRIPTION

[0025] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0026] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. The term "proximal end" is usually the end close to the operator, and the term "distal end" is usually the end close to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" usually refer to two corresponding parts, which include not only the endpoints. The terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of the two elements or the interaction relationship between the two elements. In addition, as used in the present invention, an element is arranged on another element, which usually only means that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] The study found that using conventional methods to measure the ion implantation angle of thick photoresist layers (DPW / DNPPD) is time-consuming and cannot obtain results quickly and intuitively.

[0028] Further research found that there is a certain correlation between the DNPPD resistance and the ion implantation angle of the thick layer (DPW / DNPPD), such as Figure 4 As shown in the figure, the relationship between the series resistance of multiple DNPPDs and the ion implantation angle of the thick layer, the horizontal axis is waferid (indicating the wafer number), and the data points of different wafers use different colors, see the color marking at the bottom of the coordinate axis, the vertical axis represents the series resistance RS of multiple DNPPDs, and Average represents the average value of the nine test points on the current wafer. The blue text in the figure represents the experimental parameters of each wafer, which are the ion implantation angle + and -, Figure 4 The DPW in Figure 2The second DPW in the figure shows that the DNPPD constitutes a WAT ​​test structure that can characterize the IMP angle. For the provided BSL (Baseline), when the IMP (Implantation) angle is positive, the DNPPD resistance is lower than the resistance value under the BSL. When the IMP angle is negative, the DNPPD resistance is higher than the resistance value under the BSL.

[0029] However, there is no correlation between Inline CD (Critical Dimension) and DNPPD resistance, such as Figure 5 As shown, the horizontal axis is DNPPD CD, the vertical axis is RS, the legend numbers below the coordinate axis represent wafer ID, DNPPD series resistance RS and Inline CD fitting curve, correlation coefficient R 2 It is only 0.02, and DNPPD can be used to form a WAT ​​test structure. Since the test result is not affected by CD, it can effectively and solely reflect the change of ion implantation angle of thick glue layer.

[0030] Based on this, the core idea of ​​the present invention is to solve the problems existing in the prior art by designing a WAT ​​test structure that can only reflect the ion implantation angle of the thick glue layer for electrical testing. The influencing factors of the thick glue layer can be distinguished through different WAT TK parameters, and Short Flow can be used for initial screening and confirmation at the same time, which is of great significance to shortening the tape-out cycle and improving evaluation efficiency.

[0031] For details, please refer to Figure 1-Figure 5 , which is a schematic diagram of an embodiment of the present invention. Figure 1 As shown, a WAT ​​test structure for testing an IMP angle includes a substrate 10, at least one DNPPD region 20 is arranged at a predetermined depth of the substrate 10, and the top of the DNPPD region 20 is respectively provided with an SDP (Shallw / Deep N+Implantation, shallow / deep N-type ion implantation region) 50 and an SDN (S / D P+Implantation, shallow / deep P-type ion implantation region) 60 for connection for electrical testing, and a second DPW (DeepP well, deep P-type well region) 40 is also arranged in the DNPPD region (Deep N+photo diode connection, photodiode deep N-type well region) 20, at least one P-type ion doping region is arranged between the second DPW40 and the SDP50 to connect the SDP50 and the second DPW40, and at least one N-type ion doping region is arranged between the SDN60 and the DNPPD region 20 to connect the SDN60 and the DNPPD region 20.

[0032] In one embodiment, SDP50 and SDN60 on the DNPPD area 20 are connected, the resistance of the DNPPD area 20 is tested, the IMP angle of the thick glue layer (DNPPD / DPW) in pixel structures of different sizes is evaluated by the resistance value, and ions are added to SDP50 and SDN60 to form corresponding doping areas, so that the DNPPD area 20 and SDN60 are connected, and the second DPW40 and SDP50 are connected, so as to avoid the difficulty in connecting SDP50 and SDN60 due to the small number of IMP layers, thereby affecting the WAT test. Other device areas are designed in a conventional manner, and Short Flow can be used for initial screening and confirmation, so as to solve the problem that there are many factors affecting the CIS thick glue layer that cannot be distinguished, thereby shortening the tape-out cycle and improving the evaluation efficiency.

[0033] Normally, conventional SDP50 and SDN60 are often small and shallow. Even if the injection energy is increased, it is difficult to increase the depth of SDP50 and SDN60. They are directly connected to the DNPPD area 20 or the second DPW40 to form contact, which makes the process difficult. To expand the ion injection range of SDP50 and SDN60, it is necessary to reset the mask. An NFD (N+Implantation for Floating Diffusion, floating diffusion area N-type ion injection area) 62 is arranged between the SDN60 and the DNPPD area 20. The top of the NFD62 at least covers a part of the SDN60, and the bottom is connected to the DNPPD area 20.

[0034] like Figure 3 As shown, the NFD 62 is arranged longitudinally, the top of the NFD 62 is flush with the top of the SDN 60 , and the CD value of the NFD 62 is greater than the CD value of the SDN 60 , so that the SDN 60 can be completely shielded and the SDN 60 and the DNPPD area 20 are well connected.

[0035] Specifically, N3V (N+Low Dose Drain Implantation for 3.3V device, 3.3V device N-type lightly doped region) 61 and NPPDTX (N+photo diode for transfer transistor, photodiode N-type doped region for transfer transistor) 63 are also arranged between the SDN 60 and the DNPPD region 20, the N3V 61 at least covers the overlapping area of ​​the NFD 62 and the SDN 60, and the NPPDTX 63 is arranged at the junction of the NFD 62 and the DNPPD region 20. The CD (Critical Dimension) value of the NFD 62 is greater than the CD value of the SDN 60, and the CD values ​​of the NPPDTX 63 and the N3V 61 are both greater than the CD value of the NFD 62.

[0036] Among them, since SDN60 is often a narrow and shallow ion implantation area, it is difficult to directly connect the DNPPD area 20 through an ion implantation area, and the process requirements are relatively high. N3V61 and NPPDTX63 are respectively set at the top and bottom of NFD62. N3V61 and NPPDTX63 are both wide and short N-type doping areas, which strengthen the connection between the two ends of NFD62 and SDN60 and DNPPD area 20.

[0037] It can be understood that N3V61, NFD62 and NPPDTX63 are N-type ion implantation areas with specific doping concentration range and injection energy range in the conventional process flow. The specific parameters are not repeated here. Therefore, there is no need to remake the mask plate. When measuring the resistance of the entire WAT test structure, the influence of other doping areas on the thick glue layer can also be tested by setting the ion implantation parameters of N3V61, NFD62 and NPPDTX63.

[0038] like Figure 2 As shown, ISO52 is arranged between the second DPW40 and the SDP50, the top of ISO52 at least covers a part of the SDP50, and the bottom is connected to the second DPW40. STI (Shallow Trench Isolation) 70 is also arranged on both sides of the SDP50. ISO52 is a P-type isolation ion implantation area (Isolation between pixel area device and PD, isolation area between pixel device area and photodiode), which is located in the STI70 area or side wall, PPPD (photodiode P-type doping area) 51 is also arranged between the second DPW40 and the SDP50, the PPPD51 at least covers the overlapping area of ​​ISO52 and the SDP50, and the CD value of PPPD51 is greater than the CD value of ISO52, and the bottom of ISO52 is lower than the bottom of PPPD51.

[0039] Exemplarily, both ISO52 and PPPD51 completely cover SDP50 , wherein PPPD51 is wide and shallow, used to connect SDP50 and ISO52 , and ISO52 is relatively narrow and deep, connecting SDP50 and PPPD51 at the top and contacting the second DPW40 at the bottom.

[0040] In one embodiment, the CD value of the ISO 52 is greater than the CD value of the SDP 50. The CD value or width of the ISO 52 is greater than the distance between the STI 70, and the implantation range is greater than the area defined by the STI 70.

[0041] Similarly, PPPD51 and ISO52 are P-type ion implantation areas with specific doping concentration ranges and implantation energy ranges in conventional process flows. The specific parameters are not repeated here. Therefore, there is no need to remake the mask plate. When measuring the resistance of the entire WAT test structure, the influence of other doping areas on the thick glue layer can also be tested by setting the ion implantation parameters of PPPD51 and ISO52.

[0042] Specifically, the SDP 50 and the SDN 60 are both connected through a metal interconnection structure 80. The metal interconnection structure 80 includes a CT (Contact, contact hole) and an M1 (Metal 1, first metal layer) for interconnection.

[0043] like Figure 1 As shown, a plurality of DNPPD regions 20 are provided at a predetermined depth of the substrate 10, and the DNPPD regions 20 are isolated by a first DPW 30, and the SDP 50 and SDN 60 at the top of the plurality of DNPPD regions 20 are connected correspondingly, so as to connect the plurality of DNPPD regions 20 in series. In the WAT test structure, a plurality of DNPPD regions 20 can be provided to amplify the resistance value change of the DNPPD region 20, better characterize the change of the ion implantation angle, and help fit the ion implantation angle and the resistance value in the research process. The DNPPD regions 20 are connected end to end through a metal interconnection structure 80, and the DNPPD regions 20 can be formed using the same ion implantation parameters or formed simultaneously using one ion implantation process, and the number of DNPPD regions 20 connected in series is not specifically limited here.

[0044] The second DPW 40 can be formed by two ion implantation processes. In the pixel structure, the DPW plays a role in isolating the N-well and the substrate 10, which can suppress the leakage of part of the N-well and prevent the noise of the substrate 10 from affecting the device.

[0045] The present disclosure provides a WAT ​​test structure, in which a DNPPD area 20 is connected in series for WAT testing, the purpose of which is to evaluate the IMP angle of thick glue layers (DNPPD / DPW) in pixel structures of different sizes, and to supplement corresponding ions at the bottom of SDP50 and SDN60 to form an electrical channel to prevent the failure of SDP50 and SDN60 to be connected due to a small number of IMP layers, thereby affecting the WAT test. AA (Active Area), DNPPD area 20, DPW, VTG (Vertical Trench Gate), Poly (polycrystalline silicon), NPPDTX63, NFD62, N3V61, ISO52, PPPD51, CT, and M1 are designed according to conventional devices, and Short Flow is used for initial screening and confirmation, so as to solve the problem that many factors affecting the CIS thick glue layer cannot be distinguished, and the purpose of shortening the tape-out cycle and improving the evaluation efficiency is achieved. Furthermore, through the WAT test structure, the fluctuation of the ion implantation angle of the DNPPD area 20 and the second DPW40 can be monitored separately to solve the problem that there are many factors affecting the thick CIS glue layer and it cannot be distinguished. The design structure has certain flexibility and adaptability and can be extended to PD (photo diode) / STI designs of sizes such as 0.7 / 1.1 / 2.0 / 5.0μm. The short process verification cycle can be reduced from the original 3 months to 1 month, effectively shortening the tape-out cycle.

[0046] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A WAT test structure for testing an IMP angle, characterized in that: The invention comprises a substrate, wherein at least one DNPPD region is arranged at a predetermined depth of the substrate, and an SDP and an SDN are arranged at the top of the DNPPD region respectively for connection for electrical testing, and a second DPW is also arranged in the DNPPD region, and at least one P-type ion doping region is arranged between the second DPW and the SDP to connect the SDP and the second DPW, and at least one N-type ion doping region is arranged between the SDN and the DNPPD region to connect the SDN and the DNPPD region.

2. The WAT test structure according to claim 1, characterized in that: An NFD is arranged between the SDN and the DNPPD area, the top of the NFD at least covers a partial area of ​​the SDN, and the bottom of the NFD is connected to the DNPPD area.

3. The WAT test structure according to claim 2, characterized in that: N3V and NPPDTX are further arranged between the SDN and the DNPPD area, the N3V at least covers the overlapping area of ​​the NFD and the SDN, and the NPPDTX is arranged at the junction of the NFD and the DNPPD area.

4. The WAT test structure according to claim 3, characterized in that: The CD value of the NFD is greater than the CD value of the SDN, and the CD values ​​of the NPPDTX and the N3V are both greater than the CD value of the NFD.

5. The WAT test structure according to claim 1, characterized in that: An ISO is arranged between the second DPW and the SDP, wherein the top of the ISO at least covers a partial area of ​​the SDP, and the bottom of the ISO is connected to the second DPW.

6. The WAT test structure according to claim 5, characterized in that: A PPPD is also arranged between the second DPW and the SDP, the PPPD at least covers the overlapping area of ​​the ISO and the SDP, and the CD value of the PPPD is greater than the CD value of the ISO, and the bottom of the ISO is lower than the bottom of the PPPD.

7. The WAT test structure according to claim 5, characterized in that: The CD value of the ISO is greater than the CD value of the SDP.

8. The WAT test structure according to claim 1, characterized in that: STIs are also provided on both sides of the SDP.

9. The WAT test structure according to claim 1, characterized in that: The SDP and SDN are both connected through a metal interconnection structure.

10. The WAT test structure according to claim 1, characterized in that: A plurality of DNPPD regions are arranged at a predetermined depth of the substrate, the DNPPD regions are isolated by a first DPW, and the SDPs and SDNs at the tops of the plurality of DNPPD regions are connected correspondingly to connect the plurality of DNPPD regions in series.

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