Self-recovery method and circuit of chip ESD (Electro-Static Discharge) protection system
By designing a self-recovery method in the chip ESD protection system, using electrostatic interference detection and ESD pulse signal processing, the chip system's automatic self-recovery after ESD events is achieved, solving the problem that the existing ESD protection solution cannot be self-recovered, and enhancing the anti-interference and stability of the chip.
Patent Information
- Application Number
- CN202411979798.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-13
AI Technical Summary
The existing ESD protection scheme cannot automatically identify ESD shock events, resulting in the chip system being unable to recover after the ESD event, affecting the chip's anti-interference and stability.
A self-recovery method for chip ESD protection system is designed to detect electrostatic interference, generate ESD pulse signals, and realize self-recovery of the system by using latch and multi-bit redundancy control methods.
It realizes that the chip system automatically recognizes and recovers itself after the ESD event occurs, enhancing the chip's anti-interference and stability, and avoids chip interface abnormalities and power instability caused by ESD shock.
Smart Images
Figure CN119994819A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic equipment, and in particular to a self-recovery method and circuit of a chip ESD protection system. Background Art
[0002] Electrostatic discharge (ESD) is the main cause of damage to electronic components or integrated circuit systems. Since static electricity usually has a very high instantaneous voltage, this damage is usually destructive and permanent, so preventing electrostatic damage is the focus of all IC design and manufacturing. There are currently two solutions for electrostatic protection of electronic equipment. On the one hand, ESD protection is added to the chip design so that large currents can be discharged through the chip ESD devices, such as designing I / O Pads with high ESD tolerance for the chip's input / output pins, or integrating ESD protection diodes around I / O Pads, or implementing additional ESD protection measures for internal circuits, especially sensitive areas, such as analog circuits, power circuits, and core logic circuits. On the other hand, ESD circuit protection is added at the PCB board level to ensure the safety of electronic equipment, such as using TVS diodes, multi-layer board design, ferrite beads, and LC filters.
[0003] However, the above two ESD protection solutions are aimed at strengthening ESD discharge to prevent the chip or peripheral equipment from being damaged by ESD. In the chip application system, ESD events may cause the chip system to encounter the following two problems:
[0004] (1) The ESD shock event causes some high-speed analog circuit interfaces of the chip to malfunction, causing the peripheral devices connected to them, such as the MIPI screen or HDMI peripherals, to work abnormally. Such problems usually require re-initialization of the analog PHY or re-initialization and configuration of the peripheral devices. It can be seen that there are potential defects in the ESD protection of the chip design, which affects the working performance of the chip.
[0005] (2) ESD shock events can cause power supply voltage instability, resulting in the main control chip crashing. Such problems are usually manually reset or restarted, which greatly affects the chip's anti-interference and stability.
[0006] It can be seen that the existing ESD protection solutions cannot solve the above two problems. Therefore, there is a need for an ESD protection circuit and method that can automatically identify ESD impact events and enable the system to self-recover and enhance the chip's anti-interference and stability. Summary of the invention
[0007] The present invention provides a self-recovery method and circuit for a chip ESD protection system, which are mainly used to solve the problem that existing ESD protection solutions cannot solve the problem that ESD impact events affect the anti-interference and stability of the chip, thereby achieving the effect of automatically identifying ESD impact events and enabling the system to self-recover, and enhancing the anti-interference and stability of the chip.
[0008] The present invention achieves the above-mentioned purpose through the following technical solutions:
[0009] A self-recovery method for a chip ESD protection system, comprising:
[0010] S1: Detect and determine whether the chip generates electrostatic interference. If so, connect the ESD discharge path for electrostatic discharge and synchronously output the electrostatic voltage detection signal; if not, continue to perform electrostatic detection.
[0011] S2: Outputting an ESD pulse signal after level conversion of the electrostatic voltage detection signal.
[0012] S3: Input the ESD pulse signal as a clock signal into a latch, and perform edge sampling on the ESD pulse signal. If a high-level signal is sampled, it is recorded as an ESD event occurrence signal.
[0013] S4: After inverting the ESD pulse signal, edge sampling is performed again. If a high-level signal is collected, it is recorded as an ESD event end signal.
[0014] S5: Input an asynchronous reset signal, and use a multi-bit redundant control method to perform logic control on the reset level signal input to the reset end of the latch.
[0015] S6: The latch outputs a self-recovery signal according to the reset level signal to achieve a self-recovery response of the chip system.
[0016] A further solution is that step S5 further includes:
[0017] S51: Obtain a crystal oscillator clock signal through an external crystal oscillator, and input the crystal oscillator clock signal as a clock signal source to a multi-bit register and an asynchronous reset synchronous evacuation circuit.
[0018] S52: configuring a software configuration value of a multi-bit register, locking the software configuration value in the multi-bit register, and setting a multi-bit constant.
[0019] S53: Processing the asynchronous reset signal through the asynchronous reset synchronous evacuation circuit, and outputting an asynchronous reset synchronous evacuation signal.
[0020] A further solution is that step S5 further includes:
[0021] S54: Performing a logical judgment on whether the software configuration is equal to the multi-bit constant, when the software configuration is equal to the multi-bit constant, the reset level signal is output as a valid reset level signal.
[0022] S55: Performing a logic judgment on whether the asynchronous reset synchronous withdrawal signal is a valid reset signal. When the asynchronous reset synchronous withdrawal signal is a valid reset signal, the reset level signal is output as a valid reset level signal.
[0023] A further solution is that, in the ESD event triggered reset mode, the logic control formula of the reset level signal input to the reset end of the latch is:
[0024] Rn = RSTN_SYNC & ~(Q1[n-1:0] == value) Formula (1)
[0025] Among them, RSTN_SYNC is the asynchronous reset synchronization withdrawal signal, Q1[n-1:0] is the software configuration value output by the multi-bit register in this mode, and value is the multi-bit constant.
[0026] A further solution is that step S5 further includes:
[0027] S56: Setting a soft reset signal, and using two multi-bit counters to respectively determine whether the ESD complete elimination setting time and the reset setting time have been reached.
[0028] S57: If the reset setting time is reached, the soft reset signal is set to 0. At this time, the soft reset signal will set the ESD event occurrence signal and the ESD event end signal to 0.
[0029] S58: Performing a logic judgment on whether the soft reset signal is a valid reset signal. When the soft reset signal is a valid reset signal, the reset level signal is output as a valid reset level signal.
[0030] A further solution is that step S55 further includes:
[0031] S56 - 1 : When the ESD event occurrence signal is 1, the first multi-bit counter starts counting.
[0032] S56-2: When the count value of the first multi-bit counter reaches the ESD complete elimination setting time, the soft reset signal is triggered to 1, and the second multi-bit counter starts counting.
[0033] S56-3: When the count value of the second multi-bit counter reaches the reset setting time, the count value of the second multi-bit counter is reset to 0.
[0034] A further solution is that, in the soft reset mode, the logic control formula of the reset level signal input to the reset terminal of the latch is:
[0035] Rn = RSTN_SYNC & ~(Q2[n-1:0] == value)&(~esd_wreset) Formula (2)
[0036] Among them, RSTN_SYNC is the asynchronous reset synchronization withdrawal signal, Q2[n-1:0] is the software configuration value output by the multi-bit register in this mode, value is the multi-bit constant, and esd_wreset is the soft reset signal.
[0037] A further solution is to set different bit values to correspond to the ESD event triggered reset mode and the soft reset mode respectively, and select different modes to realize system self-recovery by configuring the software configuration value of the corresponding bit value in the multi-bit register.
[0038] A self-recovery circuit of a chip ESD protection system, using the self-recovery method of a chip ESD protection system, comprising an ESD detection circuit, an ESD discharge circuit, a drive circuit, a level conversion circuit and a digital logic circuit, wherein the ESD detection circuit is used to detect the electrostatic voltage of the chip and output an electrostatic voltage detection signal to the ESD discharge circuit and the drive circuit respectively; the ESD discharge circuit is used to turn on or off ESD discharge according to the electrostatic detection signal; the drive circuit drives the electrostatic voltage detection signal and outputs it to the level conversion circuit; the level conversion circuit is used to convert the electrostatic voltage detection signal into a level signal to generate an ESD pulse signal; and the digital logic circuit is used to perform system self-recovery logic control according to the ESD pulse signal.
[0039] A further solution is that the digital logic circuit includes a first latch, a second latch, an inverter and a reset circuit, the CK terminal of the first latch is connected to the ESD pulse signal, the D terminal thereof is connected to a high level, and the RN terminal thereof is connected to the reset circuit, for sampling the rising edge of the ESD pulse signal and latching it as 1; the CK terminal of the second latch is connected to the ESD pulse signal through the inverter, the D terminal thereof is connected to a high level, and the RN terminal thereof is connected to the reset circuit, for sampling the rising edge of the ESD pulse signal after inversion and latching it as 1; the reset circuit adopts a multi-bit redundant control method to realize multi-mode reset logic control, for latching both the first latch and the second latch as 0 after the ESD event ends.
[0040] It can be seen that the present invention has the following beneficial effects:
[0041] 1. The present invention adds an ESD detection circuit to the traditional ESD discharge circuit to perform real-time electrostatic detection on the high-voltage power supply of the chip, and records the detected ESD events through a digital logic circuit, and promptly sends an interrupt signal to the system main control or outputs the ESD state to the control circuit according to the ESD event, so that the chip system can take corresponding protection operations in time, thereby avoiding the problem of chip interface abnormality caused by ESD impact.
[0042] 2. The present invention uses a crystal oscillator clock as a clock source to access a multi-bit register and an asynchronous reset synchronous evacuation circuit. Compared with the traditional method of using an internal clock, the crystal oscillator clock can ensure the synchronization and accuracy of signal transmission by providing a stable and accurate clock signal.
[0043] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 It is a flow chart of the self-recovery method of the chip ESD protection system according to an embodiment of the present invention.
[0045] Figure 2 A circuit diagram of an asynchronous reset synchronous evacuation circuit according to an embodiment of the present invention.
[0046] Figure 3 Schematic diagram of a self-recovery circuit of a chip ESD protection system according to an embodiment of the present invention.
[0047] Figure 4 It is a schematic diagram of an ESD detection circuit, a driving circuit and an ESD discharge circuit according to an embodiment of the present invention.
[0048] Figure 5 Schematic diagram of a multi-bit register according to an embodiment of the present invention. DETAILED DESCRIPTION
[0049] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0050] A self-recovery method embodiment of a chip ESD protection system
[0051] See also Figure 1 The present invention relates to a self-recovery method of a chip ESD protection system, comprising:
[0052] S1: Detect and determine whether the chip generates electrostatic interference. If so, connect the ESD discharge path for electrostatic discharge and synchronously output the electrostatic voltage detection signal; if not, continue to perform electrostatic detection.
[0053] S2: Outputting an ESD pulse signal after level conversion of the electrostatic voltage detection signal.
[0054] Specifically, this embodiment converts the electrostatic voltage detection signal from a voltage signal from generation to the end of discharge into a pulse signal through a level conversion circuit. When the pulse signal is at a high level, it indicates the presence of electrostatic interference, and when it is at a low level, there is no electrostatic interference; its rising edge indicates the occurrence of an ESD event, and its falling edge indicates the end of the ESD event.
[0055] S3: Input the ESD pulse signal as a clock signal into a latch, and perform edge sampling on the ESD pulse signal. If a high-level signal is sampled, it is recorded as an ESD event occurrence signal.
[0056] Specifically, step S3 of this embodiment further includes:
[0057] S31: Sending the ESD event occurrence signal to the CPU of the chip or an external control circuit;
[0058] S32: The CPU of the chip or the external control circuit deploys ESD event-related response operations in advance according to the ESD event occurrence signal.
[0059] S4: After inverting the ESD pulse signal, edge sampling is performed again. If a high-level signal is collected, it is recorded as an ESD event end signal.
[0060] S5: Input an asynchronous reset signal, and use a multi-bit redundant control method to perform logic control on the reset level signal input to the reset end of the latch.
[0061] S6: The latch outputs a self-recovery signal according to the reset level signal to achieve a self-recovery response of the chip system.
[0062] In this embodiment, step S5 further includes:
[0063] S51: Obtain a crystal oscillator clock signal through an external crystal oscillator, and input the crystal oscillator clock signal as a clock signal source to a multi-bit register and an asynchronous reset synchronous evacuation circuit
[0064] S52: configuring a software configuration value of a multi-bit register, locking the software configuration value in the multi-bit register, and setting a multi-bit constant.
[0065] S53: Processing the asynchronous reset signal through the asynchronous reset synchronous evacuation circuit, and outputting an asynchronous reset synchronous evacuation signal.
[0066] See also Figure 2 Specifically, the asynchronous reset synchronous evacuation circuit of this embodiment includes two stages of D flip-flops, the CK terminals of the two D flip-flops are both connected to the system crystal clock, and the RN terminals thereof are both connected to the asynchronous reset signal; the D terminal of the first stage D flip-flop is connected to the high level signal, and its output terminal is connected to the D terminal of the second stage D flip-flop. The second stage D flip-flop outputs the asynchronous reset synchronous evacuation signal.
[0067] Specifically, in this embodiment, when an asynchronous reset is performed, the asynchronous reset signal flips from 1 to 0, and the two D flip-flops are immediately reset, that is, the output asynchronous reset synchronous withdrawal signal will be immediately pulled down to the low-level reset system. It can be seen that the reset action is not controlled by the clock at this time, so asynchronous reset can be achieved; when reset withdrawal is performed, the asynchronous reset signal flips from 0 to 1, and the reset of the two D flip-flops is cancelled and starts to work normally. However, the input high-level signal needs to go through two cycles to reach the output end. Two cycles are sufficient to eliminate the metastable state caused by the reset and ensure that the reset signal perceived by the system is on the system clock edge. It can be seen that the reset withdrawal behavior at this time is controlled by the clock and can achieve synchronous cancellation.
[0068] In this embodiment, step S5 further includes:
[0069] S54: Performing a logical judgment on whether the software configuration is equal to the multi-bit constant, when the software configuration is equal to the multi-bit constant, the reset level signal is output as a valid reset level signal.
[0070] S55: Performing a logic judgment on whether the asynchronous reset synchronous withdrawal signal is a valid reset signal. When the asynchronous reset synchronous withdrawal signal is a valid reset signal, the reset level signal is output as a valid reset level signal.
[0071] In this embodiment, in the ESD event triggered reset mode, the logic control formula of the reset level signal input to the reset end of the latch is:
[0072] Rn = RSTN_SYNC & ~(Q1[n-1:0] == value) Formula (1)
[0073] Among them, RSTN_SYNC is the asynchronous reset synchronization withdrawal signal, Q1[n-1:0] is the software configuration value output by the multi-bit register in this mode, and value is the multi-bit constant.
[0074] Specifically, in this embodiment, Rn=0 is assumed to be a valid reset level signal, and then from formula (1) we can get:
[0075] When RSTN_SYNC=0, Rn=0, the latch latches 0 and outputs the self-recovery signal;
[0076] When Q[n-1:0] is equal to value, Rn=0, the latch latches 0 and outputs the self-recovery signal.
[0077] In this embodiment, step S5 further includes:
[0078] S56: Setting a soft reset signal, and using two multi-bit counters to respectively determine whether the ESD complete elimination setting time and the reset setting time have been reached.
[0079] S57: If the reset setting time is reached, the soft reset signal is set to 0. At this time, the soft reset signal will set the ESD event occurrence signal and the ESD event end signal to 0.
[0080] Specifically, this embodiment sends the soft reset signal as an interrupt to the CPU of the chip to trigger the interrupt handler of the chip system to process the ESD interrupt, thereby automatically triggering the hot reset signal of the system to achieve system self-recovery.
[0081] S58: Performing a logic judgment on whether the soft reset signal is a valid reset signal. When the soft reset signal is a valid reset signal, the reset level signal is output as a valid reset level signal.
[0082] In this embodiment, step S56 further includes:
[0083] S56 - 1 : When the ESD event occurrence signal is 1, the first multi-bit counter starts counting.
[0084] S56-2: When the count value of the first multi-bit counter reaches the ESD complete elimination setting time, the soft reset signal is triggered to 1, and the second multi-bit counter starts counting.
[0085] Specifically, this embodiment sets the ESD elimination time of the system according to the actual system. The set time is redundant compared with the actual ESD elimination time. The first multi-bit counter can play a role in delay control when the ESD event occurs, thereby ensuring that the system is in a normal control state.
[0086] S56-3: When the count value of the second multi-bit counter reaches the reset setting time, the count value of the second multi-bit counter is reset to 0.
[0087] Specifically, the second multi-bit counter in this embodiment is used to control the pulse width of the system hot reset, and the counting time is set according to the needs of the system.
[0088] In this embodiment, in the soft reset mode, the logic control formula of the reset level signal input to the reset terminal of the latch is:
[0089] Rn = RSTN_SYNC & ~(Q2[n-1:0] == value)&(~esd_wreset) Formula (2)
[0090] Among them, RSTN_SYNC is the asynchronous reset synchronization withdrawal signal, Q2[n-1:0] is the software configuration value output by the multi-bit register in this mode, value is the multi-bit constant, and esd_wreset is the soft reset signal.
[0091] In this embodiment, different bit values are set to correspond to the ESD event triggered reset mode and the soft reset mode respectively, and different modes are selected to realize system self-recovery by configuring the software configuration value of the corresponding bit value in the multi-bit register.
[0092] A self-recovery circuit embodiment of a chip ESD protection system
[0093] See also Figure 3 The present invention relates to a self-recovery circuit of a chip ESD protection system, and uses the self-recovery method of a chip ESD protection system, including an ESD detection circuit 10, an ESD discharge circuit 20, a drive circuit 30, a level conversion circuit 4050 and a digital logic circuit 50. The ESD detection circuit 10 is used to detect the electrostatic voltage of the chip and output an electrostatic voltage detection signal to the ESD discharge circuit 20 and the drive circuit 30 respectively; the ESD discharge circuit 20 is used to turn on or off the ESD discharge according to the electrostatic detection signal; the drive circuit 30 drives the electrostatic voltage detection signal and outputs it to the level conversion circuit 4050; the level conversion circuit 4050 is used to convert the electrostatic voltage detection signal into a level signal to generate an ESD pulse signal; the digital logic circuit 50 is used to perform system self-recovery logic control according to the ESD pulse signal.
[0094] See also Figure 4Specifically, the ESD detection circuit 10 of this embodiment includes a CMOS inverter and a current limiting circuit. The CMOS inverter is composed of a first PMOS transistor and a first NMOS transistor to form a complementary structure. The source of the first PMOS transistor is connected to the power supply voltage terminal of the chip, and the source of the first NMOS transistor is connected to the low-level voltage terminal of the chip. The common gate thereof is connected to the power supply voltage terminal of the chip through the current limiting circuit, and the common drain thereof outputs an electrostatic voltage detection signal to the ESD discharge circuit 20 and the drive circuit 30 respectively.
[0095] Specifically, the current limiting circuit described in this embodiment includes a first resistor and a capacitor connected in series, and the common gate of the CMOS inverter is connected to the power supply voltage end of the chip through the first resistor, and is connected to the low-level voltage end of the chip through the capacitor.
[0096] Specifically, in this embodiment, when there is no electrostatic interference at the power supply voltage end of the chip, a high-level signal is input to the common gate of the CMOS inverter, and the electrostatic voltage detection signal outputted by the CMOS inverter is a low-level signal, and the low-level electrostatic voltage detection signal controls the ESD discharge circuit 20 to be in a closed state;
[0097] When electrostatic interference exists at the power supply voltage terminal of the chip, the capacitor is in a low resistance state, the common gate of the CMOS inverter is pulled to a low level, and the electrostatic voltage detection signal outputted by it is at a high level. The high-level electrostatic voltage detection signal controls the ESD discharge circuit 20 to start ESD discharge.
[0098] Specifically, the ESD detection circuit 10 of this embodiment further includes a pull-down resistor, which is connected in parallel between the drain output terminal and the low-level voltage terminal of the CMOS inverter to ensure that the electrostatic detection signal maintains a low-level state when there is no electrostatic interference.
[0099] In this embodiment, the digital logic circuit 50 includes a first latch, a second latch, an inverter and a reset circuit, the CK terminal of the first latch is connected to the ESD pulse signal, the D terminal thereof is connected to a high level, and the RN terminal thereof is connected to the reset circuit, for sampling the rising edge of the ESD pulse signal and latching it as 1; the CK terminal of the second latch is connected to the ESD pulse signal through the inverter, the D terminal thereof is connected to a high level, and the RN terminal thereof is connected to the reset circuit, for sampling the rising edge of the ESD pulse signal after inversion and latching it as 1; the reset circuit adopts a multi-bit redundant control method to realize multi-mode reset logic control, for latching the first latch and the second latch as 0 after the ESD event ends.
[0100] Specifically, the reset circuit multi-bit register, multi-bit comparator, first multi-bit counter and second multi-bit counter described in this embodiment are shown in FIG. Figure 5 The multi-bit register is used to set the software configuration value of the bit to the first input terminal of the multi-bit comparator, and the second input terminal of the multi-bit comparator inputs a multi-bit constant for comparing the software configuration value with the multi-bit constant and outputting a comparison signal; the first multi-bit counter is used for delay control of ESD events to ensure that the system is in a normal control state; the second multi-bit counter is used to control the pulse width of the generated system hot reset.
[0101] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.
Claims
1. A self-recovery method for a chip ESD protection system, characterized in that: include: S1: Detect and determine whether the chip generates electrostatic interference. If so, connect the ESD discharge path to discharge electrostatics and output an electrostatic voltage detection signal simultaneously; if not, continue to perform electrostatic detection; S2: converting the level of the electrostatic voltage detection signal and outputting an ESD pulse signal; S3: input the ESD pulse signal as a clock signal into a latch, and perform edge sampling on the ESD pulse signal. If a high-level signal is collected, it is recorded as an ESD event occurrence signal; S4: Invert the ESD pulse signal and perform edge sampling again. If a high-level signal is collected, it is recorded as an ESD event end signal; S5: inputting an asynchronous reset signal, and using a multi-bit redundant control method to perform logic control on a reset level signal inputted to the reset end of the latch; S6: The latch outputs a self-recovery signal according to the reset level signal to achieve a self-recovery response of the chip system.
2. The self-recovery method of the chip ESD protection system according to claim 1, characterized in that: Step S5 also includes: S51: obtaining a crystal oscillator clock signal through an external crystal oscillator, and inputting the crystal oscillator clock signal as a clock signal source into a multi-bit register and an asynchronous reset synchronous evacuation circuit; S52: configuring a software configuration value of the multi-bit register, locking the software configuration value in the multi-bit register, and setting a multi-bit constant; S53: The asynchronous reset synchronous evacuation circuit processes the asynchronous reset signal and outputs an asynchronous reset synchronous evacuation signal.
3. The self-recovery method of the chip ESD protection system according to claim 2, characterized in that: Step S5 also includes: S54: performing a logical judgment on whether the software configuration is equal to the multi-bit constant, and when the software configuration is equal to the multi-bit constant, the reset level signal is output as a valid reset level signal; S55: Performing a logic judgment on whether the asynchronous reset synchronous withdrawal signal is a valid reset signal. When the asynchronous reset synchronous withdrawal signal is a valid reset signal, the reset level signal is output as a valid reset level signal.
4. The self-recovery method of the chip ESD protection system according to claim 3, characterized in that: In the ESD event triggered reset mode, the logic control formula of the reset level signal input to the reset terminal of the latch is: Rn = RSTN_SYNC & ~(Q1[n-1:0] == value) Formula (1) Among them, RSTN_SYNC is the asynchronous reset synchronization withdrawal signal, Q1[n-1:0] is the software configuration value output by the multi-bit register in this mode, and value is the multi-bit constant.
5. The self-recovery method of the chip ESD protection system according to claim 2, characterized in that: Step S5 also includes: S56: setting a soft reset signal, and using two multi-bit counters to respectively determine whether the ESD complete elimination setting time and the reset setting time have been reached; S57: if the reset setting time is reached, the soft reset signal is set to 0, and at this time, the soft reset signal will set the ESD event occurrence signal and the ESD event end signal to 0; S58: Performing a logic judgment on whether the soft reset signal is a valid reset signal. When the soft reset signal is a valid reset signal, the reset level signal is output as a valid reset level signal.
6. The self-recovery method of the chip ESD protection system according to claim 5, characterized in that: Step S56 also includes: S56-1: When the ESD event occurrence signal is 1, the first multi-bit counter starts counting; S56-2: When the count value of the first multi-bit counter reaches the ESD complete elimination setting time, the soft reset signal is triggered to be 1, and the second multi-bit counter starts counting at the same time; S56-3: When the count value of the second multi-bit counter reaches the reset setting time, the count value of the second multi-bit counter is reset to 0.
7. The self-recovery method of the chip ESD protection system according to claim 5, characterized in that: In the soft reset mode, the logic control formula of the reset level signal input to the reset terminal of the latch is: Rn = RSTN_SYNC & ~(Q2[n-1:0] == value)&(~esd_wreset) Formula (2) Among them, RSTN_SYNC is the asynchronous reset synchronization withdrawal signal, Q2[n-1:0] is the software configuration value output by the multi-bit register in this mode, value is the multi-bit constant, and esd_wreset is the soft reset signal.
8. The self-recovery method of the chip ESD protection system according to any one of claims 1 to 7, characterized in that: Different bit values are set to correspond to the ESD event triggered reset mode and the soft reset mode respectively. By configuring the software configuration value of the corresponding bit value in the multi-bit register, different modes are selected to realize system self-recovery.
9. A self-recovery circuit of a chip ESD protection system, characterized in that: A self-recovery method for a chip ESD protection system according to claims 1 to 8 is applied, comprising: An ESD detection circuit, an ESD discharge circuit, a drive circuit, a level conversion circuit and a digital logic circuit, wherein the ESD detection circuit is used to detect the electrostatic voltage of the chip and output an electrostatic voltage detection signal to the ESD discharge circuit and the drive circuit respectively; the ESD discharge circuit is used to turn on or off the ESD discharge according to the electrostatic detection signal; the drive circuit drives the electrostatic voltage detection signal and outputs it to the level conversion circuit; the level conversion circuit is used to convert the electrostatic voltage detection signal into a level signal to generate an ESD pulse signal; and the digital logic circuit is used to perform system self-recovery logic control according to the ESD pulse signal.
10. The self-recovery circuit of the chip ESD protection system according to claim 9, characterized in that: The digital logic circuit includes a first latch, a second latch, an inverter and a reset circuit. The CK terminal of the first latch is connected to the ESD pulse signal, the D terminal is connected to a high level, and the RN terminal is connected to the reset circuit, so as to perform rising edge sampling on the ESD pulse signal and latch it as 1; the CK terminal of the second latch is connected to the ESD pulse signal through the inverter, the D terminal is connected to a high level, and the RN terminal is connected to the reset circuit, so as to perform rising edge sampling on the ESD pulse signal after inversion and latch it as 1; the reset circuit adopts a multi-bit redundant control method to realize multi-mode reset logic control, so as to make the first latch and the second latch latched as 0 after the ESD event ends.