Decoding Method of Resolver, Rotary Digital Converter and Storage Medium

Abstract

The present application discloses a decoding method for a resolver, a rotary digital converter, and a storage medium, relating to the technical field of motor control, including: receiving an input signal sent by the resolver, wherein the input signal is generated based on the excitation signal of the resolver; performing analog-to-digital conversion on the input signal according to the excitation signal to obtain a digital signal corresponding to the input signal; demodulating the digital signal according to the excitation signal to obtain an angle error signal, and decoding the angle error signal. The present application realizes the effect of simultaneously supporting the decoding of the input signal of the rotary digital converter with a high-frequency or low-frequency excitation frequency in a rotary digital converter architecture by adopting different analog-to-digital conversion methods and demodulation methods for the digital signal determined based on the excitation signal when the excitation frequency of the input signal is high frequency or low frequency.

Description

Technical Field

[0001] The present application relates to the technical field of motor control, and particularly to a decoding method for a resolver, a resolver-to-digital converter, and a storage medium. Background Art

[0002] Since a resolver (hereinafter referred to as a resolver) can still maintain high reliability and high precision in a harsh environment, it is widely used in fields such as aerospace, railway, automotive, and robotics. A resolver-to-digital converter (RDC) is an interface between a resolver and a system microprocessor, and is used to decode information such as the angular position and rotational speed of a motor shaft. The resolver uses an excitation signal to excite the primary winding, and two electromagnetic induction differential output signals, namely a sine input signal and a cosine input signal, will be generated on the secondary winding. The resolver-to-digital converter decodes these two differential output signals generated by the resolver to obtain information such as the rotational phase and rotational speed of the motor shaft.

[0003] In different application scenarios, the frequency of the excitation signal applied to the resolver will vary greatly. If a high-frequency excitation signal is applied to the resolver, the resolver-to-digital converter needs to support an RDC architecture for high-frequency excitation signals; if a low-frequency excitation signal is applied to the resolver, the resolver-to-digital converter needs to support an RDC architecture for low-frequency excitation signals. Since the RDC architecture for supporting high-frequency excitation signals and the RDC architecture for supporting low-frequency excitation signals are completely different, the current RDC can only decode resolvers using high-frequency excitation signals, or can only decode resolvers using low-frequency excitation signals. It is impossible to decode both resolvers using high-frequency excitation signals and resolvers using low-frequency excitation signals.

[0004] Therefore, how the resolver-to-digital converter can simultaneously support the decoding of resolvers with high-frequency excitation signals and resolvers with low-frequency excitation signals is an urgent problem to be solved at present. Summary of the Invention

[0005] The main purpose of the present application is to provide a decoding method for a resolver, a resolver-to-digital converter, and a storage medium, aiming to solve the technical problem of how the resolver-to-digital converter can simultaneously support the decoding of resolvers with high-frequency excitation signals and resolvers with low-frequency excitation signals.

[0006] To achieve the above object, the present application proposes a decoding method for a resolver, and the method includes:

[0007] Receiving an input signal sent by the resolver, where the input signal is generated based on the excitation signal of the resolver;

[0008] Perform analog-to-digital conversion on the input signal according to the excitation signal to obtain a digital signal corresponding to the input signal;

[0009] Demodulate the digital signal according to the excitation signal to obtain an angle error signal, and decode the angle error signal.

[0010] In one embodiment, the step of performing analog-to-digital conversion on the input signal according to the excitation signal to obtain a digital signal corresponding to the input signal includes:

[0011] When the excitation signal is a high-frequency excitation signal, perform analog-to-digital conversion on the input signal according to the excitation clock frequency of the high-frequency excitation signal to obtain a digital signal corresponding to the input signal;

[0012] When the excitation signal is a low-frequency excitation signal, perform analog-to-digital conversion on the input signal according to a preset low-frequency clock frequency to obtain a digital signal corresponding to the input signal, wherein the excitation clock frequency of the high-frequency excitation signal and the excitation clock frequency of the low-frequency excitation signal constitute the value range of the preset low-frequency clock frequency.

[0013] In one embodiment, the step of performing analog-to-digital conversion on the input signal according to the excitation clock frequency of the high-frequency excitation signal to obtain a digital signal corresponding to the input signal includes:

[0014] Determine the chopping clock frequency of a preset operational amplifier according to the excitation clock frequency of the high-frequency excitation signal, and perform down-conversion on the input signal through the preset operational amplifier at the chopping clock frequency to obtain an envelope signal corresponding to the input signal; determine the first sampling clock frequency of a preset delta-sigma modulator (DSM) according to a preset system clock frequency, and perform analog-to-digital conversion on the envelope signal through the DSM at the first sampling clock frequency to obtain a digital signal corresponding to the input signal; or

[0015] Determine the second sampling clock frequency of a preset analog-to-digital converter according to the excitation clock frequency of the high-frequency excitation signal, and perform analog-to-digital conversion on the input signal through the analog-to-digital converter at the second sampling clock frequency to obtain a digital signal corresponding to the input signal.

[0016] In one embodiment, the step of performing analog-to-digital conversion on the input signal according to a preset low-frequency clock frequency to obtain a digital signal corresponding to the input signal includes:

[0017] Use the preset system clock frequency as the preset low-frequency clock frequency; determine the third sampling clock frequency of the preset delta-sigma modulator (DSM) according to the preset low-frequency clock frequency, and perform analog-to-digital conversion on the input signal through the DSM at the third sampling clock frequency to obtain the digital signal corresponding to the input signal; or

[0018] Determine the fourth sampling clock frequency of the preset analog-to-digital converter according to the low-frequency clock frequency, and perform analog-to-digital conversion on the input signal through the analog-to-digital converter at the fourth sampling clock frequency to obtain the digital signal corresponding to the input signal.

[0019] In one embodiment, the decoding process of the angle error signal is performed in a tracking loop. The step of demodulating the digital signal according to the excitation signal to obtain the angle error signal includes:

[0020] Obtain the rotation phase signal decoded by the tracking loop at the previous moment;

[0021] Demodulate the digital signal according to the rotation phase signal and the excitation signal to obtain the angle error signal.

[0022] In one embodiment, the step of demodulating the digital signal according to the rotation phase signal and the excitation signal to obtain the angle error signal includes:

[0023] In the case where the excitation signal is a high-frequency excitation signal, demodulate the digital signal according to the rotation phase signal to obtain the angle error signal;

[0024] In the case where the excitation signal is a low-frequency excitation signal, demodulate the digital signal according to the low-frequency excitation signal and the rotation phase signal to obtain the angle error signal.

[0025] In one embodiment, the digital signal includes a sine digital signal and a cosine digital signal. The step of demodulating the digital signal according to the rotation phase signal to obtain the angle error signal includes:

[0026] Determine a first frequency synthesis signal and a second frequency synthesis signal according to the phase information of the rotation phase signal, and calculate the angle error signal based on the product of the first frequency synthesis signal and the sine digital signal, and the product of the second frequency synthesis signal and the cosine digital signal; or

[0027] Oscillate the rotation phase signal to obtain a rotation sine signal and a rotation cosine signal; calculate the angle error signal based on the product of the rotation cosine signal and the sine digital signal, and the product of the rotation sine signal and the cosine digital signal.

[0028] In one embodiment, the digital signals include a sine digital signal and a cosine digital signal. The step of demodulating the digital signals according to the low-frequency excitation signal and the rotation phase signal to obtain an angle error signal includes:

[0029] Determining a third frequency composite signal and a fourth frequency composite signal according to the phase information of the low-frequency excitation signal and the rotation phase signal, and calculating the angle error signal based on the product of the third frequency composite signal and the sine digital signal and the product of the fourth frequency composite signal and the cosine digital signal; or

[0030] Oscillating the rotation phase signal to obtain a rotation sine signal and a rotation cosine signal; calculating an initial angle error signal based on the product of the rotation cosine signal and the sine digital signal and the product of the rotation sine signal and the cosine digital signal; multiplying the low-frequency excitation signal by the initial angle error signal to obtain an angle error signal.

[0031] In addition, to achieve the above object, the present application also provides a rotary digital converter, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor. The computer program is configured to implement the steps of the resolver decoding method as described above.

[0032] In addition, to achieve the above object, the present application also provides a storage medium, which is a computer-readable storage medium. A computer program is stored on the storage medium, and when the computer program is executed by a processor, it implements the steps of the resolver decoding method as described above.

[0033] One or more technical solutions provided by the present application have at least the following technical effects:

[0034] The present application receives an input signal sent by a resolver, where the input signal is generated based on the excitation signal of the resolver to obtain a signal to be decoded from the resolver; performs analog-to-digital conversion on the input signal according to the excitation signal to obtain a digital signal corresponding to the input signal, so as to convert an analog signal of a high-frequency or low-frequency excitation frequency into a discrete digital signal by using different analog-to-digital conversion methods for the input signals generated under high-frequency or low-frequency excitation signals; demodulates the digital signal according to the excitation signal to obtain an angle error signal, and decodes the angle error signal, so as to use different demodulation methods determined based on the excitation signal frequency for the digital signals corresponding to high-frequency or low-frequency excitation signals, thereby restoring the original information of the resolver.

[0035] In summary, when the excitation frequency of the input signal is high frequency or low frequency, the present application adopts different analog-to-digital conversion methods and digital signal demodulation methods determined based on the excitation signal to achieve the effect of supporting the decoding of RDC input signals with high-frequency or low-frequency excitation frequencies in an RDC architecture simultaneously. Description of the Drawings

[0036] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application and, together with the specification, used to explain the principles of the present application.

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art.

[0038] Figure 1 It is a schematic flowchart provided for the first embodiment of the resolver decoding method of the present application;

[0039] Figure 2 It is a schematic diagram of the sampling scenario of the resolver decoding method provided for the first embodiment of the present application;

[0040] Figure 3 It is a schematic flowchart provided for the second embodiment of the resolver decoding method of the present application;

[0041] Figure 4 It is a schematic diagram of the system architecture of the resolver decoding method provided for the second embodiment of the present application;

[0042] Figure 5 It is a schematic diagram of the first embodiment of the input signal processing module of the resolver decoding method provided for the second embodiment of the present application;

[0043] Figure 6 It is a schematic diagram of the second embodiment of the input signal processing module of the resolver decoding method provided for the second embodiment of the present application;

[0044] Figure 7 It is a schematic diagram of the system architecture of the frequency synthesis method of the resolver decoding method provided for the second embodiment of the present application;

[0045] Figure 8 It is a schematic diagram of the system architecture of the traditional demodulation method of the resolver decoding method provided for the second embodiment of the present application;

[0046] Figure 9 It is a schematic diagram of the device structure of the hardware operating environment involved in the resolver decoding method in the embodiments of the present application.

[0047] Explanation of the reference numerals in the drawings of the embodiments:

[0048] Detailed implementation manners

[0049] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0050] For a better understanding of the technical solutions of the present application, the following will be described in detail in conjunction with the accompanying drawings of the specification and specific implementation manners.

[0051] The main solution of the embodiment of the present application is: receiving an input signal sent by a resolver, where the input signal is generated based on the excitation signal of the resolver; performing analog-to-digital conversion on the input signal according to the excitation signal to obtain a digital signal corresponding to the input signal; demodulating the digital signal according to the excitation signal to obtain an angle error signal, and decoding the angle error signal.

[0052] Since in different application scenarios, the frequencies of the excitation signals acting on the resolver will vary greatly. If the excitation signal acting on the resolver is a high-frequency excitation signal, the rotating digital converter needs to support the RDC architecture for high-frequency excitation signals; if the excitation signal acting on the resolver is a low-frequency excitation signal, the rotating digital converter needs to support the RDC architecture for low-frequency excitation signals. Since the RDC architecture for supporting high-frequency excitation signals and the RDC architecture for supporting low-frequency excitation signals are completely different, the current RDC can only decode resolvers using high-frequency excitation signals or only decode resolvers using low-frequency excitation signals. It is impossible to decode both resolvers using high-frequency excitation signals and resolvers using low-frequency excitation signals. Therefore, how the rotating digital converter can simultaneously support the decoding of resolvers with high-frequency excitation signals and resolvers with low-frequency excitation signals is an urgent problem to be solved at present.

[0053] The present application provides a solution. By adopting different analog-to-digital conversion methods and demodulation methods for digital signals determined based on the excitation signal when the excitation frequency of the input signal is high-frequency or low-frequency, the effect of simultaneously supporting the decoding of RDC input signals with high-frequency or low-frequency excitation frequencies in one RDC architecture is achieved.

[0054] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device, a rotating digital converter, etc. that can implement the above functions. Hereinafter, the rotating digital converter will be taken as an example to illustrate this embodiment and the following embodiments.

[0055] Based on this, the embodiment of the present application provides a resolver decoding method, referring to Figure 1 ,Figure 1 This is a schematic flowchart of the first embodiment of the resolver decoding method of the present application.

[0056] In this embodiment, the resolver decoding method includes steps S10 to S30:

[0057] Step S10: Receive the input signal sent by the resolver, where the input signal is generated based on the excitation signal of the resolver;

[0058] It should be noted that a resolver is a transformer that uses the principle of electromagnetic induction to change the voltage ratio by rotation. It consists of a primary winding and two secondary windings. One secondary winding is tightly coupled with the primary winding, and the other secondary winding is coupled with the primary winding through a rotating shaft. When the resolver rotates, the magnetic flux generated by the primary winding cuts the secondary winding, thereby generating an electromotive force in the secondary winding, that is, the input signal.

[0059] In addition, it should be noted that the input signal is an electromagnetic induction signal generated on the secondary winding of the resolver under the excitation of the excitation signal. By decoding this input signal, the rotation information of the motor shaft of the resolver can be obtained.

[0060] Exemplarily, the resolver uses a sinusoidal signal as the excitation signal to generate two electromagnetic induction input signals, namely the sine input signal and the cosine input signal , where is the input shaft angle of the resolver, is the excitation angle of the excitation signal, is the amplitude of the excitation signal, is the conversion ratio of the resolver. Receiving the input signal sent by the resolver means receiving the sine input signal and the cosine input signal .

[0061] Step S20: Perform analog-to-digital conversion on the input signal according to the excitation signal to obtain the digital signal corresponding to the input signal;

[0062] It can be understood that since the current RDC can only perform analog-to-digital conversion on resolvers using high-frequency excitation signals or only on resolvers using low-frequency excitation signals, and cannot perform analog-to-digital conversion on both resolvers using high-frequency excitation signals and resolvers using low-frequency excitation signals at the same time, step S20 is carried out. By performing specific analog-to-digital conversion on the input signal of the resolver according to the excitation signal in the resolver, it is possible to simultaneously support avoiding the distortion and interference problems that may occur during the transmission and processing of high-frequency or low-frequency analog signals, thereby simultaneously improving the versatility, accuracy, and stability of high-frequency or low-frequency signal processing, creating reliable conditions for accurately decoding the rotation phase and rotation speed information of the motor shaft.

[0063] Exemplarily, the ADC (Analog to Digital Converter) built in the RDC samples and quantifies these analog input signals according to the frequency and phase of the excitation signal. The ADC converts the continuous analog signal into a discrete digital signal, usually through components such as a sample-and-hold circuit, an analog comparator, and a digital encoder. Finally, a digital signal corresponding to the original input signal is obtained.

[0064] In a feasible implementation manner, step S20 may include steps S21 to S22:

[0065] Step S21, when the excitation signal is a high-frequency excitation signal, perform analog-to-digital conversion on the input signal according to the excitation clock frequency of the high-frequency excitation signal to obtain a digital signal corresponding to the input signal;

[0066] It should be noted that a high-frequency excitation signal usually refers to an excitation signal with an excitation clock frequency above the MHz level.

[0067] It can be understood that since a high-frequency excitation signal can provide higher resolution and more accurate angle measurement, performing step S21 can avoid problems such as information loss or inaccurate angle measurement caused by insufficient sampling frequency. By using the excitation clock frequency of the high-frequency excitation signal for analog-to-digital conversion, the resolution and measurement accuracy of the system are improved, ensuring that the position information of the motor shaft can be accurately obtained even under high-speed rotation conditions.

[0068] Exemplarily, first, it is recognized that the excitation signal is a high-frequency excitation signal. Then, the ADC in the RDC is configured to operate at the excitation clock frequency of the high-frequency excitation signal. The ADC synchronously samples the sine and cosine analog signals generated by the secondary winding of the resolver to ensure that the sampling rate is the excitation clock frequency of the high-frequency excitation signal. In this way, the ADC converts the analog signals into digital signals, which are subsequently used to calculate the precise angular position of the motor. During specific implementation, it may involve setting the sampling clock source of the ADC to the clock of the high-frequency excitation signal and ensuring that the sampling window of the ADC is synchronized with the excitation signal period.

[0069] Step S22, when the excitation signal is a low-frequency excitation signal, perform analog-to-digital conversion on the input signal according to a preset low-frequency clock frequency to obtain the digital signal corresponding to the input signal, where the excitation clock frequency of the high-frequency excitation signal and the excitation clock frequency of the low-frequency excitation signal constitute the value range of the preset low-frequency clock frequency.

[0070] It should be noted that the low-frequency excitation signal generally refers to an excitation signal with an excitation clock frequency below the KHz level; the low-frequency clock frequency can be n times the excitation clock frequency of the low-frequency excitation signal, which can satisfy the Nyquist frequency.

[0071] It can be understood that since the low-frequency excitation signal may be more applicable in specific application scenarios, such as when the motor speed is low or there are strict power consumption restrictions, performing step S22 can avoid the problem of unnecessary power consumption and resource waste caused by using too high a sampling frequency under low-frequency operating conditions. By performing analog-to-digital conversion using the preset low-frequency clock frequency, while ensuring sufficient measurement accuracy, it reduces the power consumption and cost of the system and improves the overall efficiency of the system.

[0072] Exemplarily, first, it is recognized that the excitation signal is a low-frequency excitation signal, and accordingly, the sampling frequency of the ADC is adjusted. The preset low-frequency clock frequency is selected to be between the excitation clock frequencies of the high-frequency and low-frequency excitation signals to ensure a sufficient sampling rate to avoid aliasing while reducing unnecessary sampling, thereby reducing power consumption. Specifically, the microprocessor or dedicated clock management unit in the RDC configures the sampling clock of the ADC to operate at the preset low-frequency clock frequency. The ADC samples and converts the input signal of the resolver at this new sampling frequency to generate a digital signal. This method allows the system to maintain effective signal processing when the motor speed is low, while optimizing the energy efficiency and resource utilization of the system.

[0073] In this embodiment, by dynamically performing analog-to-digital conversion according to the frequency of the excitation signal, that is, dynamically adjusting the sampling frequency of the analog-to-digital converter, problems caused by insufficient signal sampling or oversampling at different excitation frequencies are avoided, such as signal distortion, resource waste, and increased power consumption. The effects of maintaining high precision in signal processing and high efficiency of the system under different working conditions are achieved, ensuring that the rotary digital converter can accurately and efficiently obtain the position information of the motor shaft under high-frequency and low-frequency excitation signals.

[0074] Step S30: Demodulate the digital signal according to the excitation signal to obtain an angle error signal, and decode the angle error signal.

[0075] It should be noted that the angle error signal refers to the error signal corresponding to the phase difference between the input shaft angle and the RDC output shaft angle, including high-frequency components and low-frequency components. The high-frequency components will be filtered out in the subsequent second-order tracking loop, and finally information such as the angular position and rotational speed is decoded.

[0076] It can be understood that since the current RDC can only perform digital demodulation on resolvers using high-frequency excitation signals or only on resolvers using low-frequency excitation signals, and cannot perform digital demodulation on both resolvers using high-frequency excitation signals and resolvers using low-frequency excitation signals, step S30 is performed. By performing a specific demodulation method on the input digital signal of the resolver according to the excitation signal in the resolver, the problem of position tracking error caused by the inability to accurately demodulate the signal during the demodulation of high-frequency or low-frequency digital signals can be avoided, improving the decoding versatility and accuracy of the RDC for the output signal of the resolver, and ensuring the precise control of the motor shaft position.

[0077] Exemplarily, the rotary digital converter can use a DSP (Digital Signal Processor) to perform the demodulation operation. The demodulation process involves comparing the digitized sine and cosine signals with a reference signal (usually the sine and cosine waveforms of the same frequency as the rotor signal). This process can be achieved through a digital mixer and an adder. The digital mixer multiplies the input digital signal by the reference signal to generate two mixed signals. Then, the adder subtracts these two signals to obtain the angle error signal. The angle error signal includes high-frequency components and low-frequency components. Finally, the angle decoding algorithm processes the angle error signal, and the high-frequency components in the angle error signal are filtered out at this stage, and the precise angular position of the motor shaft is finally calculated. This process may include algorithms such as a phase-locked loop or a quadrature demodulator to ensure the accuracy and stability of the angle information. In this way, the rotary digital converter can achieve precise decoding and control of the motor shaft position.

[0078] In a feasible implementation, the decoding process of the angle error signal is performed in a tracking loop. The step of demodulating the digital signal according to the excitation signal in step S30 to obtain the angle error signal may include steps S31 to S32:

[0079] Step S31, obtaining the rotation phase signal decoded by the tracking loop at the previous moment;

[0080] It should be noted that the tracking loop refers to a closed-loop control system used to track and lock the phase of the resolver output signal, usually composed of a phase-locked loop or a similar algorithm; the rotation phase signal refers to the phase information of the motor shaft obtained after decoding the input signal sent by the resolver.

[0081] It can be understood that since it is necessary to continuously track the position change of the motor shaft, performing step S31 can avoid problems such as loss of position information or error accumulation caused by the inability to continuously track the phase change, thereby ensuring the continuity and accuracy of the motor shaft position and providing a reliable phase reference for subsequent control algorithms.

[0082] Exemplarily, the system first decodes the digital signal of the resolver through a Type-II tracking loop to obtain the real-time phase information of the motor shaft. This process involves calculating the rotation phase signal from the digital signal of the resolver through a digital signal processing algorithm. Then, the system stores or buffers this rotation phase signal so that at the beginning of the next sampling period, it can be used as the rotation phase signal of the "previous moment". Specifically, this may involve storing the decoded phase value in a register or memory for subsequent processing.

[0083] Step S32, demodulating the digital signal according to the rotation phase signal and the excitation signal to obtain the angle error signal.

[0084] It can be understood that in order to extract the accurate resolver motor shaft angle information from the digital signal, performing step S31 can avoid problems such as angle measurement errors caused by inaccurate demodulation of digital signals at different excitation frequencies. By comparing the actually decoded rotation phase signal with the current digital signal, an accurate angle error signal is generated, thereby improving the accuracy and response speed of the motor shaft position control.

[0085] Exemplarily, the system utilizes the acquired rotation phase signal and the current excitation signal to demodulate the digital signal after analog-to-digital conversion. The demodulation process typically includes mixing the digital signal with the excitation signal to generate a baseband signal containing angle information. Next, the angle error component in the baseband signal is extracted through a low-pass filter. This process may involve the use of quadrature demodulation techniques, where two orthogonal reference signals (usually sine and cosine signals generated from the excitation signal) are multiplied with the input signal, and then the angle error signal is separated through a filter bank. Finally, the system calculates an accurate angle error signal by comparing the current rotation phase signal with the angle information obtained after demodulation, which is used for feedback control or position correction.

[0086] In this embodiment, by adopting the methods of phase tracking and targeted demodulation, the problems of position measurement error and system instability caused by the inability to accurately track digital signals at different excitation frequencies due to signal phase changes are avoided, and the effect of continuously and accurately obtaining the position information of the motor shaft is achieved, thereby improving the performance and reliability of the RDC under dynamic working conditions.

[0087] This embodiment provides a resolver decoding method, which realizes the effect of decoding the RDC input signal with high-frequency or low-frequency excitation frequencies in an RDC architecture by adopting different analog-to-digital conversion methods and demodulation methods of digital signals determined based on the excitation signal when the excitation frequency of the input signal is high-frequency or low-frequency.

[0088] In a feasible embodiment, the step of performing analog-to-digital conversion on the input signal according to the excitation clock frequency of the high-frequency excitation signal to obtain the digital signal corresponding to the input signal in step S21 may include steps A211 to A212:

[0089] Step A211, determining the chopping clock frequency of a preset operational amplifier according to the excitation clock frequency of the high-frequency excitation signal, and down-converting the input signal through the preset operational amplifier at the chopping clock frequency to obtain the envelope signal corresponding to the input signal;

[0090] It should be noted that the chopping clock frequency refers to the clock frequency used to control the chopping stability of the operational amplifier, and this frequency determines the switching rate of the chopping switch inside the operational amplifier; the envelope signal refers to the signal whose amplitude changes with the envelope of the original input signal after down-conversion processing. This signal contains the amplitude information of the input signal but has a lower frequency, which is convenient for subsequent processing.

[0091] It can be understood that when the excitation signal is a high-frequency excitation signal, the frequency of the input signal is relatively high. Therefore, step A211 is performed. By configuring the chopping clock frequency of the operational amplifier based on the excitation clock frequency of the high-frequency excitation signal, the problems of hardware performance limitation or insufficient sampling rate caused by too high signal frequency can be avoided. Thus, the frequency of the input signal is reduced through down-conversion, the signal processing process is simplified, and the stability of signal processing is improved.

[0092] Exemplarily, the chopping clock frequency of the operational amplifier is set to the excitation clock frequency of the high-frequency excitation signal to ensure the stability of the down-conversion process. Next, the operational amplifier is configured in a chopping stable mode and, under the control of the chopping clock frequency, performs down-conversion processing on the input signal. This generally involves using switched-capacitor technology or an analog multiplier to multiply the input signal by a high-frequency chopping signal and extracting the envelope of the product signal through a low-pass filter, that is, the envelope signal of the input signal is obtained.

[0093] Step A212, determine the first sampling clock frequency of the preset delta-sigma modulator (DSM) according to the preset system clock frequency, and perform analog-to-digital conversion on the envelope signal through the DSM at the first sampling clock frequency to obtain the digital signal corresponding to the input signal.

[0094] It should be noted that the system clock refers to the clock used by the entire rotation converter system, and the system clock frequency may not be higher than the excitation clock frequency of the high-frequency excitation signal; the first sampling clock frequency refers to the sampling frequency used to control the DSM (Delta Sigma Modulator) to perform analog-to-digital conversion, and this frequency determines the sampling speed and resolution of the DSM.

[0095] It can be understood that since high-precision analog-to-digital conversion needs to be performed on the down-converted envelope signal, step A212 is performed. The problems of signal distortion or quantization error caused by mismatched sampling frequencies can be avoided. Through oversampling of the DSM based on the system clock frequency, the noise spectral density can be reduced, thereby improving the signal-to-noise ratio of the sine digital signal and cosine digital signal output by the DSM. At the same time, due to the noise shaping function of the DSM, the signal-to-noise ratio of the sine digital signal and cosine digital signal output by the DSM can be further improved. In addition, since the output of the DSM is a 1-bit digital code, the multiplier required for the multiplication operation in the subsequent demodulation process can be a 1-bit multiplied by an N-bit multiplier. Therefore, the multiplier is simple to implement and can be made very small in area, saving a great deal of hardware costs.

[0096] Exemplarily, the first sampling clock frequency of the DSM is set to a preset system clock frequency to ensure sufficient sampling rate and signal accuracy. Under the control of the first sampling clock frequency, the DSM samples and quantizes the envelope signal obtained after down-conversion. Specifically, the DSM converts the continuous envelope signal into a discrete digital signal through its internal analog-to-digital conversion mechanism. This process may include comparing the analog signal with a series of increasing reference voltages and recording the comparison results through a digital accumulator, ultimately obtaining an accurate digital representation of the input signal.

[0097] In this embodiment, by adopting chopper stabilization technology and the analog-to-digital conversion of the DSM, problems caused by direct current offset, temperature drift, and nonlinear distortion in analog signal processing are avoided, achieving the effect of accurately converting the analog input signal into a digital signal while maintaining high precision and a wide dynamic range. This method not only improves the stability and reliability of signal conversion but also optimizes the system's adaptability to high-frequency and low-frequency signals, ensuring high-quality digital signal output under different working conditions.

[0098] In another feasible embodiment, the step of performing analog-to-digital conversion on the input signal according to the excitation clock frequency of the high-frequency excitation signal in step 21 to obtain the digital signal corresponding to the input signal may further include step B211:

[0099] Step B211, determining the second sampling clock frequency of a preset analog-to-digital converter according to the excitation clock frequency of the high-frequency excitation signal, and performing analog-to-digital conversion on the input signal through the analog-to-digital converter at the second sampling clock frequency to obtain the digital signal corresponding to the input signal.

[0100] It should be noted that the second sampling clock frequency refers to the sampling frequency used to control the analog-to-digital converter (ADC) for analog-to-digital conversion. This frequency determines the sampling speed and resolution of the ADC and usually matches the frequency characteristics of the input signal.

[0101] It can be understood that since it is necessary to ensure that the ADC can convert the input signal at an appropriate sampling rate to avoid signal distortion or information loss caused by mismatched sampling rates, performing step B211 can avoid problems such as aliasing or quantization errors caused by inappropriate sampling frequencies, ensuring the accuracy and integrity of the input signal in the digital domain and providing high-quality data for subsequent digital signal processing.

[0102] Exemplarily, the excitation clock frequency of the high-frequency excitation signal is used as the second sampling clock frequency of the analog-to-digital converter to achieve the effect of spectrum shifting. Then, the system configures the ADC to use this second sampling clock frequency, and the ADC samples and converts the input signal of the resolver at this frequency. For example: sampling the continuous-time input signal with an impulse sequence, please refer to Figure 2 , Figure 2 In which, the x-axis of the two coordinate systems represents the signal frequency, and the y-axis represents the signal amplitude, and the following analysis can be made:

[0103]

[0104] Among them, is the sampled signal, is the original input signal, and the sampling time , is the sampling frequency, and the impulse signal can be expressed by the following formula:

[0105]

[0106] Among them, is the impulse function, so, can be rewritten as:

[0107]

[0108] Since the multiplication in the time domain is equal to the convolution in the frequency domain, for , the time domain where the signal is located is transformed into the frequency domain through Fourier transform, and we can get:

[0109]

[0110] Among them, is the frequency-domain signal obtained by Fourier transform of the original signal , and the image of this frequency-domain signal refers to Figure 2 in coordinate graph. Among them the Fourier transform of is:

[0111]

[0112] Among them, is the sampling frequency. Substitute into the formula of to get:

[0113]

[0114] Among them, is the sampled frequency-domain signal obtained by performing a Fourier transform on the sampled signal. The image of this sampled frequency-domain signal is referenced Figure 2 in the coordinate diagram, and this coordinate diagram represents sampling at integer multiples of .

[0115] In this embodiment, the only hardware expenses required are the sampling clock selection module and the analog-to-digital conversion module, and the sampling clock frequency of this analog-to-digital conversion module only needs to support the excitation clock frequency at most. It can be seen that the requirements for the sampling clock in this analog-to-digital conversion process are not high, it is very simple to implement, and it saves hardware expenses.

[0116] In a feasible embodiment, the step of performing analog-to-digital conversion on the input signal according to the preset low-frequency clock frequency to obtain the digital signal corresponding to the input signal in step S22 may include steps A221 to A222:

[0117] Step A221, taking the preset system clock frequency as the preset low-frequency clock frequency;

[0118] It can be understood that since a reliable clock source is required to synchronize and drive subsequent signal processing when the system operating frequency is reduced, performing step A221 can avoid system synchronization problems such as signal processing delays or errors caused by clock frequency mismatches, thereby ensuring that the system can maintain a stable clock reference at different operating frequencies, thereby improving the overall performance and reliability of the system.

[0119] Step A222, determining the third sampling clock frequency of the preset delta-sigma modulator (DSM) according to the preset low-frequency clock frequency, and performing analog-to-digital conversion on the input signal through the DSM at the third sampling clock frequency to obtain the digital signal corresponding to the input signal.

[0120] It should be noted that the third sampling clock frequency refers to the sampling frequency used to control the DSM to perform analog-to-digital conversion under low-frequency operation. This frequency is usually lower than or equal to the sampling clock frequency under the high-frequency excitation signal, but high enough to maintain the required signal resolution and accuracy.

[0121] It can be understood that under low-frequency operating conditions, since it is necessary to adjust the sampling frequency to adapt to the lower signal frequency while maintaining the accuracy of signal processing, performing step A222 can avoid problems such as resource waste caused by too high a sampling frequency or signal distortion caused by too low a sampling frequency. Thus, under low-frequency signal conditions, through DSM oversampling based on the system clock frequency, the noise spectral density can be reduced, thereby improving the signal-to-noise ratio of the sine digital signal and cosine digital signal output by the DSM. At the same time, due to the noise shaping function of the DSM, the signal-to-noise ratio of the sine digital signal and cosine digital signal output by the DSM can be further improved. In addition, since the DSM output is a 1-bit digital code, the multiplier required for the multiplication operation in the subsequent demodulation process can be a 1-bit multiplied by an N-bit multiplier. Therefore, the multiplier is simple to implement and can be made very small in area, saving a great deal of hardware costs.

[0122] Exemplarily, according to the already set low-frequency clock frequency, the third sampling clock frequency of the DSM is set through programming or hardware configuration. This frequency may be a multiple value of the low-frequency clock frequency to ensure compliance with the sampling theorem and adaptation to the characteristics of the low-frequency signal. Next, under the control of the third sampling clock frequency, the DSM performs analog-to-digital conversion on the input signal. Specifically, the DSM uses its internal analog comparator and digital accumulator to quantify the amplitude of the input signal within each third sampling clock cycle and accumulate the quantization results, finally outputting a digital signal that faithfully reflects the amplitude information of the input signal. This process may also include digital filtering and calibration steps to improve the accuracy and stability of the conversion.

[0123] In this embodiment, through clock management and the analog-to-digital conversion of the DSM, problems such as signal processing synchronization issues caused by clock frequency mismatch and signal distortion or aliasing caused by inappropriate sampling frequency under low-frequency operating conditions are avoided, achieving the effect of maintaining high precision and high efficiency in signal processing at different operating frequencies. Specifically, by using the system clock frequency as the low-frequency clock frequency and setting the third sampling clock frequency of the DSM accordingly, it is ensured that under low-frequency signal conditions, the DSM can convert the input signal at the optimal sampling rate, thereby obtaining a high-quality digital signal output and enhancing the overall performance and reliability of the system.

[0124] In another feasible embodiment, the step of performing analog-to-digital conversion on the input signal according to the preset low-frequency clock frequency to obtain the digital signal corresponding to the input signal in step S22 may further include step B221:

[0125] Step B221: Determine the fourth sampling clock frequency of the preset analog-to-digital converter according to the low-frequency clock frequency, and perform analog-to-digital conversion on the input signal through the analog-to-digital converter at the fourth sampling clock frequency to obtain the digital signal corresponding to the input signal.

[0126] It should be noted that the fourth sampling clock frequency refers to the sampling frequency used to control the ADC in the low-frequency operating mode, and this frequency determines the sampling rate when the ADC converts an analog signal into a digital signal.

[0127] It can be understood that since it is necessary to ensure that the ADC can work at an appropriate sampling rate when processing low-frequency signals to maintain the accuracy and effectiveness of signal conversion, performing Step B221 can avoid problems such as signal distortion, aliasing, or quantization errors caused by inappropriate sampling frequencies. Thus, under low-frequency signal conditions, efficient analog-to-digital conversion is achieved through simple and fast analog-to-digital conversion.

[0128] In this embodiment, the only hardware expenses required are the sampling clock selection module and the analog-to-digital conversion module, and the sampling clock frequency of this analog-to-digital conversion module only needs to support the excitation clock frequency at most. It can be seen that the requirements for the sampling clock in this analog-to-digital conversion process are not high, it is very simple to implement, and it saves hardware expenses.

[0129] Based on the first embodiment of the present application, in the second embodiment of the present application, for the same or similar content as in the above-mentioned first embodiment, reference can be made to the above introduction and will not be repeated hereinafter. On this basis, please refer to Figure 3 , Step S32 may further include Steps S321 to S322:

[0130] Step S321: When the excitation signal is a high-frequency excitation signal, demodulate the digital signal according to the rotation phase signal to obtain an angle error signal;

[0131] It can be understood that since in the high-frequency operating mode, the excitation phase signal corresponding to the high-frequency excitation signal is equal to a constant phase, such as π / 2, the relevant information of this high-frequency excitation signal will not be included in the final demodulation calculation result. Therefore, performing Step S321 can avoid problems such as inaccurate angle measurement or signal distortion caused by improper processing of high-frequency signals. Thus, under high-frequency operating conditions, the rotation angle information of the motor shaft can be accurately obtained, improving the control accuracy and response speed of the system.

[0132] Exemplarily, when the excitation signal is a high-frequency excitation signal, mix the digital signal with a reference quadrature signal (I / Q signal) generated based on the rotation phase signal, and then extract the angle error information through a low-pass filter to finally obtain an accurate angle error signal.

[0133] In a feasible implementation manner, the step of demodulating the digital signal according to the rotation phase signal in step S321 to obtain an angle error signal may include step A01:

[0134] Step A01: Determine a first frequency synthesis signal and a second frequency synthesis signal according to the phase information of the rotation phase signal, and calculate an angle error signal based on the product of the first frequency synthesis signal and the sine digital signal, and the product of the second frequency synthesis signal and the cosine digital signal.

[0135] It should be noted that the first frequency synthesis signal refers to a reference frequency signal corresponding to the sine output signal of the resolver. This signal is usually a digital signal synchronized with the rotation phase signal and is used for multiplication with the sine digital signal to extract information related to the motor shaft position; the second frequency synthesis signal refers to a reference frequency signal corresponding to the cosine output signal of the resolver, which is also a digital signal synchronized with the rotation phase signal and is used for multiplication with the cosine digital signal to extract another part of the information related to the motor shaft position.

[0136] It can be understood that in order to generate a reference signal synchronized with the resolver output signal through frequency synthesis technology to accurately calculate the absolute position of the motor shaft, step A01 is performed, which can avoid angle calculation errors caused by the asynchronous reference signal and actual signal, as well as system instability problems caused by improper signal processing. Thus, it improves the measurement accuracy of the system for the motor shaft position. Even in the presence of noise or signal distortion, it can maintain a highly reliable angle error signal calculation, enhancing the overall performance and robustness of the RDC.

[0137] Exemplarily, perform an addition operation and a subtraction operation on the excitation phase signal and the rotation phase signal to generate a first angle signal and a second angle signal. Among them, the first angle signal ANGLE1 and the second angle signal ANGLE2 can be respectively expressed as:

[0138]

[0139]

[0140] After that, send the first angle signal and the second angle signal to an oscillator to generate a first sine signal, a second sine signal, a first cosine signal, and a second cosine signal through the oscillator. Among them, the first sine signal SIN1, the second sine signal SIN2, the first cosine signal COS1, and the second cosine signal COS2 can be respectively expressed as:

[0141]

[0142]

[0143]

[0144]

[0145] Among them, the oscillator can be either an analog oscillator or a digital oscillator, and can also be implemented by the LUT look-up table method or the CORDIC method. The full name of LUT is Look-Up Table, that is, the look-up table method. The sine value and cosine value of a specific phase can be obtained through mapping; the CORDIC algorithm is an algorithm of "simplifying the complex", which transforms many complex operations into an iterative operation of "only requiring shift and addition". After that, adding and subtracting the first sine signal, the second sine signal, the first cosine signal and the second cosine signal can generate the third frequency synthesis signal and the fourth frequency synthesis signal. If the amplitudes of the third frequency synthesis signal and the fourth frequency synthesis signal are not normalized, the third frequency synthesis signal EXC3 and the fourth frequency synthesis signal EXC4 obtained at this time can be respectively expressed as:

[0146]

[0147]

[0148]

[0149]

[0150] Among them, the third frequency synthesis signal and the fourth frequency synthesis signal can be normalized here; or they can be normalized in the subsequent process, such as during demodulation; or the third frequency synthesis signal and the fourth frequency synthesis signal can not be normalized. If the excitation signal is a high-frequency excitation signal, that is, in the high-frequency mode, the excitation phase signal at this time is equal to a constant phase, and the constant phase can be set to π / 2. Therefore, in the high-frequency mode, the generated first frequency synthesis signal EXC1_HP and the second frequency synthesis signal EXC2_HP can be respectively expressed as:

[0151]

[0152]

[0153]

[0154]

[0155] It can be seen that in the high-frequency mode, the generated first frequency composite signal EXC1_HP and second frequency composite signal EXC2_HP only contain information related to the rotation phase. Then, the amplitudes of the sine digital signal SIND and cosine digital signal COSD are normalized, and at this time, we get:

[0156]

[0157]

[0158] If in the high-frequency mode, the sine digital signal SIND_HP and cosine digital signal COSD_HP generated by the input signal processing module have already completed the operation of down-converting the excitation signal, and at this time, we get:

[0159]

[0160]

[0161] Then, through multiplication, the sine digital signal SIND_HP can be multiplied by the first frequency composite signal EXC1_HP to obtain the sine down-converted signal SINDD_HP, and the cosine digital signal COSD_HP can be multiplied by the second frequency composite signal EXC2_HP to obtain the cosine down-converted signal COSDD_HP. This process can be expressed as:

[0162]

[0163]

[0164]

[0165]

[0166] After that, subtraction is performed on the sine down-converted signal and the cosine down-converted signal to obtain the angle error signal . This process can be expressed as:

[0167]

[0168]

[0169]

[0170] In this embodiment, by performing demodulation based on the frequency synthesis method, the problem of inaccurate angle calculation caused by signal phase deviation or frequency offset is avoided, and the calculation of the angle error signal with high precision and high stability is realized in a complex electromagnetic environment, thereby improving the dynamic response speed and position control accuracy of the RDC.

[0171] In another feasible implementation, the step of demodulating the digital signal according to the rotation phase signal in step S321 to obtain an angle error signal may further include steps B01 to B02:

[0172] Step B01: Oscillate the rotation phase signal to obtain a rotating sine signal and a rotating cosine signal;

[0173] Exemplarily, the rotation phase signal generates a rotating sine signal through an oscillation module and a rotating cosine signal .

[0174] Step B02: Calculate the angle error signal based on the product of the rotating cosine signal and the sine digital signal, and the product of the rotating sine signal and the cosine digital signal.

[0175] Exemplarily, perform a multiplication operation on the rotating cosine signal and the sine digital signal to obtain a sine rotating down-converted signal; perform a multiplication operation on the cosine digital signal and the rotating sine signal to obtain a cosine rotating down-converted signal. Then, perform a subtraction operation on the sine rotating down-converted signal and the cosine rotating down-converted signal to obtain the angle error signal.

[0176] In this implementation, by adapting this RDC architecture to the traditional orthogonal oscillation and demodulation methods, the problems of angle calculation errors and system instability caused by non-orthogonal signals or phase mismatches are avoided, and the effect of accurately calculating the angle error signal in the RDC is achieved, thereby improving the accuracy of position detection and the system's ability to track the position of the motor shaft.

[0177] Step S322: When the excitation signal is a low-frequency excitation signal, demodulate the digital signal according to the low-frequency excitation signal and the rotation phase signal to obtain an angle error signal.

[0178] It can be understood that since, under a low-frequency excitation signal, the demodulation process needs to consider both the frequency characteristics of the excitation signal and the rotation phase signal to adapt to the characteristics of low-frequency signals, performing step S322 can avoid problems such as demodulation failure, signal noise sensitivity, or increased angle error caused by inappropriate processing of low-frequency signals. Thus, under low-frequency operating conditions, the accuracy of the angle error signal is ensured through precise demodulation, and further, the stability and reliability of the system in low-speed or low-power modes are ensured.

[0179] Exemplarily, the digital signal is processed by a digital demodulation algorithm (such as a demodulation method based on the arctangent function). This process involves comparing the digital signal with a reference signal generated by a low-frequency excitation signal, and calculating the angle error through an algorithm, so as to obtain an accurate angle error signal under low-frequency operating conditions.

[0180] In a feasible implementation manner, the step of demodulating the digital signal according to the low-frequency excitation signal and the rotation phase signal in step S322 to obtain an angle error signal may include step A11:

[0181] Step A11, determining a third frequency synthesis signal and a fourth frequency synthesis signal according to the phase information of the low-frequency excitation signal and the rotation phase signal, and calculating an angle error signal based on the product of the third frequency synthesis signal and the sine digital signal, and the product of the fourth frequency synthesis signal and the cosine digital signal.

[0182] It should be noted that the third frequency synthesis signal refers to the result of multiplying the cosine form of the phase information of the rotation phase signal by the excitation signal; the fourth frequency synthesis signal refers to the result of multiplying the sine form of the phase information of the rotation phase signal by the excitation signal.

[0183] Exemplarily, the calculation process of the frequency synthesis signal in the specific embodiment of this step may refer to step A01, which will not be elaborated here. In the low-frequency mode, multiplying the sine digital signal SIND by the third frequency synthesis signal EXC3 to obtain a sine down-converted signal SINDD, and multiplying the cosine digital signal COSD by the fourth frequency synthesis signal EXC4 to obtain a cosine down-converted signal COSDD. This process can be expressed as:

[0184]

[0185]

[0186]

[0187]

[0188] After that, performing a subtraction operation on the sine down-converted signal and the cosine down-converted signal can obtain the angle error signal. This process can be expressed as:

[0189]

[0190]

[0191]

[0192] Compared with the angular error signal AE_HP in the high-frequency mode, the angular error signal AE has more high-frequency components. However, through the subsequent Type-II tracking loop, the high-frequency components can be suppressed. Therefore, whether in the high-frequency mode or the low-frequency mode, if the input shaft angle θ is the same, the finally decoded angular position and rotational speed are the same.

[0193] In this embodiment, by performing demodulation based on the frequency synthesis method, the problem of inaccurate angle calculation caused by signal phase deviation or frequency offset is avoided, and the calculation of the angular error signal with high precision and high stability is realized in a complex electromagnetic environment, thereby improving the dynamic response speed and position control accuracy of the RDC.

[0194] In another feasible embodiment, the step of demodulating the digital signal according to the low-frequency excitation signal and the rotation phase signal to obtain the angular error signal in step S322 may further include steps B11 to B13:

[0195] Step B11: Oscillate the rotation phase signal to obtain a rotation sine signal and a rotation cosine signal;

[0196] Step B12: Calculate an initial angular error signal based on the product of the rotation cosine signal and the sine digital signal, and the product of the rotation sine signal and the cosine digital signal;

[0197] Exemplarily, perform a multiplication operation on the rotation cosine signal and the sine digital signal to obtain a sine rotation down-converted signal; perform a multiplication operation on the cosine digital signal and the rotation sine signal to obtain a cosine rotation down-converted signal. Then, perform a subtraction operation on the sine rotation down-converted signal and the cosine rotation down-converted signal to obtain the initial angular error signal.

[0198] Step B13: Multiply the low-frequency excitation signal by the initial angular error signal to obtain the angular error signal.

[0199] It can be understood that since it is necessary to modulate the initial angular error signal through a multiplication operation under the condition of the low-frequency excitation signal in order to extract the angular information corresponding to the actual position of the motor shaft, performing step B13 can avoid problems such as signal distortion, noise interference, or phase deviation that may occur when directly processing the initial angular error signal, ensuring the accuracy and stability of the angular error signal in a low-frequency working environment.

[0200] In this embodiment, under the condition of a low-frequency excitation signal, the rotation phase signal is accurately demodulated, the initial angle error signal is calculated, and it is multiplied by the low-frequency excitation signal to finally obtain an accurate angle error signal, achieving the effect of improving the angle measurement accuracy and system stability in a low-frequency working environment, and ensuring that the RDC can still maintain high-precision position control under low-frequency working conditions.

[0201] In this embodiment, by performing adaptive demodulation on the excitation signal frequency, problems such as phase shift, signal distortion, and slow system response that may occur during the signal demodulation process at different excitation frequencies are avoided. When the excitation signal frequency changes, whether it is high frequency or low frequency, the digital signal can be accurately demodulated to obtain a reliable angle error signal, ensuring the stable operation and efficient decoding of the RDC within a wide frequency range.

[0202] Exemplarily, to help understand the implementation process of the resolver decoding method obtained by combining the above-mentioned Embodiment 1 and Embodiment 2 in this embodiment, please refer to Figure 4 , Figure 4 A schematic diagram of the system architecture of a resolver decoding method is provided. Specifically:

[0203] Figure 4 This is the basic architecture of the present application, mainly composed of five parts: an input signal processing module 1, an excitation phase selection module 2, a frequency synthesis module 3, a demodulation module 4, and a Type-II tracking loop 5.

[0204] Among them, the input signal processing module 1 is used to convert the two electromagnetic induction differential output signals of the resolver, that is, the sine input signal and the cosine input signal of the RDC architecture of the present invention, from analog signals to digital signals. The excitation phase selection module 2 is used to select the corresponding excitation phase in the high-frequency or low-frequency mode. The frequency synthesis module 3, according to the input excitation phase signal and rotation phase signal, through a series of operations, finally obtains a first frequency synthesis signal and a second frequency synthesis signal (the frequency synthesis signal is the frequency synthesis signal). The demodulation module 4 multiplies the sine digital signal and the cosine digital signal output by the input signal processing module by the first frequency synthesis signal and the second frequency synthesis signal output by the frequency synthesis module respectively, so that the sine digital signal and the cosine digital signal achieve excitation down-conversion and rotation down-conversion, obtaining a sine down-conversion signal and a cosine down-conversion signal. By performing a subtraction operation on the sine down-conversion signal and the cosine down-conversion signal, an angle error signal can be obtained. The Type-II tracking loop 5 converts the angle error signal into an angular position and a rotation speed, that is, a rotation phase signal and a rotation speed signal.

[0205] Further, please refer to Figure 5 and Figure 6 , Figure 5For the first embodiment of the input signal processing module 1, Figure 6 For the second embodiment of the input signal processing module 1. Figure 5 It mainly consists of two parts, a sampling clock selection module 11 and a first analog-to-digital conversion module 12. Among them, the sampling clock selection module 11 is used to select the sampling clock signal corresponding to the first analog-to-digital conversion module in the high-frequency or low-frequency mode. The sampling clock selection module 11 controls the gating of its switch through the high-low frequency mode signal. When in the high-frequency mode, the sampling clock signal is equal to the excitation clock. At this time, through the spectral shift of the sampling operation, the purpose of excitation down-conversion can be achieved. The obtained sine digital signal and cosine digital signal have achieved excitation down-conversion. Therefore, the remaining useful information components are mainly rotor information; when in the low-frequency mode, the sampling clock signal is equal to the low-frequency clock. Since the excitation signal frequency in the low-frequency mode is low, the frequencies of the sine input signal and cosine input signal are low. Therefore, even if the sampling clock frequency is several times the excitation signal frequency, it is still the low-frequency clock. The sampling clock frequency at this time can meet the Nyquist frequency. That is, the sampling operation in the low-frequency mode does not achieve excitation down-conversion. Therefore, the obtained sine digital signal and cosine digital signal still contain excitation information components and rotor information components. The first analog-to-digital conversion module 12 is used to convert the analog signal into a digital signal, that is, to convert the sine input signal and cosine input signal in analog signal form into sine digital signal and cosine digital signal in digital signal form. The first analog-to-digital conversion module can be implemented by an ADC with Nyquist sampling characteristics, such as a SAR (Successive Approximation Register) ADC, which converts the analog signal into a digital signal by the successive approximation method. It should be noted that in the high-frequency mode, the sampling clock frequency of the SAR ADC needs to be equal to the excitation signal frequency; in the low-frequency mode, the sampling clock frequency of the SAR ADC is greater than or equal to the Nyquist frequency, and the Nyquist frequency at this time is twice the excitation signal frequency.

[0206] Figure 6 It mainly consists of three parts, an envelope extraction module 13, an input signal selection module 14, and a second analog-to-digital conversion module 15. Among them, the envelope extraction module 13 is mainly used to extract the rotor envelope information of the high-frequency sine input signal and cosine input signal in the high-frequency mode, which is equivalent to realizing the excitation down-conversion function. It can be implemented by an operational amplifier with a chopping function. As long as the chopping clock frequency is set to the excitation clock frequency, the excitation down-conversion function can be realized, and the rotor envelope information can be extracted. The frequency of the obtained rotor envelope information is the low-frequency rotor frequency.

[0207] The input signal selection module 14 is used to select the input signal of the second analog-to-digital conversion module. The input signal selection module controls the gating of its switch through the high and low frequency mode signals. When in the high frequency mode, the sine analog signal input to the second analog-to-digital conversion module is equal to the sine envelope signal, and the cosine analog signal is equal to the cosine envelope signal; when in the low frequency mode, the envelope extraction module 13 can be turned off. At this time, the sine analog signal input to the second analog-to-digital conversion module is equal to the sine input signal, and the cosine analog signal is equal to the cosine input signal. Thus, whether in the high frequency mode or the low frequency mode, the input signal of the second analog-to-digital conversion module is a signal with a relatively low frequency.

[0208] The second analog-to-digital conversion module 15 is used to convert analog signals into digital signals, that is, to convert the sine analog signal and cosine analog signal in analog signal form into sine digital signal and cosine digital signal in digital signal form. The second analog-to-digital conversion module can be implemented by a DSM, and the sampling clock of the second analog-to-digital conversion module can be equal to the system clock. Since the input signal frequency of the second analog-to-digital conversion module is low while the system clock frequency is high, its sampling process is oversampling, which can reduce the noise spectral density and improve the signal-to-noise ratio of the sine digital signal and cosine digital signal output by the DSM. If the second analog-to-digital conversion module is implemented by a DSM, due to the noise shaping function of the DSM, the signal-to-noise ratio of the sine digital signal and cosine digital signal output by the DSM can be further improved. In addition, since the output of the DSM is a 1-bit digital code, the multiplier required for the multiplication operation of the subsequent demodulation module can be a 1-bit multiplied by an N-bit multiplier. Therefore, the multiplier is simple to implement and can be made very small in area, saving a lot of hardware costs.

[0209] Furthermore, please refer to Figure 7 and Figure 8 , Figure 7 is a schematic diagram of the system architecture adapted to the frequency synthesis method, Figure 8 is a schematic diagram of the system architecture adapted to the traditional demodulation method. Figure 7 The sampling clock selection module 11 in the input signal processing module 1 of is mainly used to select the sampling clock signal corresponding to the first analog-to-digital conversion module 12 in the high frequency or low frequency mode. The sampling clock selection module 11 controls the gating of its switch through the high and low frequency mode signals. When in the high frequency mode, the sampling clock signal is equal to the excitation clock; when in the low frequency mode, the sampling clock signal is equal to the low frequency clock. The sine input signal and cosine input signal in analog signal form generated by the resolver are used as the input signals of the input signal processing module 1. Among them, the sine input signal is converted into a sine digital signal in digital signal form through the first analog-to-digital converter 121; the cosine input signal is converted into a cosine digital signal in digital signal form through the second analog-to-digital converter 122.

[0210] In addition, the excitation phase selection module 2 controls the gating of its switches through high and low frequency mode signals. When in the low frequency mode, the excitation phase signal is equal to the excitation input phase; when in the high frequency mode, the excitation phase signal is equal to a constant phase, and the constant phase can be set to π / 2 at this time, that is, the excitation phase signal is equal to 90 degrees at this time.

[0211] The excitation phase signal generated by the excitation phase selection module 2 and the rotation phase signal φ generated by the Type-II tracking loop 5 serve as the input signals of the three-frequency synthesis module. For the frequency synthesis module 3, through the first addition module 31, the excitation phase signal and the rotation phase signal are subjected to an addition operation by the first adder 311 to obtain a first angle signal; the excitation phase signal and the rotation phase signal are subjected to a subtraction operation by the second adder 312 to obtain a second angle signal. Then, through the first oscillation module 32, a first sine signal and a first cosine signal are generated from the first angle signal; a second sine signal and a second cosine signal are generated from the second angle signal. Then, through the second addition module 33, the first sine signal and the second sine signal are subjected to an addition operation by the third adder 331 to obtain a first frequency synthesis signal; the first cosine signal and the second cosine signal are subjected to an addition operation by the fourth adder 332 to obtain a second frequency synthesis signal.

[0212] Then, the first frequency synthesis signal and the second frequency synthesis signal generated by the frequency synthesis module 3, as well as the sine digital signal and the cosine digital signal generated by the input signal processing module 1, serve as the input signals of the demodulation module 4. Through the first multiplication module 41, the sine digital signal and the first frequency synthesis signal are subjected to a multiplication operation by the first multiplier 411 to obtain a sine down-converted signal; the cosine digital signal and the second frequency synthesis signal are subjected to a multiplication operation by the second multiplier 412 to obtain a cosine down-converted signal. Then, through the third addition module 42, the sine down-converted signal and the cosine down-converted signal are subjected to a subtraction operation by the fifth adder 421 to obtain an angle error signal. The angle error signal passes through the Type-II tracking loop 5, and then the rotation phase signal φ and the rotation speed signal can be decoded.

[0213] For Figure 8 the RDC architecture of the traditional demodulation method in the embodiment, a rotation sine signal is generated by the rotation phase signal through the second oscillation module 6 and a rotation cosine signal ; an excitation input signal is generated by the excitation input phase through the third oscillation module 7 . In addition, the excitation signal selection module 8 controls the gating of its switches through high and low frequency mode signals. When in the low frequency mode, the excitation signal is equal to the excitation input signal; when in the high frequency mode, the excitation signal is equal to a constant value, and the constant value can be set to 1 at this time.

[0214] For the input signal of the traditional demodulation module 9, it passes through the second multiplication module 91. Through the multiplication operation of the third multiplier 911 on the sine digital signal and the rotating cosine signal, a sine-rotating down-converted signal is obtained; through the multiplication operation of the fourth multiplier 912 on the cosine digital signal and the rotating sine signal, a cosine-rotating down-converted signal is obtained. Then, through the fourth addition module 92, through the subtraction operation of the sixth adder 921 on the sine-rotating down-converted signal and the cosine-rotating down-converted signal, an initial angle error signal is obtained. Then, through the third multiplication module 93, through the multiplication operation of the fifth multiplier 931 on the initial angle error signal and the excitation signal, an angle error signal is obtained. After the angle error signal passes through the Type-II tracking loop 5, the rotating phase signal φ and the rotating speed signal can be decoded.

[0215] The initial angle error signal AES in the low-frequency mode and the initial angle error signal AES_HP in the high-frequency mode can be respectively expressed as:

[0216]

[0217]

[0218] For the angle error signal AEC in the low-frequency mode and the angle error signal AEC_HP in the high-frequency mode, they can be respectively expressed as:

[0219]

[0220]

[0221]

[0222]

[0223]

[0224]

[0225] It can be seen from the above formula that in the RDC architecture of the traditional resolver demodulation method, the angle error signal and the angle error information obtained by the frequency synthesis method only differ in signal amplitude, but their essence is the same. In addition, since in the high-frequency mode, the excitation signal is equal to 1, the operation of multiplying the initial angle error signal by the excitation signal by the fifth multiplier 931 can be equivalent to the operation of directly passing through the initial angle error signal, that is, the angle error signal in the high-frequency mode is equal to the initial angle error signal.

[0226] It can be seen that the RDC architecture of the present application is suitable for not only the RDC architecture of the frequency synthesis method but also the RDC architecture of the traditional demodulation method. Both have the advantages of simple architecture, low hardware cost, low clock frequency requirement, power consumption saving, and high signal-to-noise ratio.

[0227] In addition, it should be noted that the two implementation manners of the input signal processing module in this embodiment respectively correspond to steps (A211 - A212, A221 - A222) and steps (B211, B221), and the two system architectures applicable to the frequency synthesis method and the traditional demodulation method in this embodiment respectively correspond to steps (A01, A11) and steps (B01 - B02, B11 - B13), and they can be combined with each other to obtain four technical solutions under combinations, namely combination 1 (A211 - A212, A221 - A222, A01, A11), combination 2 (A211 - A212, A221 - A222, B01 - B02, B11 - B13), combination 3 (B211, B221, A01, A11), and combination 4 (B211, B221, B01 - B02, B11 - B13). In this embodiment Figure 7 corresponds to combination 3, Figure 8 corresponds to combination 2. The implementation processes of the remaining two combinations can refer to the specific implementation processes in this application and will not be elaborated here.

[0228] The present application provides a rotary digital converter, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the resolver decoding method in the first embodiment above.

[0229] Next, refer to Figure 9 , which shows a schematic structural diagram of a rotary digital converter suitable for implementing the embodiments of the present application. As Figure 9As shown, the resolver-to-digital converter may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to a program stored in the read-only memory 1002 or a program loaded from the storage device 1003 into the random access memory 1004. In the random access memory 1004, various programs and data required for the operation of the resolver-to-digital converter are also stored. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are connected to each other through a bus 1005. The input / output interface 1006 is also connected to the bus. Generally, the following systems may be connected to the input / output interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the resolver-to-digital converter to communicate with other devices wirelessly or wiredly to exchange data.

[0230] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts may be implemented as computer software programs. In such an embodiment, the computer program may be downloaded and installed from a network through the communication device, or installed from the storage device 1003, or installed from the read-only memory 1002. When the computer program is executed by the processing device 1001, the above functions defined in the method of the embodiments disclosed in the present application are executed.

[0231] The resolver-to-digital converter provided in the present application adopts the resolver decoding method in the above embodiments, and can solve the technical problem of how the resolver-to-digital converter supports the decoding of resolvers with high-frequency excitation signals and resolvers with low-frequency excitation signals at the same time. Compared with the prior art, the beneficial effects of the resolver-to-digital converter provided in the present application are the same as those of the resolver decoding method provided in the above embodiments, and other technical features in the resolver-to-digital converter are the same as the features disclosed in the previous embodiment method, which will not be elaborated here.

[0232] The present application provides a computer-readable storage medium having computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the resolver decoding method in the above embodiments.

[0233] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above.

[0234] The above computer-readable storage medium carries one or more programs, which, when executed by the resolver-to-digital converter, cause the resolver-to-digital converter to: receive an input signal sent by a resolver, wherein the input signal is generated based on an excitation signal of the resolver; perform analog-to-digital conversion on the input signal according to the excitation signal to obtain a digital signal corresponding to the input signal; demodulate the digital signal according to the excitation signal to obtain an angle error signal, and decode the angle error signal.

[0235] The readable storage medium provided in this application is a computer-readable storage medium, and the computer-readable storage medium stores computer-readable program instructions (i.e., computer programs) for executing the above resolver decoding method, which can solve the technical problem of how a resolver-to-digital converter supports the decoding of resolvers with high-frequency excitation signals and resolvers with low-frequency excitation signals at the same time. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the resolver decoding method provided in the above embodiments, and will not be elaborated here.

Claims

1. A resolver decoding method, characterized in that, The method described includes: Receiving an input signal sent by a resolver, where the input signal is generated based on the excitation signal of the resolver; When the excitation signal is a high-frequency excitation signal, performing analog-to-digital conversion on the input signal according to the excitation clock frequency of the high-frequency excitation signal to obtain a digital signal corresponding to the input signal; When the excitation signal is a low-frequency excitation signal, performing analog-to-digital conversion on the input signal according to a preset low-frequency clock frequency to obtain a digital signal corresponding to the input signal, where the excitation clock frequency of the high-frequency excitation signal and the excitation clock frequency of the low-frequency excitation signal constitute the value range of the preset low-frequency clock frequency; Demodulating the digital signal according to the excitation signal to obtain an angle error signal, and decoding the angle error signal.

2. The resolver decoding method according to claim 1, characterized in that, The step of performing analog-to-digital conversion on the input signal according to the excitation clock frequency of the high-frequency excitation signal to obtain a digital signal corresponding to the input signal includes: Determining the chopping clock frequency of a preset operational amplifier according to the excitation clock frequency of the high-frequency excitation signal, and performing down-conversion on the input signal through the preset operational amplifier at the chopping clock frequency to obtain an envelope signal corresponding to the input signal; determining the first sampling clock frequency of a preset delta-sigma modulator (DSM) according to a preset system clock frequency, and performing analog-to-digital conversion on the envelope signal through the DSM at the first sampling clock frequency to obtain a digital signal corresponding to the input signal; or Determining the second sampling clock frequency of a preset analog-to-digital converter according to the excitation clock frequency of the high-frequency excitation signal, and performing analog-to-digital conversion on the input signal through the analog-to-digital converter at the second sampling clock frequency to obtain a digital signal corresponding to the input signal.

3. The resolver decoding method according to claim 1, wherein The step of performing analog-to-digital conversion on the input signal according to the preset low-frequency clock frequency to obtain a digital signal corresponding to the input signal includes: Taking the preset system clock frequency as the preset low-frequency clock frequency; determining the third sampling clock frequency of a preset delta-sigma modulator (DSM) according to the preset low-frequency clock frequency, and performing analog-to-digital conversion on the input signal through the DSM at the third sampling clock frequency to obtain a digital signal corresponding to the input signal; or Determining the fourth sampling clock frequency of a preset analog-to-digital converter according to the low-frequency clock frequency, and performing analog-to-digital conversion on the input signal through the analog-to-digital converter at the fourth sampling clock frequency to obtain a digital signal corresponding to the input signal.

4. The resolver decoding method according to claim 1, wherein The decoding process of the angle error signal is performed in a tracking loop. The step of demodulating the digital signal according to the excitation signal to obtain an angle error signal includes: Obtaining the rotation phase signal decoded by the tracking loop at the previous moment; Demodulating the digital signal according to the rotation phase signal and the excitation signal to obtain an angle error signal.

5. The resolver decoding method according to claim 4, characterized in that, The step of demodulating the digital signal according to the rotation phase signal and the excitation signal to obtain an angle error signal includes: When the excitation signal is a high-frequency excitation signal, demodulate the digital signal according to the rotation phase signal to obtain an angle error signal; When the excitation signal is a low-frequency excitation signal, demodulate the digital signal according to the low-frequency excitation signal and the rotation phase signal to obtain an angle error signal.

6. The resolver decoding method according to claim 5, wherein, The digital signal includes a sine digital signal and a cosine digital signal. The step of demodulating the digital signal according to the rotation phase signal to obtain an angle error signal includes: Determine a first frequency synthesis signal and a second frequency synthesis signal according to the phase information of the rotation phase signal, and calculate the angle error signal based on the product of the first frequency synthesis signal and the sine digital signal, and the product of the second frequency synthesis signal and the cosine digital signal; or Oscillate the rotation phase signal to obtain a rotation sine signal and a rotation cosine signal; calculate the angle error signal based on the product of the rotation cosine signal and the sine digital signal, and the product of the rotation sine signal and the cosine digital signal.

7. The resolver decoding method according to claim 5, wherein The digital signal includes a sine digital signal and a cosine digital signal. The step of demodulating the digital signal according to the low-frequency excitation signal and the rotation phase signal to obtain an angle error signal includes: Determine a third frequency synthesis signal and a fourth frequency synthesis signal according to the phase information of the low-frequency excitation signal and the rotation phase signal, and calculate the angle error signal based on the product of the third frequency synthesis signal and the sine digital signal, and the product of the fourth frequency synthesis signal and the cosine digital signal; or Oscillate the rotation phase signal to obtain a rotation sine signal and a rotation cosine signal; calculate an initial angle error signal based on the product of the rotation cosine signal and the sine digital signal, and the product of the rotation sine signal and the cosine digital signal; multiply the low-frequency excitation signal by the initial angle error signal to obtain an angle error signal.

8. A rotary digital converter, characterized in that, The rotary digital converter includes: a memory, a processor, and a computer program stored on the memory and executable on the processor. The computer program is configured to implement the steps of the resolver decoding method according to any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium. A computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the resolver decoding method according to any one of claims 1 to 7 are implemented.

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