PVT compensation ultra-low-voltage fully-differential OTA amplifier based on phase inverter

Abstract

The invention discloses a PVT compensation ultra-low-voltage fully-differential OTA amplifier based on an inverter. The PVT compensation ultra-low-voltage fully-differential OTA amplifier comprises an amplifying circuit based on the inverter and a PVT compensation substrate biasing circuit. The amplifying circuit based on the phase inverters comprises a differential input pair, a common-mode feedback amplifier, a variable current source controlled by the common-mode feedback amplifier, a first resistor and a second resistor, wherein the differential input pair is formed by CMOS phase inverters of which substrates of PMOS (P-channel Metal Oxide Semiconductor) transistors and NMOS (N-channel Metal Oxide Semiconductor) transistors are controlled by a biasing circuit; the PVT-compensated substrate biasing circuit comprises a starting circuit formed by MOS tubes, a reference current source which is formed by the MOS tubes and resistors and is in proportion to the temperature, and a circuit which is formed by the MOS tubes and outputs PMOS tube body bias voltage and NMOS tube body bias voltage at the same time. When the temperature or process parameters change, the gain and bandwidth of the amplifier can be stabilized, the amplifier can still work normally under ultra-low voltage, and the power consumption of the amplifier is remarkably reduced.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and more specifically relates to an inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier. Background Art

[0002] In recent years, due to the stringent requirements on power consumption in IoT sensor nodes, the design of extremely low power Sigma-Delta converters has become a research hotspot, and traditional converter structures are difficult to meet the requirements. Fortunately, in many applications of the IoT, the conversion speed requirement is not high, making it possible to realize extremely low power Sigma-Delta converters. The key to achieving low power consumption is to try to reduce the power consumption of the operational amplifier used in the integrator of the converter. Inverter-based amplifiers are currently a common choice, but inverter-based amplifiers are easily affected by process, voltage and temperature changes (PVT), which causes the inverter's operating point and gain, unit gain bandwidth and output swing to change significantly, greatly affecting the performance of the modulator. Therefore, based on the inverter-based amplifier, a PVT compensation strategy must be adopted to reduce the impact of PVT changes on gain and bandwidth. Summary of the invention

[0003] In view of the above problems, the present invention provides an inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier to achieve more reliable circuit performance under ultra-low voltage working conditions.

[0004] To achieve the above-mentioned object, the present invention provides an inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier, comprising an inverter-based amplifier circuit and a PVT compensated substrate bias circuit; the inverter-based amplifier circuit comprises a differential input pair composed of CMOS inverters whose substrates of PMOS and NMOS tubes are both controlled by a bias circuit, a common-mode feedback amplifier, a variable current source controlled by the common-mode feedback amplifier, and first and second resistors; the PVT compensated substrate bias circuit comprises a startup circuit composed of a MOS tube, a reference current source proportional to temperature composed of a MOS tube and a resistor, and a circuit composed of a MOS tube that simultaneously outputs a PMOS tube and an NMOS tube body bias voltage; the working state of the substrate bias circuit is:

[0005] When the temperature or process parameters change, the reference current source proportional to the temperature formed by the sixteenth to twenty-first MOS tubes and the third resistor generates a changing current, and the circuit output formed by the twenty-second and twenty-third MOS tubes and the twenty-fourth and twenty-fifth MOS tubes controls the body voltage of the PMOS tube and the NMOS tube of the amplifier circuit to offset the impact of the temperature or process parameter changes on the circuit and stabilize the circuit performance.

[0006] The inverter-based amplifier circuit includes first to twelfth MOS tubes and first and second resistors. The first and second MOS tubes and the seventh and eighth MOS tubes respectively constitute a pair of inverters and serve as differential inputs of the amplifier circuit at the same time. The third to sixth MOS tubes serve as current sources, and the ninth to twelfth MOS tubes constitute common-mode feedback amplifiers. The first, third, fifth, seventh, ninth and eleventh MOS tubes are PMOS tubes, and the second, fourth, sixth, eighth, tenth and twelfth MOS tubes are NMOS tubes.

[0007] The sources of the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, the seventh MOS tube M7, the ninth MOS tube M9 and the eleventh MOS tube M11 are all connected to the external power supply V DD The sources of the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, the eighth MOS tube M8, the tenth MOS tube M10 and the twelfth MOS tube M12 are all connected to the ground, and the gates of the first MOS tube M1 and the second MOS tube M2 are all connected to the differential input signal V in+ The drains of the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are connected together to form an output terminal V of the OTA amplifier. out- The drains of the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 are connected together to form another output terminal V of the OTA amplifier. out+ The gates of the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, and the sixth MOS tube M6 are connected together and connected to the drains of the eleventh MOS tube M11 and the twelfth MOS tube M12, and the gates of the seventh MOS tube M7 and the eighth MOS tube M8 are connected to the differential input signal V in- The body electrodes of the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, and the seventh MOS tube M7 are connected together and connected to the first output node V of the substrate bias circuit of the PVT compensation. bp The body electrodes of the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, and the eighth MOS tube M8 are connected together to the second output node V of the substrate bias circuit of the PVT compensation. bn The gates of the ninth MOS tube M9 and the eleventh MOS tube M11 are connected together and connected to the drains of the ninth MOS tube M9 and the tenth MOS tube M10. One end of the first resistor R1 and the second resistor R2 are connected to the output port V out- 、V out+ The other end is connected to the gate of the tenth MOS tube M10, and the gate of the twelfth MOS tube M12 is connected to the external reference voltage source V ref .

[0008] The substrate bias circuit for PVT compensation includes thirteenth to twenty-fifth MOS tubes, first to third capacitors and a third resistor, the thirteenth to fifteenth MOS tubes constitute a startup circuit, the sixteenth to twenty-first MOS tubes and the third resistor constitute a reference current source proportional to the temperature, the twenty-second and twenty-third MOS tubes constitute a first output node circuit, the twenty-fourth and twenty-fifth MOS tubes constitute a second output node circuit, wherein the thirteenth, sixteenth, eighteenth, twentieth, twenty-second and twenty-fourth MOS tubes are PMOS tubes, and the fourteenth, fifteenth, seventeenth, nineteenth, twenty-first, twenty-third and twenty-fifth MOS tubes are NMOS tubes.

[0009] The source electrodes of the thirteenth MOS tube M13, the sixteenth MOS tube M16, the eighteenth MOS tube M18, the twenty-second MOS tube M22, and the twenty-fourth MOS tube M24, the body electrodes of the thirteenth MOS tube M13, the sixteenth MOS tube M16, and the eighteenth MOS tube M18, the upper plate of the first capacitor C1, and one end of the third resistor R3 are all connected to the external power supply V DD The source and body electrodes of the fourteenth MOS tube M14, the fifteenth MOS tube M15, the seventeenth MOS tube M17, the nineteenth MOS tube M19, the twenty-first MOS tube M21, the twenty-third MOS tube M23, and the twenty-fifth MOS tube M25 and the lower plates of the second capacitor C2 and the third capacitor C3 are all connected to the ground; the gate electrodes of the thirteenth MOS tube M13, the fifteenth MOS tube M15, the seventeenth MOS tube M17, the nineteenth MOS tube M19, the twenty-first MOS tube M21, and the twenty-third MOS tube M23 are connected together and connected to the drain electrodes of the sixteenth MOS tube M16 and the seventeenth MOS tube M17; the thirteenth MOS tube M13 and the fifteenth MOS tube M21 The drains of the fourteenth MOS tube M14, the eighteenth MOS tube M18 and the nineteenth MOS tube M19 are connected together and connected to the gates of the sixteenth MOS tube M16 and the twenty-fifth MOS tube M25 and the lower plate of the first capacitor C1. The gates of the eighteenth MOS tube M18 and the twentieth MOS tube M20 are connected together and connected to the drains of the twentieth MOS tube M20 and the twenty-first MOS tube M21. The source and the body of the twentieth MOS tube M20 are connected and connected to the other end of the third resistor R3. The gates of the twenty-second MOS tube M22 and the twenty-fourth MOS tube M24 are connected to the external reference power supply V cmThe drains of the twenty-second MOS tube M22 and the twenty-third MOS tube M23 are connected together and connected to the upper plate of the second capacitor C2, the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, the seventh MOS tube M7, and the body of the twenty-second MOS tube M22; the drains of the twenty-fourth MOS tube M24 and the twenty-fifth MOS tube M25 are connected together and connected to the upper plate of the third capacitor C3, the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, the eighth MOS tube M8, and the body of the twenty-fourth MOS tube M24.

[0010] Compared with existing amplifiers, the inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier of the present invention uses a substrate bias circuit to perform PVT compensation on the amplifier, stabilizes the gain and bandwidth of the amplifier when the temperature or process parameters change, can still work normally under ultra-low voltage, and reduces the power consumption of the amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The schematic diagram of the amplification circuit of the inverter-based PVT compensation ultra-low voltage fully differential OTA amplifier of the present invention;

[0012] Figure 2 The schematic diagram of the substrate bias circuit for PVT compensation of the amplifier circuit;

[0013] FIG3( a ) is a graph showing the amplifier gain changing with temperature and process angle;

[0014] FIG3( b ) is a graph showing the amplifier bandwidth as a function of temperature and process angle;

[0015] Figure 4(a) is a graph showing gain versus frequency;

[0016] Figure 4(b) is a graph showing the phase variation with frequency. DETAILED DESCRIPTION

[0017] The present invention will be further described below in conjunction with the accompanying drawings.

[0018] like Figure 1 and Figure 2A circuit schematic diagram of an inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier provided by the present invention includes an inverter-based amplifier circuit and a PVT compensated substrate bias circuit; the inverter-based amplifier circuit includes a differential input pair composed of CMOS inverters whose substrates of PMOS and NMOS tubes are both controlled by a bias circuit, a common-mode feedback amplifier, a variable current source controlled by the common-mode feedback amplifier, and first and second resistors; the PVT compensated substrate bias circuit includes a startup circuit composed of a MOS tube, a reference current source proportional to temperature composed of a MOS tube and a resistor, and a circuit composed of a MOS tube that simultaneously outputs a PMOS tube and an NMOS tube body bias voltage; the working state of the substrate bias circuit is:

[0019] When the temperature or process parameters change, the reference current source proportional to the temperature formed by the sixteenth to twenty-first MOS tubes and the third resistor generates a changing current, and the circuit output formed by the twenty-second and twenty-third MOS tubes and the twenty-fourth and twenty-fifth MOS tubes controls the body voltage of the PMOS tube and the NMOS tube of the amplifier circuit to offset the impact of the temperature or process parameter changes on the circuit and stabilize the circuit performance.

[0020] The inverter-based amplifier circuit includes a first MOS tube M1, a second MOS tube M2, a seventh MOS tube M7, and an eighth MOS tube M8 constituting an inverter of a differential input pair, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, and a sixth MOS tube M6 as current sources controlled by a common-mode feedback amplifier, and a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, and a twelfth MOS tube M12 constituting a common-mode feedback amplifier, wherein the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, the seventh MOS tube M7, the ninth MOS tube M9, and the eleventh MOS tube M11 are PMOS tubes, and the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, the eighth MOS tube M8, the tenth MOS tube M10, and the twelfth MOS tube M12 are NMOS tubes.

[0021] The sources of the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, the seventh MOS tube M7, the ninth MOS tube M9 and the eleventh MOS tube M11 are connected to the external power supply (V DD ), the sources of the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, the eighth MOS tube M8, the tenth MOS tube M10, and the twelfth MOS tube M12 are all connected to the ground (GND), and the gates of the first MOS tube M1 and the second MOS tube M2 are all connected to the differential input signal (V in+) are connected, and the drains of the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are connected together to form an output end (V out- ), the drains of the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7, and the eighth MOS tube M8 are connected together to form another output end (V out+ ), the gates of the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, and the sixth MOS tube M6 are connected together and connected to the drains of the eleventh MOS tube M11 and the twelfth MOS tube M12, and the gates of the seventh MOS tube M7 and the eighth MOS tube M8 are connected to the differential input signal (V in- ), the body electrodes of the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, and the seventh MOS tube M7 are connected together to the first output node (V bp ), the body electrodes of the second MOS transistor M2, the fourth MOS transistor M4, the sixth MOS transistor M6, and the eighth MOS transistor M8 are connected together to the second output node (V bn ), the gates of the ninth MOS tube M9 and the eleventh MOS tube M11 are connected together and connected to the drains of the ninth MOS tube M9 and the tenth MOS tube M10, and one end of the first resistor R1 and the second resistor R2 are connected to the output port V out- 、V out+ The other end is connected to the gate of the tenth MOS tube M10, and the gate of the twelfth MOS tube M12 is connected to the external reference voltage source (V ref ).

[0022] The substrate circuit of the PVT compensation includes a startup circuit composed of a thirteenth MOS tube M13 to a fifteenth MOS tube M15, a reference current source proportional to the temperature composed of a sixteenth MOS tube M16 to a twenty-first MOS tube M21 and a third resistor R3, a twenty-second MOS tube M22 and a twenty-third MOS tube M23 forming a first output node (V bp ) circuit, the twenty-fourth MOS tube M24 and the twenty-fifth MOS tube M25 constitute the second output node (V bn ) circuit, wherein the thirteenth MOS tube M13, the sixteenth MOS tube M16, the eighteenth MOS tube M18, the twentieth MOS tube M20, the twenty-second MOS tube M22, and the twenty-fourth MOS tube M24 are PMOS tubes, and the fourteenth MOS tube M14, the fifteenth MOS tube M15, the seventeenth MOS tube M17, the nineteenth MOS tube M19, the twenty-first MOS tube M21, the twenty-third MOS tube M23, and the twenty-fifth MOS tube M25 are NMOS tubes.

[0023] The source electrodes of the thirteenth MOS tube M13, the sixteenth MOS tube M16, the eighteenth MOS tube M18, the twenty-second MOS tube M22, and the twenty-fourth MOS tube M24, the body electrodes of the thirteenth MOS tube M13, the sixteenth MOS tube M16, and the eighteenth MOS tube M18, the upper plate of the first capacitor C1, and one end of the third resistor R3 are all connected to the external power supply (V DD ), the source and body electrodes of the fourteenth MOS tube M14, the fifteenth MOS tube M15, the seventeenth MOS tube M17, the nineteenth MOS tube M19, the twenty-first MOS tube M21, the twenty-third MOS tube M23, and the twenty-fifth MOS tube M25 and the lower plates of the second capacitor C2 and the third capacitor C3 are all connected to the ground (GND), the gate electrodes of the thirteenth MOS tube M13, the fifteenth MOS tube M15, the seventeenth MOS tube M17, the nineteenth MOS tube M19, the twenty-first MOS tube M21, and the twenty-third MOS tube M23 are connected together and connected to the drain electrodes of the sixteenth MOS tube M16 and the seventeenth MOS tube M17, the thirteenth MOS tube M13 and the fifteenth MOS tube M21 The drain of the S transistor M15 is connected in common and connected to the gate of the fourteenth MOS transistor M14. The drains of the fourteenth MOS transistor M14, the eighteenth MOS transistor M18 and the nineteenth MOS transistor M19 are connected in common and connected to the gates of the sixteenth MOS transistor M16 and the twenty-fifth MOS transistor M25 and the lower plate of the first capacitor C1. The gates of the eighteenth MOS transistor M18 and the twentieth MOS transistor M20 are connected in common and connected to the drains of the twentieth MOS transistor M20 and the twenty-first MOS transistor M21. The source and body of the twentieth MOS transistor M20 are connected and connected to the other end of the third resistor R3. The gates of the twenty-second MOS transistor M22 and the twenty-fourth MOS transistor M24 are connected to the external reference power supply (V cm ), the drains of the twenty-second MOS tube M22 and the twenty-third MOS tube M23 are connected together and connected to the upper plate of the second capacitor C2, the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, the seventh MOS tube M7, and the body of the twenty-second MOS tube M22, the drains of the twenty-fourth MOS tube M24 and the twenty-fifth MOS tube M25 are connected together and connected to the upper plate of the third capacitor C3, the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, the eighth MOS tube M8, and the body of the twenty-fourth MOS tube M24.

[0024] The working principle of the present invention is described as follows: when the temperature rises, the threshold voltage of the MOS tube decreases, at which time the voltage of the biased PMOS tube body generated by the substrate bias circuit increases and the voltage of the biased NMOS tube body decreases; conversely, when the temperature decreases, the threshold voltage of the MOS tube increases, at which time the voltage of the biased PMOS tube body generated by the substrate bias circuit decreases and the voltage of the biased NMOS tube body increases, changing the threshold voltage of the MOS tube to offset the influence of temperature change on circuit performance. The same applies when process parameters change.

[0025] As shown in Figures 3(a) and 3(b), the characteristics of the inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier of the present invention vary with temperature at different process angles of 0.6V. Figure 3(a) is a diagram showing the variation of amplifier gain with temperature and process angle. When the temperature and process parameters change, the variation range of the amplifier gain is compressed to about 3dB; Figure 3(b) is a diagram showing the variation of amplifier bandwidth with temperature and process angle. When the temperature and process angle change, the bandwidth variation only decreases more at low temperature and SS process angle. In other cases, the decrease is less than 5% compared with the nominal case.

[0026] As shown in Figure 4(a) and Figure 4(b), the frequency response diagrams of the inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier of the present invention at different process angles, voltages of 0.54, 0.6, and 0.66V, and temperatures ranging from -55°C to 85°C. Figure 4(a) is a graph of gain variation with frequency, and Figure 4(b) is a graph of phase variation with frequency. From Figure 4(a), it can be seen that under different temperatures, power supply voltages, and process angles, the open-loop gain of the inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier of the present invention is about 45dB, and its -3dB bandwidth is in the range of 20MHz-50MHz. From Figure 4(b), it can be seen that under different temperatures, power supply voltages, and process angles, the phase margin of the amplifier is close to 90°.

[0027] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A PVT compensated ultra-low voltage fully differential OTA amplifier based on an inverter, characterized in that: include: An inverter-based amplifier circuit and a PVT-compensated substrate bias circuit; the inverter-based amplifier circuit comprises a differential input pair consisting of CMOS inverters whose substrates of PMOS and NMOS tubes are both controlled by a bias circuit, a common-mode feedback amplifier, a variable current source controlled by the common-mode feedback amplifier, and first and second resistors; the PVT-compensated substrate bias circuit comprises a startup circuit consisting of a MOS tube, a temperature-proportional reference current source consisting of a MOS tube and a resistor, and a circuit consisting of a MOS tube that simultaneously outputs a PMOS tube and an NMOS tube body bias voltage.

2. The inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier according to claim 1, characterized in that: The inverter-based amplifier circuit includes first to twelfth MOS tubes M1-M12 and first and second resistors; the first and second MOS tubes and the seventh and eighth MOS tubes respectively constitute a pair of inverters and serve as differential inputs of the amplifier circuit at the same time; the third to sixth MOS tubes serve as variable current sources; the ninth to twelfth MOS tubes constitute common-mode feedback amplifiers; the first, third, fifth, seventh, ninth and eleventh MOS tubes are PMOS tubes; the second, fourth, sixth, eighth, tenth and twelfth MOS tubes are NMOS tubes.

3. The inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier according to claim 2, characterized in that: The inverter-based amplifier circuit is specifically implemented as follows: The sources of the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, the seventh MOS tube M7, the ninth MOS tube M9 and the eleventh MOS tube M11 are all connected to the external power supply V DD The sources of the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, the eighth MOS tube M8, the tenth MOS tube M10 and the twelfth MOS tube M12 are all connected to the ground, and the gates of the first MOS tube M1 and the second MOS tube M2 are all connected to the differential input signal V in+ The drains of the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are connected together to form an output terminal V of the OTA amplifier. out- The drains of the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 are connected together to form another output terminal V of the OTA amplifier. out+ The gates of the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, and the sixth MOS tube M6 are connected together and connected to the drains of the eleventh MOS tube M11 and the twelfth MOS tube M12, and the gates of the seventh MOS tube M7 and the eighth MOS tube M8 are connected to the differential input signal V in- The body electrodes of the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, and the seventh MOS tube M7 are connected together and connected to the first output node V of the substrate bias circuit of the PVT compensation. bp The body electrodes of the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, and the eighth MOS tube M8 are connected together to the second output node V of the substrate bias circuit of the PVT compensation. bn The gates of the ninth MOS tube M9 and the eleventh MOS tube M11 are connected together and connected to the drains of the ninth MOS tube M9 and the tenth MOS tube M10. One end of the first resistor R1 and the second resistor R2 are connected to the output port V out- 、V out+ The other end is connected to the gate of the tenth MOS tube M10, and the gate of the twelfth MOS tube M12 is connected to the external reference voltage source V ref .

4. The inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier according to claim 3, characterized in that: The substrate bias circuit for PVT compensation includes thirteenth to twenty-fifth MOS tubes, first to third capacitors and a third resistor, the thirteenth to fifteenth MOS tubes constitute a startup circuit, the sixteenth to twenty-first MOS tubes and the third resistor constitute a reference current source proportional to the temperature, the twenty-second and twenty-third MOS tubes constitute a first output node circuit, the twenty-fourth and twenty-fifth MOS tubes constitute a second output node circuit, wherein the thirteenth, sixteenth, eighteenth, twentieth, twenty-second and twenty-fourth MOS tubes are PMOS tubes, and the fourteenth, fifteenth, seventeenth, nineteenth, twenty-first, twenty-third and twenty-fifth MOS tubes are NMOS tubes.

5. The inverter-based PVT compensated ultra-low voltage fully differential OTA amplifier according to claim 4, characterized in that: The substrate bias circuit of the PVT compensation is specifically implemented as follows: The source electrodes of the thirteenth MOS tube M13, the sixteenth MOS tube M16, the eighteenth MOS tube M18, the twenty-second MOS tube M22, and the twenty-fourth MOS tube M24, the body electrodes of the thirteenth MOS tube M13, the sixteenth MOS tube M16, and the eighteenth MOS tube M18, the upper plate of the first capacitor C1, and one end of the third resistor R3 are all connected to the external power supply V DD The source and body electrodes of the fourteenth MOS tube M14, the fifteenth MOS tube M15, the seventeenth MOS tube M17, the nineteenth MOS tube M19, the twenty-first MOS tube M21, the twenty-third MOS tube M23, and the twenty-fifth MOS tube M25 and the lower plates of the second capacitor C2 and the third capacitor C3 are all connected to the ground; the gate electrodes of the thirteenth MOS tube M13, the fifteenth MOS tube M15, the seventeenth MOS tube M17, the nineteenth MOS tube M19, the twenty-first MOS tube M21, and the twenty-third MOS tube M23 are connected together and connected to the drain electrodes of the sixteenth MOS tube M16 and the seventeenth MOS tube M17; the thirteenth MOS tube M13 and the fifteenth MOS tube M21 The drains of the fourteenth MOS tube M14, the eighteenth MOS tube M18 and the nineteenth MOS tube M19 are connected together and connected to the gates of the sixteenth MOS tube M16 and the twenty-fifth MOS tube M25 and the lower plate of the first capacitor C1. The gates of the eighteenth MOS tube M18 and the twentieth MOS tube M20 are connected together and connected to the drains of the twentieth MOS tube M20 and the twenty-first MOS tube M21. The source and the body of the twentieth MOS tube M20 are connected and connected to the other end of the third resistor R3. The gates of the twenty-second MOS tube M22 and the twenty-fourth MOS tube M24 are connected to the external reference power supply V cm The drains of the twenty-second MOS tube M22 and the twenty-third MOS tube M23 are connected together and connected to the upper plate of the second capacitor C2, the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, the seventh MOS tube M7, and the body of the twenty-second MOS tube M22; the drains of the twenty-fourth MOS tube M24 and the twenty-fifth MOS tube M25 are connected together and connected to the upper plate of the third capacitor C3, the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, the eighth MOS tube M8, and the body of the twenty-fourth MOS tube M24.

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