Radio frequency amplification circuit

Abstract

A radio frequency amplification circuit includes an input terminal, an output terminal, an amplification path and a bypass path. The input end is used for receiving a radio frequency input signal, and the output end is used for providing a radio frequency output signal. The amplification path is coupled between the input end and the output end and comprises an amplifier. The bypass path and the amplification path are coupled in parallel between the input terminal and the output terminal, and include a bypass switch, a first node, a second node, a wiring, and a variable capacitive structure. The first node is located between the input terminal and the bypass switch. The second node is located between the first node and the bypass switch. The wiring is provided between the first node and the second node. The variable capacitive structure is disposed between the first node and the second node, and includes a capacitive element and a switching element.

Description

Technical Field

[0001] The present invention relates to a radio frequency amplifier circuit, and more particularly to a radio frequency amplifier circuit capable of achieving multiple gain modes. Background Art

[0002] Wireless communication devices typically include a front-end module that can be used to amplify received radio frequency (RF) signals. The front-end module can operate in multiple gain modes to provide different levels of amplified signals. This is particularly important because it allows the wireless communication device to achieve better performance as needed based on the strength and / or quality of the received signal. In wireless communication technology, multiple gain modes may involve multiple signal transmission paths. For example, due to device size and / or layout limitations, multiple signal transmission paths may not be conducive to performance improvement. Summary of the invention

[0003] An embodiment of the present invention provides a radio frequency amplifier circuit, which includes an input terminal, an output terminal, an amplification path and a bypass path. The input terminal receives a radio frequency input signal, and the output terminal provides a radio frequency output signal. The amplification path is coupled between the input terminal and the output terminal, and includes an amplifier. The bypass path and the amplification path are coupled in parallel between the input terminal and the output terminal, and include a bypass switch, a first node, a second node, wiring and a variable capacitive structure. The first node is located between the input terminal and the bypass switch, the second node is located between the first node and the bypass switch, the wiring and the variable capacitive structure can be arranged between the first node and the second node, and the variable capacitive structure includes a capacitive element and a switch element.

[0004] Additionally or alternatively, the first node may be located between the output end and the bypass switch, the second node may be located between the first node and the bypass switch, the wiring and the variable capacitive structure are arranged between the first node and the second node, and the variable capacitive structure includes a capacitive element and a switch element. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a schematic circuit diagram of a radio frequency amplifier circuit according to an embodiment of the present invention.

[0006] Figure 2 FIG. 1 is a schematic diagram of a wiring and variable capacitance structure in a radio frequency amplifier circuit according to an embodiment of the present invention.

[0007] Schematic circuit diagram.

[0008] Figure 3 is a schematic circuit diagram of a radio frequency amplifier circuit according to another embodiment of the present invention.

[0009] Figure 4 The invention is a wiring and variable capacitance structure in a radio frequency amplifier circuit according to another embodiment of the present invention.

[0010] Schematic circuit diagram.

[0011] Figure 5 is a schematic circuit diagram of a radio frequency amplifier circuit according to another embodiment of the present invention.

[0012] Explanation of symbols

[0013] 10A, 10B, 10C: RF amplifier circuit

[0014] 20: Zoom in path

[0015] 22: Amplifier

[0016] 30A, 30B, 30C: Bypass path

[0017] 40A, 40B: Wiring

[0018] 50A, 50B, 50C: Variable capacitive structures

[0019] OUT: Output

[0020] IN: Input terminal

[0021] C1, C2: Capacitor components

[0022] REF1, REF2, REF3: Reference voltage terminals

[0023] L1, L2: Inductor components

[0024] Lp1, Lp2: Inductance

[0025] N1, N2, N3, N4: nodes

[0026] RFin: RF input signal

[0027] RFout: RF output signal

[0028] SW1, SW2: Switching elements

[0029] SWa1, SWa2, SWc: Shunt switches

[0030] SWb1, SWb2: Bypass switch

[0031] SWm1, SWm2: Amplification path switch DETAILED DESCRIPTION

[0032] Figure 11 is a schematic circuit diagram of a radio frequency (RF) amplifier circuit 10A according to an embodiment of the present invention. As shown in the figure, the RF amplifier circuit 10A may include an input terminal IN, an output terminal OUT, an amplification path 20, and a bypass path 30A. The input terminal IN may be used to receive an RF input signal RFin, and the output terminal OUT may be used to provide at least one RF output signal RFout. Furthermore, the output terminal OUT may be coupled to an antenna or another RF circuit.

[0033] In some embodiments, the amplification path 20 may be coupled between the input terminal IN and the output terminal OUT, and may include an amplification path switch SWm1 and an amplifier 22. The amplification path switch SWm1 may be coupled between the input terminal IN and the amplifier 22, a first end of which may be coupled to the input terminal IN, a second end of which may be coupled to the amplifier 22, and a control end of which may be used to receive a control signal. The amplification path switch SWm1 may control the electrical connection between the input terminal IN and the input terminal of the amplifier 22 according to the control signal. The first end (e.g., the input end) of the amplifier 22 may be coupled to the amplification path switch SWm1, and the second end (e.g., the output end) may be coupled to the output terminal OUT. In this embodiment, the RF input signal RFin received via the input terminal IN may be amplified by the amplification path 20, thereby providing a first RF output signal at the output terminal OUT. In this embodiment, the amplifier 22 is not limited to a single-stage amplifier, but may also be a multi-stage amplifier. For example, the multi-stage amplifier may include but is not limited to a pre-amplifier, an inter-stage amplifier, a buffer amplifier, or a power amplifier.

[0034] The bypass path 30A can be coupled in parallel with the amplification path 20 between the input terminal IN and the output terminal OUT. The RF input signal RFin received via the input terminal IN can be transmitted via the bypass path 30A, thereby providing a second RF output signal at the output terminal OUT. In the RF amplifier circuit 10A, the RF input signal RFin can be processed or transmitted via the amplification path 20 or the bypass path 30A, thereby outputting a first or second RF output signal at the output terminal OUT, wherein the first RF output signal and the second output signal can have different powers and / or frequencies. In some embodiments, for example, if the power of the RF input signal RFin is low and needs to be amplified, the RF input signal RFin can be amplified via the amplification path 20 to ensure communication quality. If the power of the RF input signal RFin is large and does not need to be amplified, the RF input signal RFin can be transmitted via the bypass path 30A, thereby reducing energy consumption. In other words, for the RF input signal RFin, the gain that can be provided by the amplification path 20 is greater than the gain provided by the bypass path 30A, so that the RF amplifier circuit 10A can operate in a multi-gain mode as required.

[0035] In some embodiments, the bypass path 30A may include a bypass switch SWb1, a node N1, and a node N2, wherein the node N1 may be located between the input terminal IN and the bypass switch SWb1, and the node N2 is located between the node N1 and the bypass switch SWb1. In other words, the node N1 is close to the input terminal IN, and the node N2 is close to the bypass switch SWb1. The bypass path 30A also includes a wiring 40A and a variable capacitive structure 50A disposed between the node N1 and the node N2. For example, the wiring 40A may be inductive, such as including at least one set of windings. Alternatively, the wiring 40A may be a metal wire connecting the node N1 and the node N2, and does not include windings. In this case, the wiring 40A may be equivalent to a parasitic inductance Lp1.

[0036] In some embodiments, the amplification path 20 and the bypass path 30A may be substantially disposed on the same chip, for example, the amplifier 22 of the amplification path 20 may be disposed on a first chip, and the bypass switch SWb1 of the bypass path 30A may also be disposed on the first chip. The node N1 close to the input terminal IN and the node N2 close to the bypass switch SWb1 may be located on the first chip. In this case, the wiring 40A may be located on the first chip and connected between the node N1 and the node N2, for example. However, the present invention is not limited thereto, and in other embodiments, the wiring 40A may be located on a carrier other than the first chip, for example, a printed circuit board (PCB), and connected between the nodes N1 and N2.

[0037] In other embodiments, the amplification path 20 and the bypass path 30A may be substantially disposed on different chips, for example, the amplifier 22 of the amplification path 20 may be disposed on a first chip, and the bypass switch SWb1 of the bypass path 30A may be disposed on a second chip. The node N1 close to the input terminal IN may be located on the first chip, and the node N2 close to the bypass switch SWb1 may be located on the second chip. In this case, the wiring 40A may be, for example, a metal wire connected between the first chip and the second chip, which may be located on a printed circuit board different from the first chip and the second chip.

[0038] In some embodiments, the variable capacitive structure 50A may be connected in parallel with the wiring 40A between the node N1 and the node N2, and include a capacitor C1 and a switch SW1. Figure 1 As shown, the variable capacitive structure 50A may additionally include an inductor element L1. In the variable capacitive structure 50A, the first end of the inductor element L1 may be coupled to the node N1, and the second end may be coupled to the capacitor element C1. The first end of the capacitor element C1 may be coupled to the inductor element L1, and the second end may be coupled to the switch element SW1. The first end of the switch element SW1 may be coupled to the capacitor element C1, the second end may be coupled to the node N2, and the control end may be used to receive a control signal. The switch element SW1 may be turned on or off according to the control signal. In some embodiments, the inductor element L1 may be a physical inductor element, for example, including at least one group of windings. Alternatively, the inductor element L1 may be a metal wiring connecting the node N1 and the capacitor element C1, and does not include windings. In this case, the inductor element L1 may have a parasitic inductance value. However, the present invention is not limited to this, and in other embodiments, the inductor element L1 may be omitted. In a further embodiment, the positions of the capacitor element C1 and the switch element SW1 may be interchanged.

[0039] In some embodiments, the distance between the node N1 and the node N2 may be larger, in other words, the wiring 40A may have a longer length. In this case, compared with the inductor L1, the capacitor C1 and the switch SW1 are preferably disposed closer to the bypass switch SWb1.

[0040] In the above embodiment, when the RF amplifier circuit 10A operates in the first gain mode (e.g., the amplification mode), the amplification path 20 is turned on (e.g., the amplification path switch SWm1 is turned on), and the bypass path 30A is turned off (e.g., the bypass switch SWb1 is turned off), so that the RF input signal RFin can be substantially amplified via the amplification path 20. When the RF amplifier circuit 10A operates in the second gain mode (e.g., the bypass mode), the amplification path 20 is turned off (e.g., the amplification path switch SWm1 is turned off), and the bypass path 30A is turned on (e.g., the bypass switch SWb1 is turned on), so that the RF input signal RFin can be substantially transmitted via the bypass path 30A.

[0041] Taking the first gain mode as an example, the RF input signal RFin is substantially transmitted via the amplification path 20, and the bypass switch SWb1 in the bypass path 30A can be turned off. In this case, for the RF signal, the bypass switch SWb1 in the off state can be equivalent to a load, and the load effect caused by it may cause energy loss, thereby affecting the performance of the RF amplifier circuit 10. In particular, in the case where the length of the wiring 40A is large, the load effect is particularly obvious. In this embodiment, the switch element SW1 can be turned on so that the variable capacitive structure 50A and the wiring 40A form a resonant structure. For example, by selecting a capacitor element C1 with a suitable capacitance value, the resonant frequency of the resonant structure formed by the inductor element L1, the capacitor element C1, and the wiring 40A can be equal to or equivalent to the frequency of the RF input signal RFin, for example, the difference between the resonant frequency and the frequency of the RF input signal RFin does not exceed one tenth of the frequency of the RF input signal RFin, thereby reducing the influence of the load effect generated by the wiring 40A and / or the bypass switch SWb1. In this case, in order to achieve a smaller signal loss, a larger transistor may be selected to implement the bypass switch SWb1, thereby better balancing the load effect and energy loss. Relatively speaking, if a smaller transistor is selected to implement the bypass switch SWb1, it may cause a larger energy loss in the bypass path 30B.

[0042] In other embodiments, the load effect of the bypass switch SWb1 can be reduced by selecting an inductor L1 with a suitable inductance value. For example, when the inductor L1 is a metal wiring, the length of the inductor L1 can be set, such as the distance between the node N1 and the capacitor C1.

[0043] In the above embodiment, when the RF amplifier circuit 10A operates in the second gain mode (e.g., bypass mode), the bypass switch SWb1 is turned on. In this case, the switch element SW1 can be turned off, and the variable capacitive structure 50A forms a high impedance path for the RF input signal RFin, so that the RF input signal RFin can be substantially transmitted to the output terminal OUT via the wiring 40A, the turned-on bypass switch SWb1, and subsequent other elements.

[0044] In some embodiments of the present invention, the amplification path 20 may further include an amplification path switch SWm2, a shunt switch SWa1, and a shunt switch SWa2. The amplification path switch SWm2 may be coupled between the amplifier 22 and the output terminal OUT, a first end thereof may be coupled to the amplifier 22, a second end thereof may be coupled to the output terminal OUT, and a control end thereof may be used to receive a control signal. The amplification path switch SWm2 may control the electrical connection between the output terminal OUT and the output terminal of the amplifier 22 according to the control signal. The first end of the shunt switch SWa1 may be coupled to the input terminal of the amplifier 22, for example, coupled between the amplification path switch SWm1 and the amplifier 22, and the second end of the shunt switch SWa1 may be coupled to the reference voltage terminal REF1. The first end of the shunt switch SWa2 may be coupled to the output terminal of the amplifier 2, for example, coupled between the amplifier 22 and the amplification path switch SWm2, and the second end of the shunt switch SWa2 may be coupled to the reference voltage terminal REF2.

[0045] In some embodiments of the present invention, the bypass path 30A may further include a bypass switch SWb2 and a shunt switch SWc. The bypass switch SWb2 may be coupled between the bypass switch SWb1 and the output terminal OUT, wherein a first end thereof may be coupled to the bypass switch SWb1, a second end thereof may be coupled to the output terminal OUT, and a control end thereof may be used to receive a control signal. The bypass switch SWb2 may control the electrical connection between the bypass switch SWb1 and the output terminal OUT according to the control signal. The first end of the shunt switch SWc may be coupled between the bypass switch SWb1 and the bypass switch SWb2, and a second end thereof may be coupled to the reference voltage terminal REF3. In detail, the first end of the shunt switch SWc may be coupled to the first end of the bypass switch SWb2.

[0046] In the above embodiments, the reference voltage terminals REF1 , REF2 , and REF3 may be used to provide the same or different reference voltages, respectively. In a specific embodiment, the reference voltage terminals REF1 , REF2 , and REF3 may be ground terminals, respectively.

[0047] In the above embodiment, when the RF amplifier circuit 10A operates in the first gain mode, the amplification path switches SWm1 and SWm2 in the amplification path 20 are turned on, and the bypass switches SWb1 and SWb2 in the bypass path 30A are turned off. In this case, the shunt switch SWc in the bypass path 30A can be turned on to avoid signal leakage in the bypass path 30A, thereby avoiding or reducing the influence of signal interference. Similarly, when the RF amplifier circuit 10A operates in the second gain mode, the amplification path switches SWm1 and SWm2 in the amplification path 20 are turned off, and the bypass switches SWb1 and SWb2 in the bypass path 30A are turned on. In this case, the shunt switches SWa1 and SWa2 in the amplification path 20 can be turned on to avoid signal leakage in the amplification path 20, thereby avoiding or reducing the influence of signal interference.

[0048] In the above embodiment, the variable capacitive structure 50A and the wiring 40A may be coupled in parallel between the node N1 and the node N2, wherein the capacitor C1 and the switch element SW1 of the variable capacitive structure 50A may be connected in series. The present invention is not limited thereto. Figure 2 is a schematic circuit diagram of a wiring 40A and a variable capacitive structure 50B in an RF amplifier circuit according to another embodiment of the present invention.

[0049] like Figure 2 As shown, the variable capacitive structure 50B and the wiring 40A may be coupled in series between the node N1 and the node N2. The variable capacitive structure 50B may include a capacitor C1 and a switch SW1, and the capacitor C1 and the switch SW1 may be connected in parallel.

[0050] In this embodiment, reference Figure 1 and Figure 2 When the RF amplifier circuit 10A operates in the first gain mode, the RF input signal RFin can be amplified via the amplification path 20. In this case, the switch element SW1 can be turned off, so that the capacitor element C1 in the variable capacitive structure 50A forms a resonant structure with the wiring 40A. For example, by selecting a capacitor element C1 with a suitable capacitance value, the resonant frequency of the resonant structure formed by the capacitor element C1 and the wiring 40A can be equal to or equivalent to the frequency of the RF input signal RFin, thereby reducing the influence of the load effect generated by the wiring 40A and / or the bypass switch SWb1 in the cut-off state. In this case, in order to achieve a smaller signal loss, a larger size transistor can be selected to implement the bypass switch SWb1, so as to better balance the load effect and energy loss.

[0051] Further, when the RF amplifier circuit 10A operates in the second gain mode, the RF input signal RFin can be transmitted via the bypass path 30A, in which case the bypass switch SWb1 can be turned on. The switch element SW1 can be turned on, so that the RF input signal RFin substantially avoids passing through the capacitor element C1. For example, the RF input signal RFin can be transmitted to the output terminal OUT via the wiring 40A, the turned-on bypass switch SWb1, and subsequent other elements.

[0052] Figure 3 FIG. 1 is a schematic circuit diagram of an RF amplifier circuit 10B according to another embodiment of the present invention. As shown in the figure, the RF amplifier circuit 10B is similar to Figure 1 The RF amplifier circuit 10A of FIG. 1 is not described in detail here, and only the main differences are explained. Figure 3 In the RF amplifier circuit 10B shown, the bypass path 30B further includes a node N3, a node N4, a wiring 40B and a variable capacitive structure 50C, wherein the node N3 may be located between the output terminal OUT and the bypass switch SWb2, and the node N4 may be located between the node N3 and the bypass switch SWb2. In other words, the node N3 is close to the output terminal OUT, and the node N4 is close to the bypass switch SWb2. The wiring 40B and the variable capacitive structure 50C may be arranged between the node N3 and the node N4, wherein the variable capacitive structure 50C may include a capacitive element C2, a switch element SW2, and an inductive element L2. In the present embodiment, the configuration of the variable capacitive structure 50C is similar to the variable capacitive structure 50A, the difference being that the variable capacitive structure 50C is close to the output terminal OUT, and the variable capacitive structure 50A is close to the input terminal IN.

[0053] In this embodiment, when the RF amplifier circuit 10B operates in the first gain mode, the RF input signal RFin can be amplified via the amplification path 20. The variable capacitive structure 50A forms a resonant structure with the wiring 40A, and the variable capacitive structure 50C forms a resonant structure with the wiring 40B, thereby reducing the influence of the load effect generated by the wiring 40A and / or the bypass switches SWb1 and SWb2. In this case, in order to achieve a smaller signal loss, a larger size transistor can be selected to implement the bypass switch SWb2, thereby better taking into account the load effect and energy loss. When the RF amplifier circuit 10B operates in the second gain mode, the switch element SW2 can be turned off, and the variable capacitive structure 50C forms a high impedance path, so that the RF signal can be substantially transmitted to the output terminal OUT via the wiring 40B.

[0054] Figure 4 is a schematic circuit diagram of a wiring 40B and a variable capacitive structure 50D in an RF amplifier circuit according to another embodiment of the present invention. Figure 4 The wiring 40B and the variable capacitive structure 50D can be used to replace Figure 3The wiring 40B and the variable capacitive structure 50C in FIG. Figure 4 As shown, the configuration of the variable capacitive structure 50D and the wiring 40B is similar to Figure 2 The configuration in is not described here.

[0055] Figure 5 FIG. 1 is a schematic circuit diagram of an RF amplifier circuit 10C according to another embodiment of the present invention. As shown in the figure, the RF amplifier circuit 10C is similar to Figure 3 The RF amplifier circuit 10B of FIG. 1 is not described in detail here, and only the main differences are explained. Figure 5 In the RF amplifier circuit 10C shown, the wiring 40A and the variable capacitive structure 50A are omitted. In other words, the wiring and the variable capacitive structure are provided only at a position close to the output terminal OUT.

[0056] Any of the RF amplifier circuits provided by the embodiments of the present invention can be used to achieve a multi-gain mode, wherein by setting wiring and variable capacitive structures to form a resonant structure as required, the RF amplifier circuit can have a smaller load effect and / or less loss, thereby achieving better performance.

[0057] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A radio frequency amplifier circuit, characterized in that: include: An input terminal for receiving a radio frequency input signal; An output terminal for providing a radio frequency output signal; an amplification path coupled between the input terminal and the output terminal and comprising an amplifier; as well as A bypass path is coupled in parallel with the amplification path between the input terminal and the output terminal, and comprises: a first bypass switch; a first node located between the input terminal and the first bypass switch; a second node located between the first node and the first bypass switch; a first wiring disposed between the first node and the second node; and A first variable capacitive structure is disposed between the first node and the second node and includes a first capacitive element and a first switch element.

2. The radio frequency amplifier circuit according to claim 1, characterized in that: The first variable capacitive structure is coupled in parallel with the first wiring between the first node and the second node.

3. The radio frequency amplifier circuit according to claim 2, characterized in that: The first capacitive element of the first variable capacitive structure is connected in series with the first switch element.

4. The radio frequency amplifier circuit according to claim 2, characterized in that: in: When the first bypass switch is turned off, the first switch element is turned on; or When the first bypass switch is turned on, the first switch element is turned off.

5. The radio frequency amplifier circuit according to claim 1, characterized in that: The first variable capacitive structure and the first wiring are connected in series between the first node and the second node.

6. The radio frequency amplification circuit according to claim 5, characterized in that: The first capacitance element and the first switch element of the first variable capacitance structure are connected in parallel.

7. The radio frequency amplifier circuit according to claim 5, characterized in that: in: When the first bypass switch is turned off, the first switch element is turned off; or When the first bypass switch is turned on, the first switch element is turned on.

8. The radio frequency amplifier circuit according to claim 1, characterized in that: The bypass path further includes: a second bypass switch coupled between the first bypass switch and the output terminal; a third node located between the output terminal and the second bypass switch; a fourth node located between the third node and the second bypass switch; a second wiring disposed between the third node and the fourth node; and A second variable capacitive structure is disposed between the third node and the fourth node and includes a second capacitive element and a second switch element.

9. The radio frequency amplification circuit according to claim 8, characterized in that: The second variable capacitive structure and the second wiring are coupled in parallel between the third node and the fourth node.

10. The radio frequency amplification circuit according to claim 9, characterized in that: The second capacitor element is connected in series with the second switch element.

11. The radio frequency amplification circuit according to claim 8, characterized in that: The second variable capacitive structure and the second wiring are connected in series between the third node and the fourth node.

12. The radio frequency amplification circuit according to claim 11, characterized in that: The second capacitor element is connected in parallel with the second switch element.

13. The radio frequency amplification circuit according to claim 1, characterized in that: The amplification path further includes: a first amplification path switch, coupled between the input terminal and the amplifier, for controlling the electrical connection between the input terminal and the amplifier; and A second amplification path switch is coupled between the amplifier and the output terminal, and is used to control the electrical connection between the output terminal and the amplifier.

14. The radio frequency amplification circuit according to claim 13, characterized in that: The amplification path further includes: a first shunt switch, comprising a first terminal coupled between the first amplification path switch and the amplifier, and a second terminal coupled to a first reference voltage terminal; and a second shunt switch, comprising a first terminal coupled between the amplifier and the second amplification path switch, and a second terminal coupled to a second reference voltage terminal, wherein: When the first amplifying path switch is turned off, or when the second amplifying path switch is turned off, the first shunt switch and the second shunt switch are turned on.

15. The radio frequency amplification circuit according to claim 1, characterized in that: The bypass path further includes: a second bypass switch disposed between the first bypass switch and the output terminal; and a third shunt switch, comprising a first terminal coupled between the first bypass switch and the second bypass switch, and a second terminal coupled to a third reference voltage terminal; When the first bypass switch or the second bypass switch is turned off, the third shunt switch is turned on.

16. The radio frequency amplification circuit according to claim 1, characterized in that: The first wiring has a first parasitic inductance value.

17. The radio frequency amplification circuit according to claim 1, characterized in that: The first variable capacitive structure further includes a first inductor element.

18. The radio frequency amplification circuit according to claim 1, characterized in that: The amplifier of the amplification path is disposed on a first chip, the first bypass switch of the bypass path is disposed on the first chip, and the first wiring is disposed on a first carrier.

19. The radio frequency amplification circuit according to claim 1, characterized in that: The amplifier of the amplification path is disposed on a first chip, the first bypass switch of the bypass path is disposed on a second chip, and the first wiring is disposed on a first carrier.

20. A radio frequency amplifier circuit, characterized in that: include: An input terminal for receiving a radio frequency input signal; An output terminal for providing a radio frequency output signal; an amplification path coupled between the input terminal and the output terminal and comprising an amplifier; as well as A bypass path is coupled in parallel with the amplification path between the input terminal and the output terminal, and comprises: A bypass switch; a first node located between the output terminal and the bypass switch; a second node located between the first node and the bypass switch; a wiring disposed between the first node and the second node; and A variable capacitive structure is disposed between the first node and the second node and includes a capacitive element and a switch element.

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