Semiconductor integrated circuit and electronic device

Abstract

The invention provides a semiconductor integrated circuit and an electronic device. The semiconductor integrated circuit includes: a first detection circuit that operates with a first input voltage as a power supply voltage, and asserts a first signal when a drop in the first input voltage is detected; a second detection circuit that operates with a second input voltage as a power supply voltage, and asserts a second signal when a drop in the second input voltage is detected; and an output circuit that monitors the first signal and the second signal and outputs a reset signal from the output terminal when the first signal or the second signal is asserted, the first detection circuit being a circuit that destabilizes the first signal when the first input voltage drops below a first operation limit voltage, and the second detection circuit being a circuit that destabilizes the second signal when the second input voltage drops below a second operation limit voltage. The second detection circuit destabilizes the second signal when the second input voltage drops below a second operation limit voltage, and the first operation limit voltage is lower than the second operation limit voltage.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor integrated circuit and an electronic device. Background Art

[0002] There is known a reset semiconductor integrated circuit which includes a voltage detection circuit and outputs a reset signal when a power supply voltage to be monitored falls below a predetermined level (see, for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Document 1: Japanese Patent Application Publication No. 2022-129021 Summary of the invention

[0005] Problems to be solved by the invention

[0006] When the power supply voltage of a semiconductor integrated circuit drops below the action limit voltage, the reset signal output from the semiconductor integrated circuit may become unstable. In this case, the reset of the electronic circuit may malfunction before the power supply voltage of the electronic circuit receiving the reset signal drops below the action limit voltage of the electronic circuit. For example, when the reset of the electronic circuit malfunctions too early relative to the time when the power supply voltage of the electronic circuit drops below the action limit voltage of the electronic circuit, the action voltage range of the electronic circuit may be excessively limited.

[0007] The present disclosure provides a semiconductor integrated circuit capable of reducing an operation limit voltage capable of outputting a reset signal and an electronic device having the same.

[0008] Means for solving problems

[0009] A first aspect is a semiconductor integrated circuit having:

[0010] a plurality of terminals including a first input terminal, a second input terminal, and an output terminal;

[0011] a first detection circuit that operates using a first input voltage of the first input terminal as a power supply voltage and validates a first signal when a decrease in the first input voltage is detected;

[0012] a second detection circuit that operates using a second input voltage of the second input terminal as a power supply voltage and validates a second signal when a decrease in the second input voltage is detected; and

[0013] an output circuit that monitors the first signal and the second signal and outputs a reset signal from the output terminal when the first signal or the second signal is valid,

[0014] The first detection circuit is a circuit that makes the first signal effective until the first input voltage drops from the first detection voltage to the first action limit voltage, and when the first input voltage drops below the first action limit voltage, the first signal becomes unstable.

[0015] The second detection circuit is a circuit that makes the second signal effective until the second input voltage drops from the second detection voltage to the second action limit voltage, and when the second input voltage drops below the second action limit voltage, the second signal becomes unstable.

[0016] The first operation limit voltage is lower than the second operation limit voltage.

[0017] A second aspect is a semiconductor integrated circuit according to the first aspect, wherein:

[0018] The first detection circuit includes a first transistor having a first threshold voltage, wherein the first transistor is an element that is turned off due to a gate voltage lower than the first threshold voltage when the first input voltage drops below the first action limit voltage.

[0019] The second detection circuit includes a second transistor having a second threshold voltage, wherein the second transistor is an element that is turned off due to a gate voltage lower than the second threshold voltage when the second input voltage drops below the second action limit voltage.

[0020] The first threshold voltage is lower than the second threshold voltage.

[0021] A third aspect is a semiconductor integrated circuit according to the second aspect, wherein:

[0022] The first transistor has a lower withstand voltage than the second transistor.

[0023] A fourth aspect is a semiconductor integrated circuit according to any one of the first to third aspects, wherein:

[0024] The output circuit comprises:

[0025] a logic circuit to which the first signal and the second signal are input; and

[0026] An output stage outputs the reset signal according to the output signal of the logic circuit.

[0027] A fifth aspect is an electronic device comprising:

[0028] A semiconductor integrated circuit according to any one of the first to fourth aspects;

[0029] A first power line connected to the first input terminal;

[0030] a second power line connected to the second input terminal; and

[0031] An electronic circuit is connected to the first power line and the output terminal.

[0032] A sixth aspect is the electronic device according to the fifth aspect, wherein:

[0033] The electronic device includes a regulator that steps down a voltage of the second power line and outputs the voltage to the first power line.

[0034] A seventh aspect is the electronic device according to the sixth aspect, wherein:

[0035] The second power line is connected to a battery power line of the vehicle.

[0036] Effects of the Invention

[0037] According to the present disclosure, it is possible to reduce an operation limit voltage at which a reset signal can be output. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a diagram showing a configuration example of an electronic device including the semiconductor integrated circuit according to the first embodiment.

[0039] Figure 2 A diagram showing a configuration example of an electronic device having a semiconductor integrated circuit of a comparative embodiment.

[0040] Figure 3 : is a diagram showing an example of the relationship between the gate voltage VG and the drain current IDS.

[0041] Figure 4 It is a diagram for explaining the operation limit voltage of each of the comparative example and the working example.

[0042] Figure 5 This is a timing chart showing an operation example of the semiconductor integrated circuit according to the first embodiment.

[0043] Figure 6 It is a diagram showing a configuration example of a first detection circuit.

[0044] Figure 7 It is a diagram showing a configuration example of a second detection circuit.

[0045] Figure 8 This is a diagram showing a configuration example of an electronic device including the semiconductor integrated circuit according to the second embodiment. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0047] Figure 1 This is a diagram showing a configuration example of an electronic device including the semiconductor integrated circuit according to the first embodiment. Figure 1 The electronic device 201 shown includes a reset IC 101. The reset IC 101 is an example of a semiconductor integrated circuit according to the first embodiment. A reset IC (Integrated Circuit) is also called a voltage detector.

[0048] The electronic device 201 is a vehicle device and is mounted on the vehicle for use. Specific examples of the electronic device 201 include a car navigation device, a driving recorder, an ETC (Electronic Toll Collection system) vehicle-mounted device, a USB (Universal Serial Bus) connector, a camera, a radar, a communication device, an ECU (Electronic Control Unit), etc. However, the electronic device 201 is not limited thereto.

[0049] The electronic device 201 is a device that uses a vehicle-mounted power supply (not shown) connected to a battery power supply line 63 mounted on a vehicle as an operating power supply. The electronic device 201 is operated by a DC power supplied from the vehicle-mounted power supply (not shown) via the battery power supply line 63. The vehicle-mounted power supply is, for example, a 12-volt battery. The battery power supply line 63 is, for example, a wire harness for the battery power supply.

[0050] The electronic device 201 includes a terminal BAT, a regulator 60 , a first power supply line 67 , a second power supply line 61 , an electronic circuit 70 , and a reset IC 101 .

[0051] The terminal BAT is a battery power terminal connected to the battery power line 63 of the vehicle. The battery power line 63 is connected to the second power line 61 of the electronic device 201 via the terminal BAT. The DC power supplied from the battery power line 63 is input to the second power line 61 of the electronic device 201 via the terminal BAT. The DC power input from the terminal BAT is input to the input terminal of the regulator 60 and the second input terminal VS2 of the reset IC 101 via the second power line 61. The second power line 61 is, for example, a power pattern built into the electronic device 201 and formed on a substrate on which the reset IC 101 is mounted.

[0052] The regulator 60 is a power supply circuit that steps down the DC voltage of the second power supply line 61 to a fixed power supply voltage Vdd and outputs it to the first power supply line 67. The regulator 60, for example, steps down a 12 volt DC voltage to generate a 3.3 volt power supply voltage Vdd. As a specific example of the regulator 60, a linear regulator such as an LDO (Low Drop Out) regulator can be cited. The power supply voltage Vdd generated by the regulator 60 is supplied to the power supply terminal VDD of the reset IC 101 and the power supply terminal of the electronic circuit 70 via the first power supply line 67. The first power supply line 67 is, for example, a power supply pattern built into the electronic device 201 and formed on a substrate on which the reset IC 101 is mounted.

[0053] The electronic circuit 70 is operated by the power supply voltage Vdd and is started by the reset signal S1 supplied from the reset IC 101. The electronic device 201 is started by the activation of the electronic circuit 70. The electronic circuit 70 controls the operation of the electronic device 201. Specific examples of the electronic circuit 70 include processors such as a central processing unit (CPU), a microcomputer, a system on chip (SoC), and a large-scale semiconductor integrated circuit (LSI).

[0054] The reset IC 101 has a function of monitoring the voltages of the first power line 67 and the second power line 61. The reset IC 101 monitors the voltages of the first power line 67 and the second power line 61, and outputs a reset signal S1 from the output terminal OUT to the electronic circuit 70 based on the monitoring result.

[0055] The reset IC 101 includes a first input terminal VS1 (power supply terminal VDD), a ground terminal GND, a second input terminal VS2, an output terminal OUT, a first detection circuit 10, a second detection circuit 20, and an output circuit 40. The reset IC 101 may include a release delay terminal CD.

[0056] The first input terminal VS1 (power supply terminal VDD) is connected to the first power supply line 67, and the power supply voltage Vdd of the first power supply line 67 is input. The ground terminal GND is connected to a reference potential such as a ground potential. The reset IC 101 operates with the potential of the ground terminal GND as a reference, and operates by the power supply voltage Vdd applied between the power supply terminal VDD and the ground terminal GND.

[0057] The second input terminal VS2 is connected to the second power supply line 61 and receives the power supply voltage of the second power supply line 61. The output terminal OUT is connected to the reset terminal of the electronic circuit 70 and outputs the reset signal S1 generated by the reset IC 101. The release delay terminal CD is connected to the capacitor 71 for generating the delay time of the reset signal S1.

[0058] The first detection circuit 10 is a voltage detection circuit connected to the first input terminal VS1 and operates using the voltage of the first input terminal VS1, that is, the first input voltage Vs1, as a power supply voltage (operating voltage). The first input voltage Vs1 corresponds to the power supply voltage Vdd applied between the power supply terminal VDD and the ground terminal GND.

[0059] The first detection circuit 10 detects a voltage drop at the first input terminal VS1 (more specifically, an excessively low first input voltage Vs1). The first detection circuit 10 asserts the first signal V1 when the voltage drop at the first input terminal VS1 (the drop in the first input voltage Vs1) is detected. For example, the first detection circuit 10 asserts the first signal V1 when it is detected that the first input voltage Vs1 is lower than a predetermined first detection voltage VTHD1. On the other hand, the first detection circuit 10 negates the first signal V1 when it is detected that the first input voltage Vs1 exceeds a predetermined first release voltage VTHU1.

[0060] There is a hysteresis between the first release voltage VTHU1 and the first detection voltage VTHD1. The first release voltage VTHU1 is a threshold value set to a voltage value higher than the first detection voltage VTHD1.

[0061] The second detection circuit 20 is a voltage detection circuit connected to the second input terminal VS2, and operates using the voltage of the second input terminal VS2, that is, the second input voltage Vs2, as a power supply voltage (operating voltage). The second input voltage Vs2 corresponds to the power supply voltage applied between the second input terminal VS2 and the ground terminal GND.

[0062] The second detection circuit 20 detects a voltage drop at the second input terminal VS2 (more specifically, an excessively low second input voltage Vs2). The second detection circuit 20 validates the second signal V2 when detecting a voltage drop at the second input terminal VS2 (a drop in the second input voltage Vs2). For example, the second detection circuit 20 validates the second signal V2 when detecting that the second input voltage Vs2 is lower than a predetermined second detection voltage VTHD2. On the other hand, the second detection circuit 20 invalidates the second signal V2 when detecting that the second input voltage Vs2 exceeds a predetermined second release voltage VTHU2.

[0063] There is a hysteresis between the second release voltage VTHU2 and the second detection voltage VTHD2. The second release voltage VTHU2 is a threshold value set to a voltage value higher than the second detection voltage VTHD2.

[0064] The output circuit 40 monitors the first signal V1 and the second signal V2, and outputs the reset signal S1 from the output terminal OUT when the first signal V1 or the second signal V2 is validated. Specifically, when the first detection circuit 10 detects that the first input voltage Vs1 is lower than the first detection voltage VTHD1 or when the second detection circuit 20 detects that the second input voltage Vs2 is lower than the second detection voltage VTHD2, the output circuit 40 outputs the reset signal S1 from the output terminal OUT.

[0065] The output circuit 40 monitors the first signal V1 and the second signal V2, and stops outputting the reset signal S1 from the output terminal OUT when the first signal V1 and the second signal V2 are invalidated. Specifically, when the first detection circuit 10 detects that the first input voltage Vs1 is higher than the first release voltage VTHU1 and the second detection circuit 20 detects that the second input voltage Vs2 is higher than the second release voltage VTHU2, the output circuit 40 cancels the output of the reset signal S1 from the output terminal OUT.

[0066] The output circuit 40 includes, for example, a logic circuit 41 to which the first signal V1 and the second signal V2 are input, and an output stage 42 that outputs a reset signal S1 according to an output signal G1 of the logic circuit 41. The logic circuit 41 operates using a first input voltage Vs1 corresponding to a power supply voltage Vdd applied between a power supply terminal VDD and a ground terminal GND as a power supply voltage (operating voltage).

[0067] The logic circuit 41 includes, for example, a NAND gate 45 to which the first signal V1 and the second signal V2 are input. The logic circuit 41 monitors the first signal V1 and the second signal V2 through the NAND gate 45, and when either the first signal V1 or the second signal V2 is valid, the logic circuit 41 outputs the output signal G1 of the low-level reset signal S1 from the output terminal OUT to the output stage 42. On the other hand, the logic circuit 41 monitors the first signal V1 and the second signal V2 through the NAND gate 45, and when both the first signal V1 and the second signal V2 are invalid, the logic circuit 41 stops outputting the output signal G1 to the output stage 42 and stops outputting the reset signal S1 from the output terminal OUT. As a result, the reset signal S1 is released from the output terminal OUT, and a high-level signal is output from the output terminal OUT.

[0068] The output stage 42 includes, for example, a transistor 43 that outputs a reset signal S1 in an open drain output form. The transistor 43 is, for example, a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) having a gate to which the output signal G1 is input, a source connected to the ground terminal GND, and a drain connected to the output terminal OUT. The output terminal OUT is pulled up and connected to the first power line 67 via an external resistor 65. By externally placing the resistor 65 in the reset IC 101, the high-level output voltage value of the output terminal OUT (the high-level voltage value of the reset signal S1) can be arbitrarily set by the potential of the first power line 67.

[0069] In this way, the reset IC 101 monitors the voltage of the first power line 67 connected to the first input terminal VS1 by monitoring the first input voltage Vs1, and monitors the second input voltage Vs2, thereby monitoring the voltage of the second power line 61 connected to the second input terminal VS2. When the reset IC 101 detects that the first input voltage Vs1 is lower than the prescribed first detection voltage VTHD1 or the second input voltage Vs2 is lower than the prescribed second detection voltage VTHD2, the reset IC 101 outputs a signal of a level (e.g., a low level) indicating an abnormal voltage drop state from the output terminal OUT as a reset signal S1.

[0070] On the other hand, when the reset IC101 detects that the first input voltage Vs1 is higher than the first release voltage VTHU1 and the second input voltage Vs2 is higher than the second release voltage VTHU2, it outputs a signal of a level (for example, a high level) indicating a normal voltage state from the output terminal OUT (output of the reset signal S1 is released).

[0071] Thus, the reset IC 101 of the first embodiment has a voltage drop detection function for multiple channels (in this example, the first power line 67 and the second power line 61). The voltage drop detection function for multiple channels is accommodated in the reset IC 101 of a single chip, so that the component mounting area can be reduced compared to a method of realizing the voltage drop detection function for multiple channels by multiple chips.

[0072] The first detection circuit 10 makes the first signal V1 valid until the first input voltage Vs1 drops from the first detection voltage VTHD1 to the first action limit voltage VL1. When the first input voltage Vs1 drops below the first action limit voltage VL1, the first signal V1 becomes unstable. The first action limit voltage VL1 is the action lower limit voltage at which the first detection circuit 10 can maintain the first signal V1 valid. On the other hand, the second detection circuit 20 makes the second signal V2 valid until the second input voltage Vs2 drops from the second detection voltage VTHD2 to the second action limit voltage VL2. When the second input voltage Vs2 drops below the second action limit voltage VL2, the second signal V2 becomes unstable. The second action limit voltage VL2 is the action lower limit voltage at which the second detection circuit 20 can maintain the second signal V2 valid.

[0073] In the reset IC 101 of the first embodiment, the first detection circuit 10 and the second detection circuit 20 are formed in such a manner that the first action limit voltage VL1 is lower than the second action limit voltage VL2. In this case, when the second input voltage Vs2 drops below the second action limit voltage VL2, the second signal V2 becomes unstable. On the other hand, even if the first input voltage Vs1 is reduced to the same voltage as the second action limit voltage VL2 at which the second signal V2 becomes unstable, the first signal V1 does not become unstable and remains in a valid state. By maintaining the first signal V1 valid, the output circuit 40 can maintain the output of the reset signal S1. Therefore, the action limit voltage that can output the reset signal S1 can be reduced to the first action limit voltage VL1.

[0074] Since the action limit voltage that can output the reset signal S1 can be reduced to the first action limit voltage VL1, the possibility of erroneous action for the reset of the electronic circuit 70 before the power supply voltage of the electronic circuit 70 is reduced to below the action limit voltage of the electronic circuit 70 can be reduced. In this case, for example, it is easy to adjust the timing of the reset erroneous action for the electronic circuit 70 so that it is not too early relative to the timing when the power supply voltage of the electronic circuit 70 is reduced to below the action limit voltage of the electronic circuit 70. Therefore, the possibility of excessive restriction of the action voltage range of the electronic circuit 70 can be reduced. In addition, since the voltage range that can maintain the reset signal S1 valid can be expanded downward, the reset IC 101 can be appropriately used as a reset IC for the electronic circuit 70 with a relatively low action limit voltage.

[0075] Next, in order to explain the functions and effects of the semiconductor integrated circuit according to the first embodiment in more detail, a semiconductor integrated circuit according to a comparative embodiment will be explained.

[0076] Figure 2 A diagram showing a configuration example of an electronic device having a semiconductor integrated circuit of a comparative embodiment. Figure 2 The electronic device 202 shown includes a reset IC 100. The reset IC 100 monitors the voltage of the second power supply line 61, and outputs a reset signal S1 from an output terminal OUT to the electronic circuit 70 according to the monitoring result. Figure 2 The reset IC100 shown relative to Figure 1 The reset IC 101 shown is different in that it does not include the first detection circuit 10 .

[0077] Figure 2 The second detection circuit 20 shown has Figure 1 The second detection circuit 20 has the same structure and function as the second detection circuit 20 shown above. The second detection circuit 20 is a voltage detection circuit connected to the second input terminal VS2, and operates using the voltage of the second input terminal VS2, that is, the second input voltage Vs2, as the power supply voltage (operating voltage). The second detection circuit 20 makes the second signal V2 valid until the second input voltage Vs2 drops from the second detection voltage VTHD2 to the second operating limit voltage VL2. When the second input voltage Vs2 drops below the second operating limit voltage VL2, the second signal V2 becomes unstable.

[0078] Figure 2 The output circuit 40 shown monitors the second signal V2, and outputs the reset signal S1 from the output terminal OUT when the second signal V2 is valid. The output circuit 40 includes: a logic circuit 41 to which the second signal V2 is input, and an output stage 42 that outputs the reset signal S1 according to the output signal G1 of the logic circuit 41. The logic circuit 41 operates using the second input voltage Vs2 equivalent to the power supply voltage applied between the second input terminal VS2 and the ground terminal GND as the power supply voltage (operating voltage).

[0079] The logic circuit 41 includes, for example, a NOT gate 46 to which the second signal V2 is input. The logic circuit 41 monitors the second signal V2 through the NOT gate 46, and when the second signal V2 is valid, the logic circuit 41 outputs the output signal G1 that causes the reset signal S1 of the low level to be output from the output terminal OUT to the output stage 42. On the other hand, the logic circuit 41 monitors the second signal V2 through the NOT gate 46, and when the second signal V2 is invalid, stops outputting the output signal G1 to the output stage 42, and stops outputting the reset signal S1 from the output terminal OUT. As a result, the reset signal S1 is released from the output terminal OUT, and a high-level signal is output from the output terminal OUT.

[0080] exist Figure 2 In the comparison method shown in FIG. 1 , when the second input voltage Vs2 in the second detection circuit 20 drops below the second action limit voltage VL2, the second signal V2 becomes unstable. Therefore, the action limit voltage that can output the reset signal S1 can only be reduced to the second action limit voltage VL2. Figure 1In the first embodiment shown, as described above, the operation limit voltage at which the reset signal S1 can be output can be reduced to the first operation limit voltage VL1 which is lower than the second operation limit voltage VL2 .

[0081] Due to the erroneous connection of the 24V battery for the truck, the battery power line 63 and the second power line 61 may become overvoltage. Figure 2 In the comparison shown, the second detection circuit 20 and the logic circuit 41 to which the high voltage of the second power supply line 61 may be applied, and the transistor 43 driven by the logic circuit 41 are formed to have a relatively high withstand voltage. Figure 3 As shown, a high withstand voltage NMOS transistor having a higher threshold voltage than a standard withstand voltage NMOS transistor is used. The NMOS transistor is an N-channel MOSFET.

[0082] The threshold voltage of the high withstand voltage NMOS transistor is higher than the threshold voltage of the standard withstand voltage NMOS transistor. Therefore, when the gate voltage decreases as the voltage of the second power supply line 61 (the second input voltage Vs2) decreases, the high withstand voltage NMOS transistor cannot maintain the on state at a relatively high gate voltage value. As a result, Figure 4 As shown in the upper section of FIG. 1 , when the second input voltage Vs2 is a relatively high voltage value, the reset signal S1 becomes unstable.

[0083] In contrast, Figure 1 In the first embodiment shown, the second detection circuit 20 to which the high voltage of the second power line 61 may be applied is formed to have a relatively high withstand voltage. On the other hand, the first detection circuit 10 and the logic circuit 41 to which the low voltage of the first power line 67 is applied, and the transistor 43 driven by the logic circuit 41 are formed to have a relatively low withstand voltage. Figure 3 As shown, a standard withstand voltage NMOS transistor having a threshold voltage lower than that of a high withstand voltage NMOS transistor is used.

[0084] The threshold voltage of the standard withstand voltage NMOS transistor is lower than the threshold voltage of the high withstand voltage NMOS transistor. Therefore, even if the first input voltage Vs1 decreases as the voltage of the second power supply line 61 (the second input voltage Vs2) decreases, and the gate voltage decreases as the first input voltage Vs1 decreases, the standard withstand voltage NMOS transistor can maintain the on state until the gate voltage value is relatively low. As a result, Figure 4 As shown in the lower paragraph, Figure 4 Compared with the upper section, the action limit voltage at which the reset signal S1 can be output can be lowered.

[0085] In this way, Figure 1In the first embodiment shown, the first detection circuit 10 includes, for example, a first transistor T1 having a first threshold voltage Vth1. The first transistor T1 is, for example, the standard withstand voltage NMOS transistor described above. The first transistor T1 is an element that is cut off when the first input voltage Vs1 decreases below the first action limit voltage VL1 and the gate voltage becomes lower than the first threshold voltage Vth1. On the other hand, the second detection circuit 20 includes, for example, a second transistor T2 having a second threshold voltage Vth2. The second transistor T2 is, for example, the high withstand voltage NMOS transistor described above. The second transistor T2 is an element that is cut off when the second input voltage Vs2 decreases below the second action limit voltage VL2 and the gate voltage becomes lower than the second threshold voltage Vth2.

[0086] In the reset IC 101 of the first embodiment, the first detection circuit 10 and the second detection circuit 20 are formed in such a way that the first threshold voltage Vth1 is lower than the second threshold voltage Vth2. For example, the withstand voltage of the first transistor T1 is formed to be lower than that of the second transistor T2, and thus, the first threshold voltage Vth1 is lower than the second threshold voltage Vth2. When the first threshold voltage Vth1 is lower than the second threshold voltage Vth2, even if the gate voltage of the first transistor T1 is reduced to the same voltage as the second threshold voltage Vth2 at which the second transistor T2 is cut off, the first transistor T1 is not cut off but maintained in the on state. By maintaining the on state of the first transistor T1, the validity of the first signal V1 and the level of the output signal G1 are maintained, and the output circuit 40 can maintain the output of the reset signal S1. Therefore, the action limit voltage that can output the reset signal S1 can be reduced to the first action limit voltage VL1.

[0087] Figure 5 1 is a timing diagram showing an operation example of the semiconductor integrated circuit of the first embodiment. When the first input voltage Vs1 is less than the first action limit voltage VL1, the first signal V1 output from the first detection circuit 10 becomes unstable (from time t1 to time t2). The first detection circuit 10 makes the first signal V1 valid until the first input voltage Vs1 rises from the first action limit voltage VL1 to the first release voltage VTHU1 (from time t2 to time t5). When the first input voltage Vs1 rises and becomes higher than the first release voltage VTHU1, the first detection circuit 10 switches the first signal V1 from valid to invalid (time t5). In this example, the first signal V1 is switched from a low level to a high level.

[0088] When the first input voltage Vs1 drops and becomes lower than the first detection voltage VTHD1, the first detection circuit 10 switches the first signal V1 from invalid to valid (time t9). In this example, the first signal V1 is switched from a high level to a low level. The first detection circuit 10 makes the first signal V1 valid until the first input voltage Vs1 drops from the first detection voltage VTHD1 to the first action limit voltage VL1 (time t9 to time t11). When the first input voltage Vs1 is lower than the first action limit voltage VL1, the first signal V1 output from the first detection circuit 10 becomes unstable (after time t11).

[0089] On the other hand, when the second input voltage Vs2 is less than the second action limit voltage VL2, the second signal V2 output from the second detection circuit 20 becomes unstable (time t1 to time t3). The second detection circuit 20 makes the second signal V2 valid until the second input voltage Vs2 rises from the second action limit voltage VL2 to the second release voltage VTHU2 (time t3 to time t4). When the second input voltage Vs2 rises and becomes higher than the second release voltage VTHU2, the second detection circuit 20 switches the second signal V2 from valid to invalid (time t4). In this example, the second signal V2 is switched from a low level to a high level.

[0090] When the second input voltage Vs2 decreases and becomes lower than the second detection voltage VTHD2, the second detection circuit 20 switches the second signal V2 from invalid to valid (time t6 and time t8). In this example, the second signal V2 is switched from a high level to a low level. The second detection circuit 20 makes the second signal V2 valid until the second input voltage Vs2 decreases from the second detection voltage VTHD2 to the second action limit voltage VL2 (time t8 to time t10). When the second input voltage Vs2 is lower than the second action limit voltage VL2, the second signal V2 output from the second detection circuit 20 becomes unstable (after time t10).

[0091] Therefore, when the first signal V1 or the second signal V2 is enabled, the reset IC101 outputs a low-level reset signal S1 from the output terminal OUT. On the other hand, when the first signal V1 and the second signal V2 are disabled, the reset IC101 outputs a high-level reset signal S1 from the output terminal OUT. During the period from time t6 to time t7, the second signal V2 is enabled, but the output terminal OUT is pulled up to the first power line 67 by the resistor element 65, and thus the output of the high-level reset signal S1 is maintained. The reset IC101 makes the reset signal S1 unstable when the first input voltage Vs1 is lower than the first action limit voltage VL1 which is lower than the second action limit voltage VL2. Thus, the action limit voltage at which the reset signal S1 can be output can be reduced to the first action limit voltage VL1.

[0092] Figure 6 1 is a diagram showing a configuration example of a first detection circuit. The first detection circuit 10 monitors a first input voltage Vs1. When the first detection circuit 10 detects a voltage drop state of the first input voltage Vs1, the first detection circuit 10 makes the first signal V1 valid, in which case, the first signal V1 of a low level is output. On the other hand, when the first detection circuit 10 does not detect a voltage drop state of the first input voltage Vs1, the first detection circuit 10 makes the first signal V1 invalid, in which case, the first signal V1 of a high level is output.

[0093] The first detection circuit 10 includes a resistor voltage divider circuit 18 (resistors 11, 12, and 13) and a first voltage detection circuit 1. The first voltage detection circuit 1 includes a diode 68, a comparator 17, a transistor 14, a reference voltage generation circuit 19 (a constant current source 15 and a reference voltage source 16), a transistor 51, a resistor 52, a Schmitt trigger 53, and a transistor 54.

[0094] The anode of the diode 68 is connected to the ground terminal GND, and the cathode is connected to the first input terminal VS1. The diode 68 clamps the negative first input voltage Vs1 by the forward voltage of the diode 68, thereby protecting the first detection circuit 10 from the input of the negative first input voltage Vs1. The diode 68 is, for example, an electrostatic protection element.

[0095] The resistor voltage divider circuit 18 is a monitoring circuit for monitoring the first input voltage Vs1. The resistor voltage divider circuit 18 is a series circuit of resistors 11, 12, and 13, and is connected between the ground terminal GND and the first input terminal VS1. The resistor voltage divider circuit 18 outputs a detection voltage Vs11 obtained by dividing the first input voltage Vs1 from the connection point between the resistors 11 and 12. That is, the detection voltage Vs11 is a value corresponding to the first input voltage Vs1.

[0096] In the resistor voltage divider circuit 18, when the output voltage V11 of the comparator 17 is at a low level, the transistor 14 is turned off, and thus the detection voltage Vs11 obtained by dividing the first input voltage Vs1 by the resistor 11 and the resistors 12 and 13 is output. In the resistor voltage divider circuit 18, when the output voltage V11 of the comparator 17 is at a high level, the transistor 14 is turned on, and thus the detection voltage Vs11 obtained by dividing the first input voltage Vs1 by the resistor 11 and the resistor 12 is output. Thus, the magnitude comparison between the detection voltage Vs11 generated by the resistor voltage divider circuit 18 and the reference voltage VREF generated by the reference voltage generation circuit 19 can have the above-mentioned hysteresis (= first release voltage VTHU1 - first detection voltage VTHD1).

[0097] The comparator 17 compares the detection voltage Vs11 and the reference voltage VREF, and outputs an output voltage V11 corresponding to the comparison result. The reference voltage VREF is a fixed voltage value generated by stepping down the power supply voltage Vdd by the reference voltage generation circuit 19. The reference voltage VREF is input to the non-inverting input terminal of the comparator 17, and the detection voltage Vs11 is input to the inverting input terminal of the comparator 17. When the detection voltage Vs11 is lower than the reference voltage VREF, the comparator 17 outputs a high-level output voltage V11, and when the detection voltage Vs11 is higher than the reference voltage VREF, the comparator 17 outputs a low-level output voltage V11.

[0098] The reference voltage generating circuit 19 generates a fixed reference voltage VREF lower than the power supply voltage Vdd by, for example, causing a constant current flowing from the constant current source 15 to flow to the reference voltage source 16. The constant current source 15 is, for example, composed of a depletion-type MOSFET whose drain is connected to the power supply voltage Vdd and whose gate and source are short-circuited. The reference voltage source 16 is, for example, composed of a depletion-type MOSFET connected by a diode.

[0099] Therefore, when the output voltage V11 is at a high level, the first voltage detection circuit 1 detects the voltage drop state of the first input voltage Vs1 and turns on the transistor 51. By turning on the transistor 51, the logic signal V12 becomes a low level. Through the Schmitt trigger 53, the logic signal V13 becomes a high level. By the high-level logic signal V13, the transistor 54 is turned on, and thus the low-level first signal V1 is output (the first signal V1 is validated).

[0100] On the other hand, when the output voltage V11 is at a low level, the first voltage detection circuit 1 detects that the voltage of the first input voltage Vs1 is in a normal state, and turns off the transistor 51. By turning off the transistor 51, the logic signal V12 becomes a high level. Through the Schmitt trigger 53, the logic signal V13 becomes a low level. By the low-level logic signal V13, the transistor 54 is turned off, and therefore, the high-level first signal V1 is output through the pull-up resistor (the first signal V1 is invalid).

[0101] For example, part or all of the constant current source 15 , the reference voltage source 16 , the comparator 17 , the transistors 14 , 51 , 54 , and the Schmitt trigger 53 may be formed using the first transistor T1 described above.

[0102] Figure 72 is a diagram showing a configuration example of a second detection circuit. The second detection circuit 20 monitors the second input voltage Vs2. When the second detection circuit 20 detects a voltage drop state of the second input voltage Vs2, the second detection circuit 20 makes the second signal V2 valid, in which case, the second signal V2 of a low level is output. On the other hand, when the second detection circuit 20 does not detect a voltage drop state of the second input voltage Vs2, the second detection circuit 20 makes the second signal V2 invalid, in which case, the second signal V2 of a high level is output.

[0103] The second detection circuit 20 includes a resistor voltage divider circuit 28 (resistors 21, 22, 23) and a second voltage detection circuit 2. The second voltage detection circuit 2 includes a diode 69, a comparator 27, a transistor 24, a reference voltage generation circuit 29 (a constant current source 25 and a reference voltage source 26), inverting circuits 55, 56, and a transistor 57.

[0104] The anode of the diode 69 is connected to the ground terminal GND, and the cathode is connected to the second input terminal VS2. The diode 69 clamps the negative second input voltage Vs2 by the forward voltage of the diode 69, thereby protecting the second detection circuit 20 from the influence of the input negative second input voltage Vs2. The diode 69 is, for example, an electrostatic protection element.

[0105] The resistor voltage divider circuit 28 is a monitoring circuit for monitoring the second input voltage Vs2. The resistor voltage divider circuit 28 is a series circuit of resistors 21, 22, and 23, and is connected between the ground terminal GND and the second input terminal VS2. The resistor voltage divider circuit 28 outputs a detection voltage Vs21 obtained by dividing the second input voltage Vs2 from the connection point between the resistors 21 and 22. That is, the detection voltage Vs21 is a value corresponding to the second input voltage Vs2.

[0106] In the resistor voltage divider circuit 28, when the output voltage V21 of the comparator 27 is at a low level, the transistor 24 is turned off, and thus the detection voltage Vs21 obtained by dividing the second input voltage Vs2 by the resistor 21 and the resistors 22 and 23 is output. In the resistor voltage divider circuit 28, when the output voltage V21 of the comparator 27 is at a high level, the transistor 24 is turned on, and thus the detection voltage Vs21 obtained by dividing the second input voltage Vs2 by the resistor 21 and the resistor 22 is output. Thus, the magnitude comparison between the detection voltage Vs21 generated by the resistor voltage divider circuit 28 and the reference voltage VREF generated by the reference voltage generation circuit 29 can have the above-mentioned hysteresis (= second release voltage VTHU2 - second detection voltage VTHD2).

[0107] The comparator 27 compares the detection voltage Vs21 and the reference voltage VREF, and outputs an output voltage V21 corresponding to the comparison result. The reference voltage VREF is a fixed voltage value generated by stepping down the power supply voltage Vdd by the reference voltage generation circuit 29. The reference voltage VREF is input to the non-inverting input terminal of the comparator 27, and the detection voltage Vs21 is input to the inverting input terminal of the comparator 27. The comparator 27 outputs a high-level output voltage V21 when the detection voltage Vs21 is lower than the reference voltage VREF, and outputs a low-level output voltage V21 when the detection voltage Vs21 is higher than the reference voltage VREF.

[0108] The reference voltage generating circuit 29 generates a fixed reference voltage VREF lower than the power supply voltage Vdd by, for example, causing a constant current flowing from the constant current source 25 to flow to the reference voltage source 26. The constant current source 25 is, for example, composed of a depletion-type MOSFET whose drain is connected to the power supply voltage Vdd and whose gate and source are short-circuited. The reference voltage source 26 is, for example, composed of a depletion-type MOSFET connected by a diode.

[0109] Therefore, when the output voltage V21 is at a high level, the second voltage detection circuit 2 detects the voltage drop state of the second input voltage Vs2, and makes the logic signal V22 high level through the inversion circuits 55 and 56 that invert the logic between the input and output signals. The transistor 57 is turned on by the high-level logic signal V22, and thus the low-level second signal V2 is output (the second signal V2 is validated).

[0110] On the other hand, when the output voltage V21 is at a low level, the second voltage detection circuit 2 detects that the voltage of the second input voltage Vs2 is in a normal state, and makes the logic signal V22 at a low level through the inversion circuits 55 and 56. The transistor 57 is turned off by the low-level logic signal V22, and thus, the high-level second signal V2 is output through the pull-up resistor (not shown) (the second signal V2 is invalid).

[0111] For example, part or all of the constant current source 25 , the reference voltage source 26 , the comparator 27 , the transistors 24 , 57 , and the inverting circuits 55 , 56 may be formed using the second transistor T2 described above.

[0112] Figure 8 1 is a diagram showing a configuration example of an electronic device having a semiconductor integrated circuit according to Embodiment 2. In Embodiment 2, the configuration, operation, or effect similar to that of Embodiment 1 will be omitted by citing the above description. Figure 8The electronic device 202 shown has a reset IC 102. The reset IC 102 is an example of a semiconductor integrated circuit of the second embodiment. The reset IC 102 of the second embodiment is different from the reset IC 101 of the first embodiment in that the output stage 42 is a CMOS (Complementary Metal Oxide Semiconductor) output format. The output stage 42 is operated by a power supply voltage Vdd applied between the first input terminal VS1 (power supply terminal VDD) and the ground terminal GND.

[0113] The output stage 42 includes transistors 43 and 47 that output the reset signal S1 in a CMOS output format. The output stage 42 includes an inverter circuit that complementarily combines the transistors 43 and 47. By making the output stage 42 a CMOS output format, the resistor element 65 (see Figure 1 ), it is possible to reduce the consumption current flowing to the transistor 43 via the resistor element 65 when the transistor 43 is in the on state.

[0114] As described above, the embodiments are described, but the above embodiments are presented as examples, and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other ways, and various combinations, omissions, substitutions, changes, etc. can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and their equivalents.

[0115] For example, the semiconductor integrated circuit to which the present disclosure can be applied is not limited to the reset IC, but may be other semiconductor integrated circuits such as a power supply IC.

[0116] The battery power line may be an ignition power line for transmitting an ignition signal or an auxiliary power line for transmitting an auxiliary signal.

[0117] The electronic device is not limited to a vehicle device, and may be other electronic devices for uses other than vehicles.

[0118] The reset signal S1 is not limited to being active at a low level, but may be active at a high level. The output form of the output circuit 40 may be changed as appropriate.

[0119] Explanation of symbols

[0120] 1. First voltage detection circuit

[0121] 2 Second voltage detection circuit

[0122] 10 First detection circuit

[0123] 18 Resistor voltage divider circuit

[0124] 20 Second detection circuit

[0125] 28 Resistor voltage divider circuit

[0126] 30 Third detection circuit

[0127] 40 Output Circuit

[0128] 41 Logic Circuit

[0129] 42 Output stage

[0130] 60 Regulator

[0131] 61 Second power cord

[0132] 63 Battery power cable

[0133] 67 First power line

[0134] 70 Electronic Circuits

[0135] 71 Capacitor

[0136] 100, 101, 102 Semiconductor Integrated Circuits

[0137] 200, 201, 202 electronic equipment.

Claims

1. A semiconductor integrated circuit, characterized in that: have: a plurality of terminals including a first input terminal, a second input terminal, and an output terminal; a first detection circuit that operates using a first input voltage of the first input terminal as a power supply voltage and validates a first signal when a decrease in the first input voltage is detected; a second detection circuit that operates using a second input voltage of the second input terminal as a power supply voltage and validates a second signal when a decrease in the second input voltage is detected; as well as an output circuit that monitors the first signal and the second signal and outputs a reset signal from the output terminal when the first signal or the second signal is valid, The first detection circuit is a circuit that makes the first signal effective until the first input voltage drops from the first detection voltage to the first action limit voltage, and when the first input voltage drops below the first action limit voltage, the first signal becomes unstable. The second detection circuit is a circuit that makes the second signal effective until the second input voltage drops from the second detection voltage to the second action limit voltage, and when the second input voltage drops below the second action limit voltage, the second signal becomes unstable. The first operation limit voltage is lower than the second operation limit voltage.

2. The semiconductor integrated circuit according to claim 1, wherein: The first detection circuit includes a first transistor having a first threshold voltage, wherein the first transistor is an element that is turned off due to a gate voltage lower than the first threshold voltage when the first input voltage drops below the first action limit voltage. The second detection circuit includes a second transistor having a second threshold voltage, wherein the second transistor is an element that is turned off due to a gate voltage lower than the second threshold voltage when the second input voltage drops below the second action limit voltage. The first threshold voltage is lower than the second threshold voltage.

3. The semiconductor integrated circuit according to claim 2, wherein: The first transistor has a lower withstand voltage than the second transistor.

4. The semiconductor integrated circuit according to claim 1, wherein: The output circuit comprises: a logic circuit to which the first signal and the second signal are input; and An output stage outputs the reset signal according to the output signal of the logic circuit.

5. An electronic device, characterized in that: have: The semiconductor integrated circuit according to any one of claims 1 to 4; A first power line connected to the first input terminal; a second power line connected to the second input terminal; as well as An electronic circuit is connected to the first power line and the output terminal.

6. The electronic device according to claim 5, characterized in that: The electronic device includes a regulator that steps down a voltage of the second power line and outputs the voltage to the first power line.

7. The electronic device according to claim 6, characterized in that: The second power line is connected to a battery power line of the vehicle.

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