High-end ideal diode based on voltage comparator

Abstract

A high-end ideal diode based on a voltage comparator disclosed by the present invention comprises a control circuit, the circuit comprises a comparator, a voltage comparator U1, a power supply VCC and a transistor main tube V1, the transistor main tube V1 is connected with the power supply VCC, and the comparator comprises a transistor pair transistor and a peripheral circuit thereof. The transistor pair transistor is used for comparing voltage of the source electrode and the drain electrode of the transistor main tube V1, the input end of the voltage comparator receives comparator signals, and the output end of the voltage comparator outputs signals to control on and off of the transistor main tube V1. Compared with the prior art, the high-end ideal diode based on the voltage comparator has the advantage that the high-end ideal diode based on the voltage comparator is applied in combination with characteristics of the hysteresis voltage comparator.

Description

Technical Field

[0001] The invention relates to the technical field of power diodes, and in particular to a high-end ideal diode based on a voltage comparator. Background Art

[0002] Diodes are used more and more due to their unidirectional conduction characteristics and backflow prevention functions. In particular, Schottky diodes have a smaller voltage drop and are becoming more and more popular among designers. Since the conduction voltage drop of Schottky diodes is still greater than that of MOS tubes, for some voltage-sensitive circuits, MOS tubes with low impedance characteristics are more preferred to improve product reliability.

[0003] At present, the Oring circuit is used in many occasions to ensure that each single power supply is independent of each other and does not have backflow. It is most commonly used in current sharing circuits to meet different power requirements. Therefore, a low-loss high-end ideal diode and an ultra-low-loss ideal diode are needed to further reduce the voltage drop and have the function of preventing backflow and protecting the front stage, so as to minimize the loss and extend the battery working time.

[0004] The main technical solutions for high-end ideal diodes implemented by existing technologies are as follows.

[0005] PMOS main tube + PMOS pair tube (auxiliary tube) technical solution: existing technology patent (an ultra-low loss ideal diode, patent number: CN201821304820.X), which uses PMOS main tube to realize high-end ideal diode, including comparison circuit (logic control circuit) and PMOS main tube.

[0006] NMOS main tube + NMOS pair tube (auxiliary tube) technical solution: It adopts NMOS main tube to realize high-end ideal diode. The circuit consists of an NMOS main tube, two NMOS auxiliary tubes, bias power supply VBIAS, etc. The load RL is located between the positive pole of the power supply VCC and the NMOS main tube V1. An additional higher voltage bias power supply VBIAS is required (to meet VCC+V TN <VBIAS,V TN Using two NMOS auxiliary tubes with the same parameters can ensure that the parameters of the two NMOS auxiliary tubes are basically equal, or preferably a pair of NMOS tubes packaged together, so that the parameters of the two are almost equal, thereby ensuring proper switching and anti-backflow functions.

[0007] The comparator implemented by the above technical solution belongs to a single-limit comparator: that is, the circuit has only one threshold voltage V T, any small change in the input voltage near the threshold voltage will cause a jump in the output voltage, regardless of whether the small change comes from the input signal or external interference. T When the output voltage Vo changes from V OH becomes V OL , or V OL becomes V OH The applied circuits include zero-crossing comparator and general single-limit comparator. Single-limit comparator is very sensitive, but has poor anti-interference ability. Summary of the invention

[0008] The technical problem to be solved by the present invention is to overcome the above technical defects and provide a high-end ideal diode based on a voltage comparator combined with the application of the hysteresis voltage comparator characteristics.

[0009] In order to solve the above technical problems, the present invention provides a technical solution: a high-end ideal diode based on a voltage comparator, including a control circuit, the circuit includes

[0010] A comparator, a voltage comparator U1, a power supply VCC and a transistor main body V1, wherein the transistor main body V1 is connected to the power supply VCC, the comparator comprises a transistor pair and its peripheral circuit, the transistor pair is used to compare the source and drain voltages of the transistor main body V1, the input end of the voltage comparator U1 receives a comparator signal, and the output end outputs a signal to control the conduction and cutoff of the transistor main body V1.

[0011] Preferably, the transistor pair includes any one of a PMOS auxiliary tube or an NMOS auxiliary tube, and the transistor main tube includes any one of a PMOS main tube or an NMOS main tube.

[0012] Preferably, the transistor pair is PMOS auxiliary transistors V2 and V3, the transistor main tube is PMOS main tube V1, and the peripheral circuit includes resistors R1-R2;

[0013] The source of the PMOS auxiliary tube V2 is connected to the power supply VCC, and the drain is grounded through the resistor R1;

[0014] The source of the PMOS auxiliary tube V3 is connected to the source of the PMOS main tube V1, and the drain is grounded through the resistor R2. The output end of the voltage comparator U1 is connected to the gate of the PMOS main tube V1. The source of the PMOS main tube V1 is connected to the load resistor RL.

[0015] When the drain of the PMOS auxiliary tube V3 indirectly controls the PMOS main tube V1:

[0016] The non-inverting terminal of the voltage comparator U1 is connected to the drain of the PMOS auxiliary tube V3 through the resistor R3, and the inverting terminal is connected to the source of the PMOS main tube V1 through the resistors R4 and R5. The resistor R6 is disposed between the resistors R4 and R5. The gates of the PMOS auxiliary tubes V2 and V3 are connected and connected to the resistor R1.

[0017] When the drain of the PMOS auxiliary tube V2 indirectly controls the PMOS main tube V1:

[0018] The in-phase terminal of the voltage comparator U1 is connected to the source of the PMOS main tube V1 through resistors R3 and R5, and the resistor R6 is disposed between the resistors R3 and R5. The inverting terminal is connected to the drain of the PMOS auxiliary tube V2 through the resistor R4. The gates of the PMOS auxiliary tubes V2 and V3 are connected and connected to the resistor R2.

[0019] Preferably, the transistor pair is NMOS auxiliary transistors V2 and V3, the transistor main tube is NMOS main tube V1, and the peripheral circuit includes resistors R1 to R3;

[0020] The source of the NMOS auxiliary tube V2 is connected to the power supply VCC, and the drain is connected to the bias power supply VBIAS through the resistor R1;

[0021] The source of the NMOS auxiliary tube V3 is connected to the drain of the NMOS main tube V1, and the drain is connected to the bias power supply VBIAS through the resistor R2. The output end of the voltage comparator U1 is connected to the gate of the NMOS main tube V1 to control the conduction and cutoff of the NMOS main tube V1. The drain of the NMOS main tube V1 is connected to the load resistor RL.

[0022] When the drain of the NMOS auxiliary tube V2 indirectly controls the NMOS main tube V1:

[0023] The non-inverting terminal of the voltage comparator U1 is connected to the drain of the NMOS auxiliary tube V2 through the resistor R7, and the inverting terminal is connected to the bias power supply VBIAS through the resistors R4 and R5. The resistor R6 is disposed between the resistors R4 and R5, and the gates of the NMOS auxiliary tubes V2 and V3 are connected, and are also connected to the resistor R2;

[0024] When the drain of the NMOS auxiliary tube V3 indirectly controls the NMOS main tube V1:

[0025] The in-phase end of the voltage comparator U1 is connected to the bias power supply VBIAS through resistors R7 and R5, and the resistor R6 is disposed indirectly between the resistors R7 and R5. The inverting end is connected to the drain of the NMOS auxiliary tube V3 through the resistor R4, and the gates of the NMOS auxiliary tubes V2 and V3 are connected and connected to the resistor R1.

[0026] Compared with the prior art, the present invention has the following advantages: the circuit has a backflow prevention function and can protect the previous stage circuit; it has lower loss and small static current loss; the circuit is simple, the cost is very low and the practicability is strong.

[0027] The following will further explain the concept, specific structure and technical effects of the present invention in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is the principle diagram of the back-end PMOS auxiliary tube controlling the PMOS type (main tube) high-end ideal diode of the present invention;

[0029] Figure 2 It is the principle diagram of the front-end PMOS auxiliary tube controlling the PMOS type (main tube) high-end ideal diode of the present invention;

[0030] Figure 3 It is the principle diagram of the front-end NMOS auxiliary tube controlling the NMOS type (main tube) high-end ideal diode of the present invention;

[0031] Figure 4 It is the principle diagram of the back-end NMOS auxiliary tube controlling the NMOS type (main tube) high-end ideal diode of the present invention;

[0032] Figure 5 yes Figure 1 Forward conduction simulation;

[0033] Figure 6 yes Figure 1 Reverse cutoff simulation;

[0034] Figure 7 yes Figure 2 Forward conduction simulation;

[0035] Figure 8 yes Figure 2 Reverse cutoff simulation;

[0036] Fig. 9 yes Figure 3 Forward conduction simulation;

[0037] Fig.10 yes Figure 3 Reverse cutoff simulation;

[0038] Fig.11 yes Figure 4 Forward conduction simulation;

[0039] Fig.12 yes Figure 4 Reverse cutoff simulation. DETAILED DESCRIPTION

[0040] The embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention can be implemented in many different ways as defined and covered by the claims.

[0041] Implementation Method 1

[0042] Circuit such as Figure 1 As shown, a high-end ideal diode based on a voltage comparator includes a PMOS main tube, a comparator, a voltage comparator, a bias power supply, etc. The comparator is composed of a front-end (or left-end, left side, located in front of the PMOS main tube) PMOS auxiliary tube V2 and a rear-end (or right-end, right side, located behind the PMOS main tube) PMOS auxiliary tube V3.

[0043] This circuit belongs to the drain of the back-end PMOS auxiliary tube V3 indirectly controlling the PMOS main tube V1: the drain of the back-end PMOS auxiliary tube V3 outputs a VC signal, the VC signal is compared with the reference level VREF of the voltage comparator, and the output VB signal controls the PMOS main tube V1. The working principle of the high-end ideal diode is as follows.

[0044] When the DC power supply VCC=VCC1 is powered on (forward conduction), the current output by VCC first passes through the body diode of PMOS tube V1 (Vout=VCC-V F , V F When the output current gradually increases and the internal power supply VCC is obviously higher than the external voltage Vout (VCC>Vout), the PMOS tube V2 gradually turns on (from cut-off, linear conduction, and finally to saturation conduction, and the conduction current is inversely proportional to R1), VA=VCC+V TP (V TP is the PMOS tube conduction threshold voltage); the drain-source channel impedance of the PMOS tube V3 gradually increases (from saturation conduction, linear conduction, and finally to the cut-off state), and the drain voltage VC of the PMOS tube V3 gradually decreases, and finally VC≈0V, satisfying VREF=Vout×R6 / (R6+R5)>VC, and the voltage comparator U1 outputs a low level, that is, VB≈0V. When V1 GS =VB-Vout≈-Vout≈-VCC<V TP , the drain-source channel of the PMOS tube V1 is turned on, and the VCC current passes through the drain-source low-impedance channel of the PMOS tube V1 to the load RL (no longer passes through the body diode high-impedance channel of the PMOS tube V1). The drain-source channel of the PMOS tube V1 has a small conduction impedance, that is, the conduction loss is less than that of the diode, which reduces power loss and improves power utilization efficiency.

[0045] When the external voltage Vout=VCC2 is greater than or equal to the internal power supply VCC (Vout≥VCC), the drain-source channel impedance of the PMOS tube V2 gradually increases (from saturation conduction, linear conduction, and finally to weak conduction state), and the PMOS tube V3 gradually turns on (from cutoff, linear conduction, and finally to saturation conduction, and the conduction current is inversely proportional to R2), and the voltage VC gradually increases. Finally, VC≈Vout, VC>VREF=Vout×R6 / (R6+R5), the voltage comparator U1 outputs a high level, VB=Vout, when V1 GS =VB-Vout≈0V, the drain-source channel of the PMOS tube V1 is cut off, the power supply VCC1 is isolated from the external voltage Vout, and the current of the external power supply (other power supplies connected in parallel with the voltage Vout) cannot flow back into the power supply VCC, thereby achieving the purpose of protecting the power supply VCC.

[0046] Preferably, the voltage comparator has a voltage comparator with a hysteresis loop transmission characteristic (also known as a Schmitt trigger). The threshold voltage of this comparator changes with the change of the output voltage at an accelerated rate, so the anti-interference ability is improved. The hysteresis comparator has a hysteresis characteristic, that is, inertia, and thus has a certain anti-interference ability. The stronger the anti-interference ability, the worse the sensitivity. The hysteresis comparator circuit has two threshold voltages. The input voltage VCC causes the output voltage Vout to jump in the process of gradual increase. The input voltage VCC causes the output voltage Vout to jump in the process of gradual decrease. The threshold voltage VT2, VT1≠VT2, the circuit has a hysteresis characteristic. The same as the single-limit comparator is that when the input voltage changes in a single direction, the output voltage Vout only jumps once.

[0047] Preferably, the PMOS main tube V1 can use PMOS tubes with different conduction current sizes. For high-power power supply control, the PMOS tube can select a conduction resistance R between the drain and the source. DS(ON) A power tube device with a current of several milliohms and a large flow rate. When a large current flows through it, the conduction voltage drop is small, that is, it has a very low forward voltage and can be approximated as an ideal diode.

[0048] Implementation Method 2

[0049] Circuit such as Figure 2 As shown, the circuit structure is basically the same as that of Implementation Method 1, except that: Implementation Method 1 is that the drain of the back-end PMOS auxiliary tube V3 indirectly controls the PMOS main tube V1, and Implementation Method 2 is that the drain of the front-end PMOS auxiliary tube V2 indirectly controls the PMOS main tube V1: the drain of the front-end PMOS auxiliary tube V2 outputs a VC signal, the VC signal is compared with the reference level VREF of the voltage comparator, and the VB signal is output to control the PMOS main tube V1. The working principle of the constructed high-end ideal diode is as follows.

[0050] When the DC power supply VCC=VCC1 is powered on (forward conduction), the current output by VCC first passes through the body diode of PMOS tube V1 (Vout=VCC-V F ), when the current output by VCC gradually increases, the internal power supply VCC is obviously higher than the external voltage Vout (VCC>Vout), the PMOS tube V2 gradually turns on (from cut-off, linear conduction, and finally to saturation conduction, the conduction current is inversely proportional to R1), VA = VCC + V TP The drain-source channel impedance of the PMOS tube V3 gradually increases (from saturated conduction, linear conduction, and finally to weak conduction state), and the drain voltage VC of the PMOS tube V2 gradually increases, VC≈VCC, satisfying VREF=Vout×R6 / (R6+R5)<VC, and the voltage comparator U1 outputs a low level, that is, VB≈0V. When V1 GS =VB-Vout≈-Vout<V TP , the drain-source channel of the PMOS tube V1 is turned on, and the VCC current passes through the drain-source low-impedance channel of the PMOS tube V1 to the load RL (no longer passes through the body diode high-impedance channel of the PMOS tube V1). The drain-source channel of the PMOS tube V1 has a small conduction impedance, that is, the conduction loss is less than that of the diode, which reduces power loss and improves power utilization efficiency.

[0051] When the external voltage Vout=VCC2 is greater than or equal to the internal power supply VCC (Vout≥VCC), the drain-source channel impedance of the PMOS tube V2 gradually increases (from saturation conduction, linear conduction, and finally to high resistance or cut-off state), the PMOS tube V3 gradually turns on (from cut-off, linear conduction, and finally to saturation conduction, and the conduction current is inversely proportional to R2), the voltage VC gradually decreases, and finally VC≈0V, VC<VREF=Vout×R6 / (R6+R5), the voltage comparator U1 outputs a high level, VB=Vout, when V1 GS =VB-Vout≈0V, the drain-source channel of the PMOS tube V1 is cut off, the power supply VCC1 is isolated from the external voltage Vout, and the current of the external power supply (other power supplies connected in parallel with the voltage Vout) cannot flow back into the power supply VCC, thereby achieving the purpose of protecting the power supply VCC.

[0052] Implementation Method 3

[0053] Circuit such as Figure 3As shown, a high-end ideal diode based on a voltage comparator includes an NMOS main tube, a comparator, a voltage comparator, a bias power supply, etc. The comparator is composed of a front-end NMOS auxiliary tube V2 and a back-end NMOS auxiliary tube V3. This circuit belongs to the drain of the front-end NMOS auxiliary tube V2 indirectly controlling the NMOS main tube V1: the drain of the front-end NMOS auxiliary tube V2 outputs a VC signal, the VC signal is compared with the reference level VREF of the voltage comparator, and the VB signal is output to control the NMOS main tube V1. The working principle of the high-end ideal diode is as follows.

[0054] When the DC power supply VCC=VCC1 is powered on (forward conduction), the current output by VCC first passes through the body diode of the NMOS V1 (Vout=VCC-V F ), when the output current gradually increases, the internal power supply VCC is higher than the external voltage Vout (VCC>Vout), the NMOS tube V3 gradually turns on (from cut-off, linear conduction, and finally to saturation conduction, the conduction current is inversely proportional to R2), VA=Vout+V TN ≈VCC+V TN (V TN is the NMOS tube conduction threshold voltage); the drain-source channel impedance of the NMOS tube V2 gradually increases (from saturated conduction, linear conduction, and finally to weak conduction state), and the drain voltage VC of the NMOS tube V2 gradually increases, satisfying VA<VC<VBIAS, that is, VCC+V TN <VC<VBIAS, the level of VC is relatively high, and it must satisfy VC>VREF=VBIAS×R6 / (R6+R5). When the voltage of VC is greater than VREF, the voltage comparator U1 outputs a high level, that is, VB=VBIAS(VBIAS>VCC+V TN ), the drain-source channel of the NMOS V1 is turned on, and the VCC current flows through the drain-source channel of the NMOS V1 to the load RL (no longer through the body diode of the NMOS V1). The on-resistance of the NMOS V1 is small, that is, the conduction loss is smaller than that of the diode, which reduces the power loss and improves the power utilization efficiency.

[0055] Reverse cutoff: When the external power supply Vout = VCC2 is greater than or equal to the internal power supply VCC (Vout ≥ VCC), the drain-source channel impedance of the NMOS tube V3 gradually increases to cutoff (from saturation conduction, linear conduction, and finally to weak conduction state); when VBIAS> Vout-V F When VA=VCC+V TN ; When VBIAS≤Vout-V F When Vout passes through the body diode of NMOS tube V3, VA = Vout-V F =VCC2-V F , V3GS =VA-Vout=VCC2-V F -VCC2=-V F ≤V TN , the drain-source channel of NMOS tube V3 is cut off, and NMOS tube V2 is gradually turned on (from cutoff, linear turn-on, and finally to saturation turn-on, with very small impedance, about tens of milliohms, and the on-current is inversely proportional to R2), and the voltage VC gradually decreases, and finally VC=VCC. When the voltage of VC is less than VREF, that is, VREF=VBIAS×R6 / (R6+R5)>VCC, the voltage comparator U1 outputs a low level, the drain-source channel of NMOS tube V1 is cut off, the internal power supply VCC is isolated from the external circuit, and the current of the external power supply cannot be backflowed into the internal of this power supply, thereby achieving the purpose of protecting the power supply VCC.

[0056] NMOS tube V1 can use NMOS tubes with different conduction currents. For high-power power control, the NMOS tube can choose the conduction resistance R between the drain and the source. DS(ON) A power tube device with a current of several milliohms and a large flow rate. When a large current flows through it, the conduction voltage drop is small, that is, it has a very low forward voltage and can be approximated as an ideal diode.

[0057] Implementation Method 4

[0058] Circuit such as Figure 4 As shown, the circuit structure is basically the same as that of the third implementation mode, except that: in the third implementation mode, the drain of the front-end NMOS auxiliary tube V2 indirectly controls the NMOS main tube V1, and in the fourth implementation mode, the drain of the back-end NMOS auxiliary tube V3 indirectly controls the NMOS main tube V1: the drain of the back-end NMOS auxiliary tube V3 outputs a VC signal, the VC signal is compared with the reference level VREF of the voltage comparator, and the VB signal is output to control the NMOS main tube V1. The working principle of the constructed high-end ideal diode is as follows.

[0059] When the DC power supply VCC=VCC1 is powered on (forward conduction), the current output by VCC first passes through the body diode of the NMOS V1 (Vout=VCC-V F ), when the current output by VCC gradually increases, the internal power supply VCC is higher than the external voltage Vout (VCC>Vout), the NMOS tube V3 gradually turns on (from cut-off, linear conduction, and finally to saturation conduction, the conduction current is inversely proportional to R2), VA=Vout+V TN ≈VCC+V TN (V TNis the NMOS tube conduction threshold voltage); the drain-source channel impedance of the NMOS tube V2 gradually increases (from saturated conduction, linear conduction, and finally to weak conduction state), and the drain voltage VC of the NMOS tube V2 gradually increases, satisfying VC<VA<VBIAS, that is, VA=VCC+V TN , VC≈Vout≈VCC, must satisfy VC<VREF=VBIAS×R6 / (R6+R5), when the voltage of VC is less than VREF, the voltage comparator U1 outputs a high level, that is, VB=VBIAS(VBIAS>VCC+V TN ), the drain-source channel of the NMOS V1 is turned on, and the VCC current flows through the drain-source channel of the NMOS V1 to the load RL (no longer through the body diode of the NMOS V1). The on-resistance of the NMOS V1 is small, that is, the conduction loss is smaller than that of the diode, which reduces the power loss and improves the power utilization efficiency.

[0060] Reverse cutoff: When the external voltage Vout = VCC2 is greater than or equal to the internal power supply VCC (Vout ≥ VCC), the drain-source channel impedance of the NMOS tube V3 gradually increases to cutoff (from saturation conduction, linear conduction, and finally to cutoff state): When VBIAS> Vout-V F When VA=VCC+V TN ; When VBIAS≤Vout-V F When Vout passes through the body diode of NMOS tube V3, VA = Vout-V F =VCC2-V F , V3 GS =VA-Vout=VCC2-V F -VCC2=-V F ≤V TN , the drain-source channel of NMOS tube V3 is cut off, and NMOS tube V2 is gradually turned on (from cutoff, linear turn-on, and finally to saturation turn-on, with very small impedance, about tens of milliohms, and the on-current is inversely proportional to R2), the voltage VC gradually increases, and finally VC=VBIAS. When the voltage of VC is obviously greater than VREF, that is, VC=VBIAS>VREF=VBIAS×R6 / (R6+R5), the voltage comparator U1 outputs a low level, the drain-source channel of NMOS tube V1 is cut off, the internal power supply VCC is isolated from the external circuit, and the current of the external power supply cannot be backflowed into the internal power supply, thereby achieving the purpose of protecting the power supply VCC.

[0061] according to Figure 1 to Figure 4The circuit schematic is simulated and tested using the National Instruments simulation software Multisim (version V14.0). The comparator (voltage comparator) is LMC7211AIM5, a rail-to-rail op amp, and the output stage uses push-pull amplification to achieve an approximate full swing. The PMOS tube is ON Semiconductor's NVTFS5124PLTAG, with a minimum on-state voltage of V TP(MIN) =-1.5V, maximum value V TP(MAX) =-2.5V, typical value not given, on-state current up to -6A, on-state impedance R DS(ON) =0.26Ω(V GS =-10V), R DS(ON) =0.38Ω(V GS =-4.5V). The NMOS tube is NXP's model BSP030, and the minimum on-voltage value is V TN(MIN) =1V, maximum value V TN(MAX) =2.8V, typical value not given, on-state current I D 10A / 30V, on-resistance R DS(ON) ≤0.03Ω(V GS =10V), R DS(ON) ≤0.05Ω(V GS =4.5V). Load resistance RL = 10Ω. The specific simulation test is as follows.

[0062] Implementation Method 1 Simulation

[0063] DC power supply forward conduction simulation test: set R5=R6=100kΩ, VREF≈Vout / 2, R1=R2=1MΩ, VCC=VCC1=12V (switch J1 is closed), when forward conduction, the output voltage of PMOS main tube V1 is Vout=11.7V; the drain current of PMOS auxiliary tube V2 is 9.71μA (test point PR7), and it can be considered that the drain-source channel of PMOS auxiliary tube V2 is turned on; the drain current of PMOS auxiliary tube V3 is 192nA (test point PR8), and it can be considered that the drain-source channel of PMOS auxiliary tube V3 is cut off, and the drain of PMOS auxiliary tube V3 at the back end of the comparator outputs a low level, that is, VC=192mV (test point PR2), VC is compared with VREF, and the voltage comparator U1 outputs VB=2.71mV, the drain-source channel of PMOS main tube V1 is turned on, and the conduction voltage drop is 12V-11.7V=0.3V, which is lower than the conduction voltage drop V F =0.6V, the positive output current of the power supply is 11.7V / 10Ω=1.17A, corresponding to the on-resistance R DS =0.3V / 1.17A=25.6mΩ, which is consistent with the datasheet data. Figure 5 shown.

[0064] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 15V, VCC2 > VCC (VCC1) = 12V, the drain current of PMOS auxiliary tube V2 is 9.71μA, and it can be considered that the drain-source channel of PMOS auxiliary tube V2 is weakly turned on; the drain current of PMOS auxiliary tube V3 is 15.0μA, and it can be considered that the drain-source channel of PMOS auxiliary tube V3 is turned on, and the drain of PMOS auxiliary tube V3 at the back end of the comparator outputs a high level, VC = 15.0V (test point PR2), VC is compared with VREF, and the voltage comparator U1 outputs VB = 15.0V, V1 GS =VB-Vout=3V>V TP , the drain-source channel of the PMOS V1 is cut off, there is no reverse current in the PMOS V1, the output current of VCC1 is 9.59μA (test point PR4), and no backflow current occurs. Figure 6 shown.

[0065] Implementation Method 2 Simulation

[0066] DC power supply forward conduction simulation test: set R5=R6=100kΩ, VREF≈Vout / 2, R1=R2=1MΩ, VCC=VCC1=12V (switch J1 is closed), when forward conduction, the output voltage of PMOS main tube V1 is Vout=11.7V; the drain current of PMOS auxiliary tube V2 is 12.0μA, and it can be considered that the drain-source channel of PMOS auxiliary tube V2 is turned on; the drain current of PMOS auxiliary tube V3 is 9.41μA, and it can be considered that the drain-source channel of PMOS auxiliary tube V3 is weakly turned on, and the drain of PMOS auxiliary tube V2 at the front end of the comparator outputs a high level, VC=12.0V (test point PR2), VC is compared with VREF, and the voltage comparator U1 outputs VB=2.71mV, the drain-source channel of PMOS main tube V1 is turned on, and the conduction voltage drop is 12V-11.7V=0.3V, which is lower than the conduction voltage drop V of the diode F =0.6V, the positive output current of the power supply is 11.7V / 10Ω=1.17A, corresponding to the on-resistance R DS =0.3V / 1.17A=25.6mΩ, which is consistent with the datasheet data. Figure 7 shown.

[0067] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 15V, VCC2 > VCC (VCC1) = 12V, the drain current of PMOS auxiliary tube V2 is 197nA, and the drain-source channel of PMOS auxiliary tube V2 can be considered to be cut off; the drain current of PMOS auxiliary tube V3 is 12.7μA, and the drain-source channel of PMOS auxiliary tube V3 can be considered to be turned on, and the drain of PMOS auxiliary tube V2 at the front end of the comparator outputs a low level, that is, VC = 197mV (test point PR2), VC is compared with VREF, and the voltage comparator U1 outputs VB = 15.0V, V1 GS =VB-Vout=0V>V TP , the drain-source channel of the PMOS V1 is cut off, there is no reverse current in the PMOS V1, the output current of VCC1 is 0A (test point PR4), and no backflow current occurs. Figure 8 shown.

[0068] Implementation Method 3 Simulation

[0069] DC power supply forward conduction simulation test: set R5 = 30kΩ, R6 = 70kΩ, VREF = 14.0V, R1 = R2 = 1MΩ, VCC = VCC1 = 12V (switch J1 is closed), when forward conduction, the output voltage Vout of NMOS main tube V1 is 12.0V; the drain current of NMOS auxiliary tube V2 is 5.38μA, it can be considered that the drain-source channel of NMOS auxiliary tube V2 is weakly turned on; the drain current of PMOS auxiliary tube V3 is 6.6 5μA, it can be considered that the drain-source channel of the PMOS auxiliary tube V3 is turned on, the drain of the NMOS auxiliary tube V2 at the front end of the comparator outputs a high level, VC=14.6V (test point PR2), VC is compared with VREF, the voltage comparator U1 outputs VB=20.0V, the drain-source channel of the NMOS main tube V1 is turned on, and the output voltage is 11.974V (measured by a multimeter), and the conduction voltage drop is 12V-11.974V=26mV, which is much lower than the conduction voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the on-resistance R DS =26mV / 1.20A=21.67mΩ, which is consistent with the datasheet data. Fig. 9 shown.

[0070] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 15V, VCC2 > VCC (VCC1) = 12V, the drain current of NMOS auxiliary tube V2 is 8μA, it can be considered that the drain-source channel of NMOS auxiliary tube V2 is turned on; the drain current of NMOS auxiliary tube V3 is 3.7μA, it can be considered that the drain-source channel of NMOS auxiliary tube V3 is weakly turned on, the drain output VC of NMOS auxiliary tube V2 at the front end of the comparator is 12.0V, VC is compared with VREF, the voltage comparator U1 outputs VB = 129mV, V1 GS =VB-VCC≈-12V<V TN , the drain-source channel of NMOS V1 is cut off, there is no reverse current in NMOS V1, the output bias current of VCC1 is 110μA (test point PR4, current path VCC→R3→U1 output end), and no backflow current occurs. Fig.10 shown.

[0071] Implementation Method 4 Simulation

[0072] DC power supply forward conduction simulation test: set R5 = 30kΩ, R6 = 70kΩ, VREF = 14.0V, R1 = R2 = 1MΩ, VCC = VCC1 = 12V (switch J1 is closed), when forward conduction, the output voltage Vout of NMOS main tube V1 is 12.0V; the drain current of NMOS auxiliary tube V2 is 63.5μA, which can be considered that the drain-source channel of NMOS auxiliary tube V2 is weakly conducted; the drain current of PMOS auxiliary tube V3 is 78. 4μA, it can be considered that the drain-source channel of the PMOS auxiliary tube V3 is turned on, the drain of the NMOS auxiliary tube V3 at the back end of the comparator outputs a high level, VC=12.2V (test point PR2), VC is compared with VREF, the voltage comparator U1 outputs VB=20.0V, the drain-source channel of the NMOS main tube V1 is turned on, and the output voltage is 11.974V (measured by a multimeter), and the conduction voltage drop is 12V-11.974V=26mV, which is much lower than the conduction voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the on-resistance R DS =26mV / 1.20A=21.67mΩ, which is consistent with the datasheet data. Fig.11 shown.

[0073] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 15V, VCC2 > VCC (VCC1) = 12V, the drain current of NMOS auxiliary tube V2 is 63.5μA, and the drain-source channel of NMOS auxiliary tube V2 can be considered to be turned on; the drain current of NMOS auxiliary tube V3 is 1.04nA, and the drain-source channel of NMOS auxiliary tube V3 can be considered to be cut off, and the drain output of NMOS auxiliary tube V3 at the back end of the comparator is VC = 13.7V. VC is compared with the voltage comparator VREF, and the output VB = 129mV, V1 GS =VB-VCC≈-12V<V TN , the drain-source channel of the NMOS V1 is cut off, there is no reverse current in the NPMOS V1, the VCC1 output bias current is 54.9μA (test point PR4, current path VCC→R3→U1 output end), and no backflow current occurs. Fig.12 shown.

[0074] Under the same conditions, the conduction voltage drop of the high-end ideal diode, which is a PMOS tube, is 0.3V, which is suitable for occasions with small working currents; while the conduction voltage drop of the NMOS tube is only tens of millivolts, which is suitable for occasions with large working currents, verifying that the NMOS tube has extremely low on-resistance as a supervisor.

[0075] The beneficial effects of the present invention are: compared with the milliampere level of current loss controlled by conventional power diodes or triodes, the static current loss is small, and there is no backflow current. The circuit has a backflow prevention function, which can protect the previous stage circuit; it has low loss and small static current loss; the circuit is simple, the cost is very low, and the practicability is strong.

[0076] The above circuit uses a PMOS pair of tubes as a comparator, and a PNP pair of tubes can be used as a comparator: just replace the PMOS auxiliary tube (pair of tubes) with the PNP pair of tubes in the above circuit; the above circuit uses an NMOS pair of tubes as a comparator, and an NPN pair of tubes can be used as a comparator: just replace the NMOS auxiliary tube (pair of tubes) with the NPN pair of tubes in the above circuit. The specific working principle of the circuit is similar and will not be repeated here.

[0077] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A high-end ideal diode based on a voltage comparator, characterized in that: The control circuit includes a comparator, a voltage comparator U1, a power supply VCC and a transistor main body V1. The transistor main body V1 is connected to the power supply VCC. The comparator includes a transistor pair and its peripheral circuit. The transistor pair is used to compare the source and drain voltages of the transistor main body V1. The input end of the voltage comparator U1 receives a comparator signal, and the output end outputs a signal to control the conduction and cutoff of the transistor main body V1.

2. The high-end ideal diode based on a voltage comparator according to claim 1, characterized in that: The transistor pair includes any one of a PMOS auxiliary tube and an NMOS auxiliary tube, and the transistor main tube includes any one of a PMOS main tube and an NMOS main tube.

3. The high-end ideal diode based on a voltage comparator according to claim 2, characterized in that: The transistor pair is a PMOS auxiliary transistor V2, V3, the transistor main tube is a PMOS main tube V1, and the peripheral circuit includes resistors R1-R2; The source of the PMOS auxiliary tube V2 is connected to the power supply VCC, and the drain is grounded through the resistor R1; The source of the PMOS auxiliary tube V3 is connected to the source of the PMOS main tube V1, and the drain is grounded through the resistor R2. The output end of the voltage comparator U1 is connected to the gate of the PMOS main tube V1. The source of the PMOS main tube V1 is connected to the load resistor RL. When the drain of the PMOS auxiliary tube V3 indirectly controls the PMOS main tube V1: The non-inverting terminal of the voltage comparator U1 is connected to the drain of the PMOS auxiliary tube V3 through the resistor R3, and the inverting terminal is connected to the source of the PMOS main tube V1 through the resistors R4 and R5. The resistor R6 is disposed between the resistors R4 and R5. The gates of the PMOS auxiliary tubes V2 and V3 are connected and connected to the resistor R1. When the drain of the PMOS auxiliary tube V2 indirectly controls the PMOS main tube V1: The in-phase terminal of the voltage comparator U1 is connected to the source of the PMOS main tube V1 through resistors R3 and R5, and the resistor R6 is disposed between the resistors R3 and R5. The inverting terminal is connected to the drain of the PMOS auxiliary tube V2 through the resistor R4. The gates of the PMOS auxiliary tubes V2 and V3 are connected and connected to the resistor R2.

4. The high-end ideal diode based on a voltage comparator according to claim 2, characterized in that: The transistor pair is NMOS auxiliary transistors V2 and V3, the transistor main tube is NMOS main tube V1, and the peripheral circuit includes resistors R1 to R3; The source of the NMOS auxiliary tube V2 is connected to the power supply VCC, and the drain is connected to the bias power supply VBIAS through the resistor R1; The source of the NMOS auxiliary tube V3 is connected to the drain of the NMOS main tube V1, and the drain is connected to the bias power supply VBIAS through the resistor R2. The output end of the voltage comparator U1 is connected to the gate of the NMOS main tube V1 to control the conduction and cutoff of the NMOS main tube V1. The drain of the NMOS main tube V1 is connected to the load resistor RL. When the drain of the NMOS auxiliary tube V2 indirectly controls the NMOS main tube V1: The non-inverting terminal of the voltage comparator U1 is connected to the drain of the NMOS auxiliary tube V2 through the resistor R7, and the inverting terminal is connected to the bias power supply VBIAS through the resistors R4 and R5. The resistor R6 is disposed between the resistors R4 and R5, and the gates of the NMOS auxiliary tubes V2 and V3 are connected, and are also connected to the resistor R2; When the drain of the NMOS auxiliary tube V3 indirectly controls the NMOS main tube V1: The in-phase end of the voltage comparator U1 is connected to the bias power supply VBIAS through resistors R7 and R5, and the resistor R6 is disposed indirectly between the resistors R7 and R5. The inverting end is connected to the drain of the NMOS auxiliary tube V3 through the resistor R4, and the gates of the NMOS auxiliary tubes V2 and V3 are connected and connected to the resistor R1.

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