Single bus interface circuit capable of being plugged positively and negatively

Abstract

The invention discloses a single bus interface circuit capable of being plugged forwards and backwards, relates to the technical field of communication, and aims to solve the problems that in the prior art, a single bus interface can only be plugged forwards and cannot be plugged backwards, and a packaging mold of a single bus product is complex. The single bus interface circuit at least comprises a first port, a second port, a level guiding circuit and a logic processing circuit. The level guiding circuit at least comprises a plurality of diodes; the first port and the second port are connected with the level guiding circuit; the power supply anode end and the power supply cathode end of the logic processing circuit are connected with the level guiding circuit; the plurality of diodes are used for introducing an input signal in the communication end into the power supply positive electrode end; and the logic processing circuit is used for logically processing the input signal of the first port and the input signal of the second port so as to identify the communication end and the ground end. Therefore, forward plugging and reverse plugging of the single bus interface can be simultaneously realized, and the design requirement of a single bus product packaging mold is simplified.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a single bus interface circuit capable of being plugged in either direction. Background Art

[0002] Existing single bus products have two wires, a signal line and a ground line, and are widely used in various application environments that require fewer contacts, because the fewer contact points, the higher the connection reliability and the lower the product cost.

[0003] Existing single-bus products all need to distinguish between signal lines and ground lines, and currently use a packaging mold to prevent reverse insertion.

[0004] In the prior art, the reason why a single bus interface circuit (such as the common GX18B20 temperature sensor) cannot be reversed is mainly related to the circuit design and physical connection method. For example, a single bus interface usually includes a negative power supply corresponding to the GND ground and a data line corresponding to the DQ. The functions of the above pins are clear and specific. If the DQ pin is reversed, the original data line may be connected to the ground, resulting in data transmission failure or short circuit.

[0005] In order to meet the diversified market demands, the present invention proposes a circuit that does not need to distinguish between signals and grounds, which can simplify the design requirements of a single-bus product packaging mold. Summary of the invention

[0006] The purpose of the present invention is to provide a single bus interface circuit that can be plugged in both directions, which is used to simultaneously realize the forward plugging and reverse plugging of the single bus interface and simplify the design requirements of the packaging mold of the single bus product to meet the diversified market needs.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] The present invention provides a single bus interface circuit that can be plugged in and out of the socket, comprising at least: a first port, a second port, a level guiding circuit and a logic processing circuit; wherein, either end of the first port or the second port is a ground end, and the other end is a communication end; the level guiding circuit comprises at least a plurality of diodes;

[0009] The first port and the second port are both connected to the level guiding circuit; the positive power supply terminal and the negative power supply terminal of the logic processing circuit are both connected to the level guiding circuit;

[0010] The plurality of diodes are used to introduce the input signal in the communication terminal into the positive terminal of the power supply;

[0011] The logic processing circuit is used to perform logic processing on the input signal of the first port and the input signal of the second port to realize identification of the communication end and the ground end.

[0012] Optionally, the level guiding circuit includes a first resistor, a second resistor, a first diode, a second diode, a third diode and a fourth diode;

[0013] Wherein, the first end of the first resistor is connected to the first port;

[0014] The first end of the second resistor is connected to the second port

[0015] An anode of the first diode is connected to a second end of the first resistor;

[0016] The cathode of the second diode is connected to the second end of the second resistor;

[0017] An anode of the third diode is connected to the second end of the second resistor;

[0018] The cathode of the fourth diode is connected to the second end of the first resistor;

[0019] The cathode of the first diode and the cathode of the third diode are both connected to the positive terminal of the power supply;

[0020] An anode of the second diode and an anode of the fourth diode are both connected to the negative terminal of the power supply.

[0021] Optionally, the logic processing circuit includes at least a port signal identification subcircuit;

[0022] The port signal identification subcircuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube.

[0023] Optionally, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube are all connected to the first bias voltage terminal of the logic processing circuit; the first bias voltage terminal is connected to the second end of the first resistor;

[0024] The first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube are connected in series; the source of the first PMOS tube is connected to the positive terminal of the power supply; the source of the second NMOS tube is connected to the negative terminal of the power supply;

[0025] The drain of the first PMOS tube and the source of the second PMOS tube are both connected to the source of the third PMOS tube;

[0026] The source of the first NMOS tube and the drain of the second NMOS tube are both connected to the source of the third NMOS tube;

[0027] The drain of the second PMOS tube, the drain of the first NMOS tube, the gate of the third PMOS tube, the gate of the third NMOS tube, the gate of the fourth PMOS tube and the gate of the fourth NMOS tube are all connected to the first node;

[0028] The source of the fourth PMOS tube is connected to the positive terminal of the power supply, and the source of the fourth NMOS tube is connected to the negative terminal of the power supply; the fourth PMOS tube is connected in series with the fourth NMOS tube;

[0029] The drain of the fourth PMOS tube and the drain of the fourth NMOS tube are both connected to the second node;

[0030] The gate of the fifth PMOS tube, the gate of the sixth PMOS tube, the gate of the seventh PMOS tube and the gate of the eighth PMOS tube are all connected to the second bias voltage terminal of the logic processing circuit; the second bias voltage terminal is connected to the second end of the second resistor;

[0031] The fifth PMOS tube, the sixth PMOS tube, the fifth NMOS tube and the sixth NMOS tube are connected in series; the source of the fifth PMOS tube is connected to the positive terminal of the power supply; the source of the sixth NMOS tube is connected to the negative terminal of the power supply;

[0032] The drain of the fifth PMOS tube and the source of the sixth PMOS tube are both connected to the source of the seventh PMOS tube;

[0033] The source of the fifth NMOS tube and the drain of the sixth NMOS tube are both connected to the source of the seventh NMOS tube;

[0034] The drain of the sixth PMOS tube, the drain of the fifth NMOS tube, the gate of the seventh PMOS tube, the gate of the seventh NMOS tube, the gate of the eighth PMOS tube and the gate of the eighth NMOS tube are all connected to the third node;

[0035] The source of the eighth PMOS tube is connected to the positive terminal of the power supply, and the source of the eighth NMOS tube is connected to the negative terminal of the power supply; the eighth PMOS tube is connected in series with the eighth NMOS tube;

[0036] The drain of the eighth PMOS tube and the drain of the eighth NMOS tube are both connected to the fourth node.

[0037] Optionally, the logic processing circuit further includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube.

[0038] Optionally, the gate of the ninth PMOS transistor and the gate of the ninth NMOS transistor are both connected to the second node;

[0039] The ninth PMOS tube, the tenth PMOS tube and the tenth NMOS tube are connected in series, that is, the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube, and the drain of the tenth PMOS tube is connected to the drain of the tenth NMOS tube;

[0040] The drain of the ninth NMOS tube is connected to the drain of the tenth NMOS tube; the source of the ninth NMOS tube and the source of the tenth NMOS tube are both connected to the negative power supply terminal VSS;

[0041] The drain of the tenth PMOS tube, the drain of the tenth NMOS tube, the gate of the thirteenth NMOS tube, the gate of the twelfth PMOS tube and the gate of the twelfth NMOS tube are all connected to the fifth node;

[0042] The gate of the eleventh PMOS tube and the gate of the eleventh NMOS tube are both connected to the fourth node;

[0043] The eleventh PMOS tube, the twelfth PMOS tube and the twelfth NMOS tube are connected in series, that is, the drain of the eleventh PMOS tube is connected to the source of the twelfth PMOS tube, and the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS tube;

[0044] The drain of the eleventh NMOS tube is connected to the drain of the twelfth NMOS tube; the source of the eleventh NMOS tube and the source of the twelfth NMOS tube are connected to the negative power supply terminal VSS;

[0045] The drain of the twelfth PMOS tube, the source of the twelfth NMOS tube, the gate of the ninth PMOS tube, the gate of the tenth NMOS tube and the gate of the fourteenth NMOS tube are all connected to the sixth node.

[0046] Optionally, the thirteenth NMOS tube and the fourteenth NMOS tube are both large-size power tubes.

[0047] Optionally, the reversible pluggable single bus interface circuit further includes: an ESD protection circuit; the ESD protection circuit includes: a fifth diode, a sixth diode, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a third resistor and a fourth resistor;

[0048] Wherein, the cathode of the fifth diode and the drain of the fifteenth NMOS tube are both connected to the first port;

[0049] The cathode of the sixth diode and the drain of the sixteenth NMOS tube are both connected to the second port;

[0050] The gate of the fifteenth NMOS tube is connected to the first end of the third resistor; the second end of the third resistor is connected to the first end of the fourth resistor; the second end of the fourth resistor is connected to the gate of the sixteenth NMOS tube;

[0051] The source of the fifteenth NMOS tube and the source of the sixteenth NMOS tube are both connected to the negative terminal of the power supply.

[0052] Optionally, the logic processing circuit also includes a digital analysis circuit, and the second node and the fourth node are both connected to the digital analysis circuit; the digital analysis circuit is used to identify and analyze the communication signal based on the level output by the second node and the level output by the fourth node.

[0053] Optionally, the reversible pluggable single bus interface circuit further includes a seventeenth NMOS tube and an eighteenth NMOS tube;

[0054] The drain of the seventeenth NMOS tube is connected to the first port; the drain of the eighteenth NMOS tube is connected to the second port; the source of the seventeenth NMOS tube and the source of the eighteenth NMOS tube are both connected to the negative terminal of the power supply;

[0055] The gate of the seventeenth NMOS tube and the gate of the eighteenth NMOS tube are both connected to the digital analysis circuit.

[0056] Compared with the prior art, the present invention provides a single bus interface circuit that can be plugged in forward and reverse directions. A level guiding circuit and a logic processing circuit are added after the two ports. First, the communication signal input at any one of the two ports is connected to the positive terminal of the power supply by using multiple diodes of the level guiding circuit, and the ground signal input at the other end is connected to the negative terminal of the power supply (also called the ground terminal). In this way, the problem that the two ports in the single bus interface circuit of the prior art cannot be plugged in reverse can be solved, and the working safety of the electronic components inside the circuit under the two conditions of forward and reverse plugging of the interface circuit can be guaranteed; then the communication signal and the ground signal are logically processed by the logic processing circuit, so that the communication terminal and the ground terminal can be identified, and then the corresponding signal is output for protocol analysis. In this way, the forward plugging and reverse plugging of the single bus interface can be realized at the same time, and the design requirements of the packaging mold of the single bus product are simplified, thereby meeting the diversified market needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0058] Figure 1 A schematic diagram of the circuit structure of a reversible single bus interface circuit provided by an embodiment of the present invention;

[0059] Figure 2 A schematic diagram of the circuit structure of a reversible single bus interface circuit provided by another embodiment of the present invention;

[0060] Reference numerals:

[0061] 1-level guidance circuit; 2-logic processing circuit; 3-ESD protection circuit; 21-port signal identification subcircuit; 22-digital analysis circuit. DETAILED DESCRIPTION

[0062] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0063] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0064] In the present invention, "at least one" means one or more, "more than one" means two or more. "And / or" describes the association relationship of the associated objects, indicating that three types of relationships may exist.

[0065] like Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a single bus interface circuit that can be plugged in and out, comprising at least: a first port (also known as port 0), a second port (also known as port 1), a level guiding circuit 1 and a logic processing circuit 2; wherein either end of the first port or the second port is a ground end, and the other end is a communication end; the level guiding circuit 1 comprises at least a plurality of diodes;

[0066] The logic processing circuit 2 is used to perform logic processing on the input signal of the first port and the input signal of the second port to realize identification of the communication end and the ground end.

[0067] It is understandable that the single bus protocol itself supports the parasitic power supply mode and specifies the specific method of how to transmit power and communicate data through the data line. The single bus interface includes two ports, the ground end and the signal end, the ground end is used to provide reference positioning, and the signal end is used to transmit communication signals. As mentioned in the background technology, in the entire single bus, the physical position of the power pin (such as the positive power end) of the chip where the single bus interface is located is fixed, and for the single bus, it has no external power supply, and the communication signal input by the communication end provides power for the internal circuit of the chip. The position of each pin is fixed. If the communication end and the ground end are reversely plugged, that is, the original data line may be connected to the ground, which will cause data transmission failure or short circuit of the internal circuit of the chip. Therefore, the single bus interface in the prior art can only be plugged in forward and cannot be plugged in reverse. This is also the reason why the single bus interface in the prior art adopts a packaging mold. It should be noted that the main function of the single bus interface circuit is to perform protocol analysis on the communication signal input by the communication end.

[0068] The single bus interface circuit in the prior art often includes two ports and a digital analysis circuit, so that the communication end receives the communication signal, the ground end receives the ground signal, and then the communication signal and the ground signal enter the digital analysis circuit, which performs protocol analysis on the communication signal.

[0069] Different from the prior art, in order to meet the diversified market demands, the embodiment of the present invention proposes a single bus interface circuit that does not need to distinguish between the communication end and the ground end at the single bus interface, and adds a level guidance circuit and a logic processing circuit between the two ports and the digital analysis circuit. First, the communication signal input at any one of the two ports is connected to the positive end of the power supply by using multiple diodes of the level guidance circuit, and the ground signal input at the other end is connected to the negative end of the power supply (also called the ground end). In this way, the problem that the two ports in the single bus interface circuit of the prior art cannot be reversely plugged can be solved. Then, the logic processing circuit is used to perform logic processing on the communication signal and the ground signal, so that the communication end and the ground end can be identified, and then the corresponding signal is output to the digital analysis circuit to further realize the protocol analysis of the communication signal.

[0070] Based on the above, it can be understood that Figure 2 The single bus interface circuit also includes a digital analysis circuit 22, which is used to perform protocol analysis on the communication signal.

[0071] Alternatively, if Figure 1 As shown, the level guiding circuit 1 may include a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4;

[0072] Wherein, the first end of the first resistor R1 is connected to the first port;

[0073] The first end of the second resistor R2 is connected to the second port

[0074] An anode of the first diode D1 is connected to a second end of the first resistor R1;

[0075] The cathode of the second diode D2 is connected to the second end of the second resistor R2;

[0076] An anode of the third diode D3 is connected to the second end of the second resistor R2;

[0077] The cathode of the fourth diode D4 is connected to the second end of the first resistor R1;

[0078] The cathode of the first diode D1 and the cathode of the third diode D3 are both connected to the positive terminal of the power supply;

[0079] The anode of the second diode D2 and the anode of the fourth diode D4 are both connected to the negative terminal of the power supply.

[0080] The first resistor R1 and the second resistor R2 play a role in circuit protection.

[0081] All the above diodes achieve level guidance in the following way: if port 0 is the communication terminal and port 1 is the ground terminal, that is, port 0 inputs a high level and port 1 inputs a low level, then the first diode D1 and the second diode D2 are turned on. Then the high level of port 0 is introduced into the positive power supply terminal VDD by the first diode D1, and the conduction of the second diode D2 causes the low level of port 1 to be introduced into the negative power supply terminal VSS.

[0082] If port 0 is the ground terminal and port 1 is the communication terminal, that is, port 0 inputs a low level and port 1 inputs a high level, then the third diode D3 and the fourth diode D4 are turned on. Then the high level of port 1 is introduced into the positive power supply terminal VDD by the third diode D3, and the conduction of the fourth diode D4 causes the low level of port 0 to be introduced into the negative power supply terminal VSS.

[0083] From the above content, we can see that no matter whether the input of port 0 is high or low, or whether the input of port 1 is low or high, the positive power supply terminal VDD and the negative power supply terminal VSS remain unchanged, which can ensure that the internal circuit in the single bus interface chip will not be burned and can work safely.

[0084] Alternatively, if Figure 1 or Figure 2 As shown, the logic processing circuit 2 at least includes a port signal identification subcircuit 21;

[0085] The port signal identification subcircuit 21 includes a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7 and an eighth NMOS tube N8.

[0086] The specific connection relationship of the above port signal identification subcircuit 21 is as follows: the gate of the first PMOS transistor P1, the gate of the second PMOS transistor P2, the gate of the third PMOS transistor P3 and the gate of the fourth PMOS transistor P4 are all connected to the first bias voltage terminal of the logic processing circuit 2; the first bias voltage terminal is connected to the second end of the first resistor R1;

[0087] The first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1 and the second NMOS tube N2 are connected in series, that is, the drain of the first PMOS tube P1 is connected to the source of the second PMOS tube P2, the drain of the second PMOS tube P2 is connected to the drain of the first NMOS tube N1, and the source of the first NMOS tube N1 is connected to the drain of the second NMOS tube N2; the source of the first PMOS tube P1 is connected to the positive power supply terminal VDD; the source of the second NMOS tube N2 is connected to the negative power supply terminal VSS;

[0088] The drain of the first PMOS tube P1 and the source of the second PMOS tube P2 are both connected to the source of the third PMOS tube P3; the drain of the third PMOS tube P3 is connected to the negative power supply terminal VSS;

[0089] The source of the first NMOS tube N1 and the drain of the second NMOS tube N2 are both connected to the source of the third NMOS tube N3; the drain of the third NMOS tube N3 is connected to the positive terminal VDD of the power supply;

[0090] The drain of the second PMOS tube P2, the drain of the first NMOS tube N1, the gate of the third PMOS tube P3, the gate of the third NMOS tube N3, the gate of the fourth PMOS tube P4 and the gate of the fourth NMOS tube N4 are all connected to the first node (the level signal at the first node is V1);

[0091] The source of the fourth PMOS tube P4 is connected to the positive terminal of the power supply, and the source of the fourth NMOS tube N4 is connected to the negative terminal of the power supply; the fourth PMOS tube P4 and the fourth NMOS tube N4 are connected in series;

[0092] The drain of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4 are both connected to the second node (the level signal output from the second node is V2);

[0093] From the above content, it can be known that the first bias voltage terminal is connected to the second end of the first resistor R1, that is, the combination of MOS tubes P1, P2, P3, P4, N1, N2, N3 and N4 follows the input signal of port 0 (that is, the first port). First, P1, P2, P3, N1, N2 and N3 are combined to obtain a first inverter, and P4 and N4 are combined to obtain a second inverter. The input signal of port 0 is logically converted by the first inverter to output an opposite level signal V1 at the first node (for example, if port 0 is high level, then the level V1 output from the first node is low level), and then the level V1 at the first node is logically converted again by the second inverter to obtain the level signal V2 output at the second node, wherein the level signal V2 is high level. The above process realizes that the level signal V2 output at the second node is consistent with the signal input to port 0.

[0094] The first inverter has a Schmidt hysteresis effect, which can filter out the burrs of the input port and improve the reliability of communication. The second inverter has a shaping effect, making the waveform of V2 closer to a square wave, which is convenient for subsequent digital circuit processing.

[0095] The gate of the fifth PMOS transistor P5, the gate of the sixth PMOS transistor P6, the gate of the seventh PMOS transistor P7 and the gate of the eighth PMOS transistor P8 are all connected to the second bias voltage terminal of the logic processing circuit 2; the second bias voltage terminal is connected to the second end of the second resistor R2;

[0096] The fifth PMOS tube P5, the sixth PMOS tube P6, the fifth NMOS tube N5 and the sixth NMOS tube N6 are connected in series; that is, the drain of the fifth PMOS tube P5 is connected to the source of the sixth PMOS tube P6, the drain of the sixth PMOS tube P6 is connected to the drain of the fifth NMOS tube N5, and the source of the fifth NMOS tube N5 is connected to the drain of the sixth NMOS tube N6; the source of the fifth PMOS tube P5 is connected to the positive terminal of the power supply; the source of the sixth NMOS tube N6 is connected to the negative terminal of the power supply;

[0097] The drain of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6 are both connected to the source of the seventh PMOS tube P7; the drain of the seventh PMOS tube P7 is connected to the negative power supply terminal VSS;

[0098] The source of the fifth NMOS tube N5 and the drain of the sixth NMOS tube N6 are both connected to the source of the seventh NMOS tube N7; the drain of the seventh NMOS tube N7 is connected to the positive power supply terminal VDD;

[0099] The drain of the sixth PMOS tube P6, the drain of the fifth NMOS tube N5, the gate of the seventh PMOS tube P7, the gate of the seventh NMOS tube N7, the gate of the eighth PMOS tube P8 and the gate of the eighth NMOS tube N8 are all connected to the third node (the level signal at the third node is V3);

[0100] The source of the eighth PMOS tube P8 is connected to the positive terminal of the power supply, and the source of the eighth NMOS tube N8 is connected to the negative terminal of the power supply; the eighth PMOS tube P8 and the eighth NMOS tube N8 are connected in series;

[0101] The drain of the eighth PMOS transistor P8, the drain of the eighth NMOS transistor N8 and the digital analysis circuit 22 are all connected to the fourth node (the level signal at the fourth node is V4).

[0102] From the above content, it can be known that the second bias voltage terminal is connected to the second end of the second resistor R2, that is, the combination of MOS tubes P5, P6, P7, P8, N5, N6, N7 and N8 follows the input signal of port 1 (that is, the second port). First, P5, P6, P7, N5, N6 and N7 are combined to obtain a third inverter, and P8 and N8 are combined to obtain a fourth inverter. The input signal of port 1 is logically converted by the third inverter to output an opposite level signal V3 at the third node (for example, if port 1 is low level, then the level V3 at the third node is high level), and then the level V3 at the third node is logically converted again by the fourth inverter to obtain a level signal V4 output at the fourth node, wherein the level signal V4 is low level. The above process realizes that the level signal V4 output at the fourth node is consistent with the signal input at port 1.

[0103] The third inverter has a Schmidt hysteresis effect, which can filter out the burrs of the input port and improve the reliability of communication. The fourth inverter has a shaping effect, making the waveform of V4 closer to a square wave, which is convenient for subsequent digital circuit processing.

[0104] Optionally, the logic processing circuit 2 further includes a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a ninth NMOS tube N9, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13 and a fourteenth NMOS tube N14.

[0105] The connection relationship of the above MOS transistors is: the gate of the ninth PMOS transistor P9 and the gate of the ninth NMOS transistor N9 are both connected to the second node;

[0106] The ninth PMOS tube P9, the tenth PMOS tube P10 and the tenth NMOS tube N10 are connected in series, that is, the drain of the ninth PMOS tube P9 is connected to the source of the tenth PMOS tube P10, and the drain of the tenth PMOS tube P10 is connected to the drain of the tenth NMOS tube N10;

[0107] The drain of the ninth NMOS tube N9 is connected to the drain of the tenth NMOS tube N10; the source of the ninth NMOS tube N9 and the source of the tenth NMOS tube N10 are both connected to the negative power supply terminal VSS;

[0108] The drain of the tenth PMOS tube P10, the drain of the tenth NMOS tube N10, the gate of the thirteenth NMOS tube, the gate of the twelfth PMOS tube P12 and the gate of the twelfth NMOS tube N12 are all connected to the fifth node (the level signal at the fifth node is V5);

[0109] The gate of the eleventh PMOS transistor P11 and the gate of the eleventh NMOS transistor N11 are both connected to the fourth node;

[0110] The eleventh PMOS tube P11, the twelfth PMOS tube P12 and the twelfth NMOS tube N12 are connected in series, that is, the drain of the eleventh PMOS tube P11 is connected to the source of the twelfth PMOS tube P12, and the drain of the twelfth PMOS tube P12 is connected to the drain of the twelfth NMOS tube N12;

[0111] The drain of the eleventh NMOS tube N11 is connected to the drain of the twelfth NMOS tube N12; the source of the eleventh NMOS tube N11 and the source of the twelfth NMOS tube N12 are connected to the negative power supply terminal VSS;

[0112] The drain of the twelfth PMOS tube P12, the source of the twelfth NMOS tube N12, the gate of the ninth PMOS tube P9, the gate of the tenth NMOS tube N10 and the gate of the fourteenth NMOS tube are all connected to the sixth node (the level signal at the sixth node is V6);

[0113] The source of the thirteenth NMOS tube N13 is connected to the negative terminal of the power supply, the drain of the thirteenth NMOS tube N13 is connected to the source of the fourteenth NMOS tube N14, and the drain of the fourteenth NMOS tube N14 is connected to the second end of the first resistor R1.

[0114] N13 and N14 are used to, after the internal VDD and VSS levels are initially established, 1) provide a more reliable connection from the internal VSS to the ground port, making VSS more stable, so that the internal VSS-based circuits work more reliably; 2) reduce the voltage drop from the internal VSS to the ground port, so that the operating voltage range of the internal circuit is higher and closer to the level range from the signal port to the ground port, so that the operating voltage margin of the internal circuit is larger.

[0115] It should be noted that the thirteenth NMOS tube N13 and the fourteenth NMOS tube N14 are both large-size power tubes, so that the thirteenth NMOS tube N13 and the fourteenth NMOS tube N14 can pass a large current.

[0116] From all the above contents, it can be seen that when port 0 is at a high level and port 1 is at ground: D1 is turned on, port 0 supplies power to the internal VDD; D2 is turned on, port 1 supplies power to the internal VSS; a weak voltage is generated inside the interface circuit, and the logic processing circuit 2 starts working.

[0117] The high level of port 0 makes V1 become low level and V2 become high level.

[0118] The low level of port 1 makes V3 become high level and V4 become low level;

[0119] Subsequently, V5 becomes a low level and V6 becomes a high level, causing N14 to turn off and N13 to turn on; the impedance of N13 is very low, which can provide a larger current to VSS, and a complete voltage is established inside the circuit, which can start to work normally.

[0120] When port 1 is at a high level and port 0 is at ground: D3 is turned on, port 1 supplies power to the internal VDD; D4 is turned on, port 0 supplies power to the internal VSS; a weak voltage is generated inside the interface circuit, and the logic processing circuit 2 starts working.

[0121] The low level of port 0 makes V1 become high level and V2 become low level;

[0122] The high level of port 1 makes V3 become low level and V4 become high level;

[0123] Then V5 becomes high level and V6 becomes low level, causing N14 to turn on and N13 to turn off. The impedance of N14 is very low and can provide a larger current. A complete voltage is established inside the circuit and it can start to work normally.

[0124] See also Figure 2 The single bus interface circuit that can be plugged in both directions also includes: an ESD protection circuit 3; the ESD protection circuit 3 includes: a fifth diode D5, a sixth diode D6, a fifteenth NMOS tube N15, a sixteenth NMOS tube N16, a third resistor and a fourth resistor;

[0125] Wherein, the cathode of the fifth diode D5 and the drain of the fifteenth NMOS transistor N15 are both connected to the first port;

[0126] The cathode of the sixth diode D6 and the drain of the sixteenth NMOS transistor N16 are both connected to the second port;

[0127] The gate of the fifteenth NMOS transistor N15 is connected to the first end of the third resistor; the second end of the third resistor is connected to the first end of the fourth resistor; the second end of the fourth resistor is connected to the gate of the sixteenth NMOS transistor N16;

[0128] The source of the fifteenth NMOS tube N15 and the source of the sixteenth NMOS tube N16 are both connected to the negative terminal of the power supply.

[0129] From the above content, it can be seen that the ESD protection circuit 3 can protect the single bus from being damaged by electrostatic discharge, thereby ensuring the circuit stability and reliability.

[0130] Optionally, the reversible pluggable single bus interface circuit may further include a seventeenth NMOS tube N17 and an eighteenth NMOS tube N18;

[0131] The drain of the seventeenth NMOS tube N17 is connected to the first port; the drain of the eighteenth NMOS tube N18 is connected to the second port; the source of the seventeenth NMOS tube N17 and the source of the eighteenth NMOS tube N18 are both connected to the negative terminal of the power supply;

[0132] The gate of the seventeenth NMOS transistor N17 and the gate of the eighteenth NMOS transistor N18 are both connected to the digital analysis circuit 22 .

[0133] From the above content, it can be known that after the digital analysis circuit 22 performs protocol analysis on the communication signal, the output result is output through the seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18, and output to other circuits other than the single bus interface circuit.

[0134] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0135] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A reversible single bus interface circuit, characterized in that: At least: A first port, a second port, a level guiding circuit and a logic processing circuit; wherein, either end of the first port or the second port is a ground end, and the other end is a communication end; the level guiding circuit includes at least a plurality of diodes; The first port and the second port are both connected to the level guiding circuit; the positive power supply terminal and the negative power supply terminal of the logic processing circuit are both connected to the level guiding circuit; The plurality of diodes are used to introduce the input signal in the communication terminal into the positive terminal of the power supply; The logic processing circuit is used to perform logic processing on the input signal of the first port and the input signal of the second port to realize identification of the communication end and the ground end.

2. The reversible single bus interface circuit according to claim 1, characterized in that: The level guiding circuit includes a first resistor, a second resistor, a first diode, a second diode, a third diode and a fourth diode; Wherein, the first end of the first resistor is connected to the first port; The first end of the second resistor is connected to the second port An anode of the first diode is connected to a second end of the first resistor; The cathode of the second diode is connected to the second end of the second resistor; An anode of the third diode is connected to the second end of the second resistor; The cathode of the fourth diode is connected to the second end of the first resistor; The cathode of the first diode and the cathode of the third diode are both connected to the positive terminal of the power supply; An anode of the second diode and an anode of the fourth diode are both connected to the negative terminal of the power supply.

3. The reversible single bus interface circuit according to claim 2, characterized in that: The logic processing circuit includes at least a port signal identification subcircuit; The port signal identification subcircuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube.

4. The reversible single bus interface circuit according to claim 3, characterized in that: The gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube are all connected to the first bias voltage terminal of the logic processing circuit; the first bias voltage terminal is connected to the second end of the first resistor; The first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube are connected in series; the source of the first PMOS tube is connected to the positive terminal of the power supply; the source of the second NMOS tube is connected to the negative terminal of the power supply; The drain of the first PMOS tube and the source of the second PMOS tube are both connected to the source of the third PMOS tube; The source of the first NMOS tube and the drain of the second NMOS tube are both connected to the source of the third NMOS tube; The drain of the second PMOS tube, the drain of the first NMOS tube, the gate of the third PMOS tube, the gate of the third NMOS tube, the gate of the fourth PMOS tube and the gate of the fourth NMOS tube are all connected to the first node; The source of the fourth PMOS tube is connected to the positive terminal of the power supply, and the source of the fourth NMOS tube is connected to the negative terminal of the power supply; the fourth PMOS tube is connected in series with the fourth NMOS tube; The drain of the fourth PMOS tube and the drain of the fourth NMOS tube are both connected to the second node; The gate of the fifth PMOS tube, the gate of the sixth PMOS tube, the gate of the seventh PMOS tube and the gate of the eighth PMOS tube are all connected to the second bias voltage terminal of the logic processing circuit; the second bias voltage terminal is connected to the second end of the second resistor; The fifth PMOS tube, the sixth PMOS tube, the fifth NMOS tube and the sixth NMOS tube are connected in series; the source of the fifth PMOS tube is connected to the positive terminal of the power supply; the source of the sixth NMOS tube is connected to the negative terminal of the power supply; The drain of the fifth PMOS tube and the source of the sixth PMOS tube are both connected to the source of the seventh PMOS tube; The source of the fifth NMOS tube and the drain of the sixth NMOS tube are both connected to the source of the seventh NMOS tube; The drain of the sixth PMOS tube, the drain of the fifth NMOS tube, the gate of the seventh PMOS tube, the gate of the seventh NMOS tube, the gate of the eighth PMOS tube and the gate of the eighth NMOS tube are all connected to the third node; The source of the eighth PMOS tube is connected to the positive terminal of the power supply, and the source of the eighth NMOS tube is connected to the negative terminal of the power supply; the eighth PMOS tube is connected in series with the eighth NMOS tube; The drain of the eighth PMOS tube and the drain of the eighth NMOS tube are both connected to the fourth node.

5. The reversible single bus interface circuit according to claim 4, characterized in that: The logic processing circuit also includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube.

6. The reversible single bus interface circuit according to claim 5, characterized in that: The gate of the ninth PMOS tube and the gate of the ninth NMOS tube are both connected to the second node; The ninth PMOS tube, the tenth PMOS tube and the tenth NMOS tube are connected in series, that is, the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube, and the drain of the tenth PMOS tube is connected to the drain of the tenth NMOS tube; The drain of the ninth NMOS tube is connected to the drain of the tenth NMOS tube; the source of the ninth NMOS tube and the source of the tenth NMOS tube are both connected to the negative power supply terminal VSS; The drain of the tenth PMOS tube, the drain of the tenth NMOS tube, the gate of the thirteenth NMOS tube, the gate of the twelfth PMOS tube and the gate of the twelfth NMOS tube are all connected to the fifth node; The gate of the eleventh PMOS tube and the gate of the eleventh NMOS tube are both connected to the fourth node; The eleventh PMOS tube, the twelfth PMOS tube and the twelfth NMOS tube are connected in series, that is, the drain of the eleventh PMOS tube is connected to the source of the twelfth PMOS tube, and the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS tube; The drain of the eleventh NMOS tube is connected to the drain of the twelfth NMOS tube; the source of the eleventh NMOS tube and the source of the twelfth NMOS tube are connected to the negative power supply terminal VSS; The drain of the twelfth PMOS tube, the source of the twelfth NMOS tube, the gate of the ninth PMOS tube, the gate of the tenth NMOS tube and the gate of the fourteenth NMOS tube are all connected to the sixth node.

7. The reversible single bus interface circuit according to claim 6, characterized in that: The thirteenth NMOS tube and the fourteenth NMOS tube are both large-size power tubes.

8. The reversible single bus interface circuit according to claim 4, characterized in that: Also includes: ESD protection circuit; the ESD protection circuit comprises: a fifth diode, a sixth diode, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a third resistor and a fourth resistor; Wherein, the cathode of the fifth diode and the drain of the fifteenth NMOS tube are both connected to the first port; The cathode of the sixth diode and the drain of the sixteenth NMOS tube are both connected to the second port; The gate of the fifteenth NMOS tube is connected to the first end of the third resistor; the second end of the third resistor is connected to the first end of the fourth resistor; the second end of the fourth resistor is connected to the gate of the sixteenth NMOS tube; The source of the fifteenth NMOS tube and the source of the sixteenth NMOS tube are both connected to the negative terminal of the power supply.

9. The reversible single bus interface circuit according to claim 4, characterized in that: The logic processing circuit also includes a digital analysis circuit, and the second node and the fourth node are both connected to the digital analysis circuit; the digital analysis circuit is used to identify and analyze the communication signal based on the level output by the second node and the level output by the fourth node.

10. The reversible single bus interface circuit according to claim 9, characterized in that: Also includes a seventeenth NMOS tube and an eighteenth NMOS tube; The drain of the seventeenth NMOS tube is connected to the first port; the drain of the eighteenth NMOS tube is connected to the second port; the source of the seventeenth NMOS tube and the source of the eighteenth NMOS tube are both connected to the negative terminal of the power supply; The gate of the seventeenth NMOS tube and the gate of the eighteenth NMOS tube are both connected to the digital analysis circuit.

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