Charge pump current mismatch calibration method and calibration circuit thereof

Abstract

The invention relates to the technical field of phase-locked loops, in particular to a charge pump current mismatch calibration method and a calibration circuit thereof. According to the charge pump current mismatch calibration method, the first counting module and the second counting module are matched with the state of the state machine module to control the size of the charge and discharge current mirror of the output charge pump so as to carry out current mismatch calibration, any PLL output frequency can be calibrated under any condition, the applicability is high, and the calibrated charge pump current mismatch is small.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loops, and in particular to a charge pump current mismatch calibration method and a calibration circuit thereof. Background Art

[0002] Low spurious phase-locked loops (PLLs) can provide signals with high frequency purity, which is very important for applications such as high-performance wireless communications, test and measurement equipment, and precision clock generation. Therefore, PLLs are crucial in many application areas. When PLL spurious signals are high, they will also contribute a large amount of noise to the PLL output jitter, so it is crucial for PLLs to achieve low spurious signals.

[0003] The PLL loop charge pump current mismatch is the main source of PLL output reference spurs. The greater the charge pump current mismatch, the greater the PLL output reference spurs, so it is difficult to design a charge pump with low current mismatch. At present, a multi-loop feedback op amp is usually used to feedback control the charge pump current mirror to achieve a lower charge pump current mismatch. The disadvantage is that when the PLL loop control voltage Vctrl range is large, the channel length modulation effect of the transistor of the charge pump charging and discharging current mirror will increase the mismatch of the current mirror.

[0004] In order to solve the above problem, the prior art realizes charge pump current mismatch through the current mirror design of the charge pump itself and the analog method of operational amplifier feedback. However, this method is suitable for systems with low spurious requirements, resulting in poor applicability.

[0005] In order to solve the above problems, it is urgent to provide a charge pump current mismatch calibration method and a calibration circuit thereof. Summary of the invention

[0006] The purpose of the present invention is to propose a charge pump current mismatch calibration method and a calibration circuit thereof, which performs current mismatch calibration by controlling the size of the charge pump charging and discharging current mirror output by a digital counter in cooperation with a digital state machine. The method can calibrate any PLL output frequency in any situation, has strong applicability, and the charge pump current mismatch after calibration is small.

[0007] To achieve this object, the present invention adopts the following technical solutions: A charge pump current mismatch calibration method, comprising: The frequency division module receives the input reference clock and outputs the charge and discharge control signal up pulse signal, dn pulse signal and calibration clock; The calibration clock and the charge and discharge control signals up pulse signal and dn pulse signal are AND-operated through four AND gates and output to the first counting module and the second counting module respectively; The first counting module presets a count overflow value count_num_ctrl<10:0>; When the count of the first counting module is greater than the preset count overflow value count_num_ctrl<10:0>, cal_stop is output, the input of the second counting module is set to 1, and counting stops; The state machine module outputs Idn_ctrl<7:0>, Iup_ctrl<7:0>, cal_done, and cal_fail according to a result of comparing count_num_ctrl<10:0> with the count value C<10:0> of the second counting module.

[0008] As an optional solution, the calibration clock and the charge and discharge control signal up pulse signal and dn pulse signal are ANDed through four AND gates, including: The calibration clock performs AND operation with the up pulse signal and the dn pulse signal respectively and outputs up_calck and dn_calck respectively as counting clocks; up_calck passes through an AND gate and is output to the first counting module for counting, and dn_calck passes through an AND gate and is output to the second counting module for counting.

[0009] As an optional solution, the result of the state machine module comparing count_num_ctrl<10:0> with the count value C<10:0> of the second counting module includes: When the count value of C<10:0> is less than count_num_ctrl<10:0>, the phase difference △T between the up pulse signal and the dn pulse signal is greater than 0, the state machine module controls Idn_ctrl<7:0> to increase, then clear outputs 1, and clears the count value to wait for the next count; After Idn_ctrl<7:0> increases, it waits for the preset time and outputs active=1, starting a new counting cycle; When the count value of C<10:0> is greater than count_num_ctrl<10:0>, the phase difference △T between the up pulse signal and the dn pulse signal is <0, and the state machine controls Iup_ctrl<7:0> to increase.

[0010] As an optional solution, the preset time is a phase-locked loop locking time.

[0011] As an optional solution, the result of the state machine module comparing count_num_ctrl<10:0> with the count value C<10:0> of the second counting module further includes: When the difference between count_num_ctrl<10:0> and C<10:0> is less than the input error value, the calibration is completed and the final values ​​of Iup_ctrl<7:0> and Idn_ctrl<7:0> are output, cal_done=1, cal_fail=0; When the difference between count_num_ctrl<10:0> and C<10:0> is greater than the input error value, the calibration is completed and the final values ​​of Iup_ctrl<7:0> and Idn_ctrl<7:0> are output, cal_done=1, cal_fail=1.

[0012] As an optional solution, the state machine module outputs Idn_ctrl<7:0>, Iup_ctrl<7:0>, cal_done and cal_fail according to the result of comparing count_num_ctrl<10:0> with the count value C<10:0> of the second counting module, and further includes: Adjust the reference clock divider value and the feedback divider value for normal working state.

[0013] As an optional solution, it is characterized in that the frequency division module outputs the charge and discharge control signal up pulse signal, dn pulse signal and the method of calibrating the clock includes: The reference clock divider divides the reference clock to obtain a reference frequency; The frequency and phase detector discriminates the input reference frequency and feedback frequency, and outputs the charge and discharge control signals up pulse signal, dn pulse signal, and reverse signals upb pulse signal, dnb pulse signal; The charge pump converts the charge and discharge control signals up pulse signal, dn pulse signal and reverse signals upb pulse signal, dnb pulse signal into current signals; The low-pass filter converts the current signal into a voltage-controlled oscillator control voltage Vctrl; The voltage-controlled oscillator outputs a clock of a preset frequency; The phase-locked loop feedback frequency divider divides the clock output by the voltage-controlled oscillator; The mismatch calibration divider divides the clock output by the voltage-controlled oscillator in a phase-locked loop locked state to generate the calibration clock.

[0014] A charge pump current mismatch calibration circuit is used to perform the charge pump current mismatch calibration method as described above, and the charge pump current mismatch calibration circuit comprises: A frequency division module is configured to receive an input reference clock and output a charge and discharge control signal up pulse signal, a dn pulse signal and a calibration clock; A calculation module is connected to the frequency division module signal, the calculation module includes four AND gates, and the calibration clock and the charge and discharge control signal up pulse signal and dn pulse signal are AND-operated and output through the four AND gates; A first counting module, connected to the calculation module; A second counting module connected to the calculation module, wherein the first counting module and the second counting module are connected to each other; A state machine module is connected to the first counting module, the second counting module and the calculation module.

[0015] As an optional solution, the frequency division module includes: Reference clock divider; A frequency detector and a phase detector connected to the reference clock divider; A charge pump, connected to the frequency and phase detector signal; A filter connected to the charge pump; A voltage-controlled oscillator connected to the filter; a phase-locked loop feedback divider, two ends of which are respectively connected to the voltage-controlled oscillator and the phase frequency detector, and the phase frequency detector is configured to output a feedback clock to the phase frequency detector; and A calibration frequency divider is connected to the voltage-controlled oscillator, and the calibration frequency divider is configured to output the calibration clock.

[0016] As an optional solution, the calculation module includes: A first AND gate, through which the charge and discharge control signal up pulse signal and the calibration clock are ANDed, and outputs up_calck; A second AND gate, through which the charge and discharge control signal dn pulse signal and the calibration clock are ANDed, and dn_calck, up_calck and dn_calck are output as counting clocks; a third AND gate and a fourth AND gate, an output end of the state machine module is connected to the third AND gate and the fourth AND gate, the up_calck and the output signal of the state machine module are AND-operated through the third AND gate, the output end of the third AND gate is connected to the first counting module, and the dn_calck and the output signal of the state machine module are AND-operated through the fourth AND gate; An OR gate is connected to the fourth AND gate, Cal_stop and dn_calck output by the first counting module and the output signal of the state machine module are AND-operated through the fourth AND gate and then OR-operated through the OR gate, and the output end of the OR gate is connected to the second counting module.

[0017] The beneficial effects of the present invention are: The present invention provides a charge pump current mismatch calibration method and a calibration circuit thereof, comprising: a frequency division module receives an input reference clock, and outputs a charge and discharge control signal up pulse signal, a dn pulse signal and a calibration clock; the calibration clock and the charge and discharge control signal up pulse signal and the dn pulse signal are AND-operated through four AND gates and output to a first counting module and a second counting module respectively; the first counting module presets a count overflow value count_num_ctrl<10:0>; when the count of the first counting module is greater than the preset count overflow value count_num_ctrl<10:0>, cal_stop is output, the input of the second counting module is set to 1, and counting is stopped; and a state machine module outputs Idn_ctrl<7:0>, Iup_ctrl<7:0>, cal_done and cal_fail according to the result of comparing count_num_ctrl<10:0> with the count value C<10:0> of the second counting module. The charge pump current mismatch calibration method performs current mismatch calibration by controlling the size of the charge pump charging and discharging current mirror output by the first counting module and the second counting module in cooperation with the state of the state machine module. The method can calibrate any PLL output frequency in any situation, has strong applicability, and the charge pump current mismatch after calibration is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without paying any creative work.

[0019] Figure 1 is a logic diagram of a charge pump current mismatch calibration method provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of the relationship between the charge pump current mismatch size and the charge and discharge pulse width provided by an embodiment of the present invention; Figure 3 is a schematic structural diagram of a charge pump current mismatch calibration circuit provided by an embodiment of the present invention; Figure 4 is a schematic diagram of the structure of a phase-locked loop provided by an embodiment of the present invention; Figure 5 is a schematic diagram of a charge pump circuit provided by an embodiment of the present invention; Figure 6 Schematic diagram of a charge pump current mismatch calibration circuit provided by an embodiment of the present invention.

[0020] The following are marked in the figure: 100-frequency division module; 110-reference clock frequency divider; 120-frequency detector and phase detector; 130-charge pump; 140-filter; 150-voltage controlled oscillator; 160-phase-locked loop feedback frequency divider; 170-calibration frequency divider; 200-computing module; 300-first counting module; 400-second counting module; 500-State machine module. DETAILED DESCRIPTION

[0021] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only partial structures related to the present invention are shown in the accompanying drawings, rather than the entire structure.

[0022] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the connection of the internal structures of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0024] In the description of this embodiment, the terms "upper", "lower", "left", "right" and other directions or positional relationships are based on the directions or positional relationships shown in the drawings, and are only for the convenience of description and simplification of operation, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operate in a specific direction, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used to distinguish in the description and have no special meaning.

[0025] like Figure 1-Figure 6As shown, this embodiment provides a charge pump 130 current mismatch calibration method, the calibration method comprising: S1, the frequency division module 100 receives the input reference clock and outputs the charge and discharge control signal up pulse signal, dn pulse signal and calibration clock. Specifically, it includes the following steps:

[0026] S11, the reference clock divider 110ref_ck_divider divides the reference clock to obtain a reference frequency. The reference clock input to the reference clock divider 110ref_ck_divider is Refer_ck_in, and the reference frequency output is Ref_ck.

[0027] S12, the phase frequency detector 120PFD performs frequency and phase discrimination on the input reference frequency and feedback frequency, and outputs the charge and discharge control signals up pulse signal, dn pulse signal and the reverse signals upb pulse signal, dnb pulse signal.

[0028] S13, the charge pump 130 converts the result of the phase frequency detector 120PFD, ie, the charge and discharge control signal up pulse signal, dn pulse signal and the reverse signal upb pulse signal, dnb pulse signal of the charge pump 130, into a current signal.

[0029] S14, the low-pass filter 140 converts the current signal into a control voltage Vctrl of the voltage-controlled oscillator 150 VCO. The low-pass filter 140 here is composed of C1, R1 and C2.

[0030] S15, the voltage controlled oscillator 150VCO outputs a clock of a preset frequency; S16, the phase-locked loop PLL feedback divider Divider N divides the clock output by the voltage-controlled oscillator 150VCO; S17, the mismatch calibration divider 170Divider M divides the clock output by the voltage controlled oscillator 150VCO in the PLL locked state to generate a calibration clock cp_cal_ck.

[0031] The charge pump 130 current mismatch calibration method controls the charge and discharge current of the compensation charge pump 130 by detecting the width of the charge and discharge control signal up pulse signal and the dn pulse signal output by the frequency detector 120 when the PLL closed loop is working. The relationship between the charge pump 130 current mismatch size and the charge and discharge pulse width is as follows: Figure 1As shown, when Iup = Idn, the widths of the up pulse signal and the dn pulse signal are the same in the PLL locked state; when Iup < Idn, the width wup of the up pulse signal is required to be > wdn; when Iup > Idn, the width wup of the up pulse signal is required to be < wdn to satisfy a constant Vc in the PLL closed loop. It can be seen that the widths of wup and wdn can characterize the mismatch of the charge pump 130. Therefore, in this embodiment, the charge and discharge currents of the charge pump 130 are calibrated by calibrating the widths of wup and wdn. When the PLL frequency is fixed, calibration can be performed according to the current control voltage Vctrl, so that the current mismatch of the charge pump 130 does not follow the control voltage Vctrl.

[0032] The data in Table 1 reflects the relationship between the phase difference time of the reference clock Tref and the PLL feedback clock and the mismatch of the charge pump 130. It can be seen from the table that the ratio of the phase difference time △t between the reference clock and the PLL feedback clock to the period of the reference clock is equivalent to the current mismatch of the charge pump 130. When the phase difference is 2n, if the reference clock is 2 MHz, then the mismatch of the charge pump 130 is △t / Tref = 2 ns / 500 ns = 0.4%.

[0033] Table 1, Phase difference between the reference clock and the PLL feedback clock corresponding to the charge pump 130 mismatch parameter: To ensure that the standard accuracy is less than 0.4%, and at the same time the mismatch calibration clock of the charge pump 130 cannot be too high in frequency. For example, select a phase difference of 2 ns between the reference clock and the feedback clock, and at this time the corresponding PLL reference clock frequency is 2 MHz.

[0034] According to the locked frequency of the PLL during normal operation, adjust the values of the reference clock divider 110 and the feedback divider to ensure that the output frequency of the PLL in the calibration state is the same as the normal output frequency, that is, the VCO control voltage Vctrl is the same. Adjust the value of the reference clock divider 110 so that it is configured to output 2 MHz according to the value of the reference frequency.

[0035] Configure the calibration clock divider Divider M of the charge pump 130 according to the configured frequency of the VCO so that it outputs a calibration clock CP_cal_ck with a period of 2 ns and a frequency of 500 MHz.

[0036] S2, The calibration clock and the charge and discharge control signals up pulse signal and dn pulse signal are AND-operated through four AND gates and output to the first counting module 300 and the second counting module 400 respectively. The specific steps are as follows:

[0037] S21, the calibration clock performs AND operation with the up pulse signal and the dn pulse signal respectively and outputs up_calck and dn_calck as counting clocks respectively. Since the difference in the number of clocks of up_calck and dn_calck in one up pulse signal cycle and dn pulse signal cycle represents the pulse width of the up pulse signal and the dn pulse signal, the clocks of up_calck and dn_calck can be counted.

[0038] S22, up_calck passes through an AND gate and is output to the first counting module 300 for counting, and dn_calck passes through an AND gate and is output to the second counting module 400 for counting.

[0039] S3 , the first counting module 300 presets a counting overflow value count_num_ctrl<10:0>.

[0040] S4, when the count of the first counting module 300 is greater than the preset count overflow value count_num_ctrl<10:0>, cal_stop is output, the input of the second counting module 400 is set to 1, and counting is stopped.

[0041] S5 , the state machine module 500 outputs Idn_ctrl<7:0>, Iup_ctrl<7:0>, cal_done, and cal_fail according to the result of comparing count_num_ctrl<10:0> with the count value C<10:0> of the second counting module 400 .

[0042] like Figure 2 As shown, when the PLL loop is locked, the current mismatch of the charge pump 130 is equal to the mismatch of the charging and discharging control pulse widths of the up pulse signal and the dn pulse signal output by the PFD, |△T / Tref_ck|=|△Icp / Icp|, and △T=wup-wdn, △Icp=Iup-Idn are defined. Since the PLL is in a locked state and the average value of the VCO control voltage Vctrl is fixed, the PFD will feedback and adjust the output charging and discharging control pulse widths wup and wdn. When △Icp>0, △T<0, and when △Icp<0, △T>0.

[0043] Therefore, adjusting △Icp will affect the pulse widths wup and wdn of the up pulse signal and the dn pulse signal. In this way, the up pulse signal and the dn pulse signal are counted and compared after being operated with a high-speed clock, and then the current mirror size of the charge and discharge current tube of the charge pump 130 is controlled by the state machine output control signal, so that the current mismatch calibration of the charge pump 130 can be realized.

[0044] In the above steps, the charge pump 130 current mismatch calibration method detects the phase difference between the reference clock and the PLL feedback clock by the first counting module 300 and the second technical module counting method, and adjusts the charge pump 130 charging and discharging current by judging the comparison value result of the first counting module 300 and the second technical module to achieve a lower charge pump 130 current mismatch. The method can be applied to systems with high requirements for PLL spurious, such as radio frequency communication, wireless local area network and radar system.

[0045] Therefore, the charge pump 130 current mismatch calibration method performs current mismatch calibration by controlling the size of the charge and discharge current mirror of the output charge pump 130 through the first counting module 300 and the second counting module 400 in cooperation with the state machine module 500. This method can calibrate any PLL output frequency in any situation, has strong applicability, and the current mismatch of the charge pump 130 after calibration is small.

[0046] Specifically, step S5 includes the following steps: S51, when the count value of C<10:0> is less than count_num_ctrl<10:0>, the phase difference △T between the up pulse signal and the dn pulse signal is greater than 0, the state machine module 500 controls Idn_ctrl<7:0> to increase, then clear outputs 1, and clears the count value to wait for the next count; S52, after Idn_ctrl<7:0> increases, it waits for a preset time, outputs active=1, and starts a new counting cycle; S53, when the count value of C<10:0> is greater than count_num_ctrl<10:0>, the phase difference △T<0 between the up pulse signal and the dn pulse signal, and the state machine controls Iup_ctrl<7:0> to increase.

[0047] The preset time is the phase-locked loop locking time.

[0048] S54, when the difference between count_num_ctrl<10:0> and C<10:0> is less than the input error value, the calibration is completed, and the final values ​​of Iup_ctrl<7:0> and Idn_ctrl<7:0> are output, cal_done=1, cal_fail=0; S55, when the difference between count_num_ctrl<10:0> and C<10:0> is greater than the input error value, the calibration is completed, and the final values ​​of Iup_ctrl<7:0> and Idn_ctrl<7:0> are output, cal_done=1, cal_fail=1.

[0049] S6, adjusting the value of the reference clock divider 110 and the value of the feedback divider to a normal working state.

[0050] like Figure 3-Figure 6 As shown, this embodiment also provides a charge pump 130 current mismatch calibration circuit, which is used to perform the charge pump 130 current mismatch calibration method, and the charge pump 130 current mismatch calibration circuit includes a frequency division module 100, a calculation module 200, a first counting module 300, a second counting module 400 and a state machine module 500. The frequency division module 100 is configured to receive an input reference clock and output a charge and discharge control signal up pulse signal, a dn pulse signal and a calibration clock, the calculation module 200 is connected to the frequency division module 100 signal, the calculation module 200 includes four AND gates, the calibration clock and the charge and discharge control signal up pulse signal and dn pulse signal are ANDed through the four AND gates and output, the first counting module 300 is connected to the calculation module 200, the second counting module 400 is connected to the calculation module 200, the first counting module 300 and the second counting module 400 are connected to each other, and the state machine module 500 is connected to the first counting module 300, the second counting module 400 and the calculation module 200. The charge pump 130 current mismatch calibration circuit performs current mismatch calibration by controlling the size of the charge and discharge current mirror of the charge pump 130 in cooperation with the state of the state machine module 500 through the first counting module 300 and the second counting module 400. It can calibrate any PLL output frequency in any situation, has strong applicability, and the current mismatch of the charge pump 130 after calibration is small.

[0051] Further, the phase-locked loop includes a reference clock divider 110, a phase frequency detector 120, a charge pump 130, a filter 140, a voltage-controlled oscillator 150, a phase-locked loop feedback divider 160, and a calibration divider 170. The phase frequency detector 120 is connected to the reference clock divider 110, the charge pump 130 is signal-connected to the phase frequency detector 120, the filter 140 is connected to the charge pump 130, the voltage-controlled oscillator 150 is connected to the filter 140, two ends of the phase-locked loop feedback divider 160 are respectively connected to the voltage-controlled oscillator 150 and the phase frequency detector 120, the phase-locked loop feedback divider 160 is configured to output a feedback clock to the phase frequency detector 120, the calibration divider 170 is connected to the voltage-controlled oscillator 150, and the calibration divider 170 is configured to output a calibration clock. The frequency division module 100 can be calibrated according to the current control voltage Vctrl, so that the current mismatch of the charge pump 130 will not follow the control voltage Vctrl.

[0052] Among them, Figure 5As shown in the circuit diagram of the charge pump 130, the charge pump 130 includes a first NMOS transistor mn1, a second NMOS transistor mn2, a third NMOS transistor mn3, a fourth NMOS transistor mn4<7:0>, a fifth NMOS transistor mn5, a sixth NMOS transistor mn6, a second PMOS transistor mp2, a third PMOS transistor mp3, a fourth PMOS transistor mp4<7:0>, a fifth PMOS transistor mp5, and a sixth PMOS transistor mp6. The gates of the first NMOS transistor mn1 and the second NMOS transistor mn2 are connected and connected to a power source at the same time, the source of the first NMOS transistor mn1 is connected to the power source, the drains of the first NMOS transistor mn1 and the second NMOS transistor mn2 are connected to the ground terminal respectively, and the drain of the second NMOS transistor mn2 is connected to the source of the second PMOS transistor mp2. The drain of the third NMOS tube mn3 is connected to the power supply, the drains of the second PMOS tube mp2 and the third PMOS tube mp3 are connected, and are also connected to the source of the second NMOS tube mn2. The third PMOS tube mp3 forms I up, and its source is connected to the source of the fourth PMOS tube mp4<7:0> and the drain of the fifth PMOS tube mp5. The gate of the fourth PMOS tube mp4<7:0> is connected to the source of the second NMOS tube mn2, the gate of the fifth NMOS tube mn5 receives the up signal, and the source is connected to the source of the fifth NMOS tube mn5. The gate of the fifth NMOS tube mn5 is connected to dnb, and the drain is connected to the source of the third NMOS tube mn3 and the source of the fourth NMOS tube mn4<7:0>. The gate of the third NMOS transistor mn3 and the gate of the fourth NMOS transistor mn4<7:0> are connected to the power supply Iref at the same time, the drain of the third NMOS transistor mn3 and the drain of the fourth NMOS transistor mn4<7:0> are connected to the ground terminal respectively, the third NMOS transistor mn3 forms Idn, and the fourth NMOS transistor mn4<7:0> forms Idn<7:0>. The source of the fifth PMOS transistor mp5 and the source of the fifth NMOS transistor mn5 are connected to the inverter opa1 at the same time. The drain of the sixth PMOS tube mp6 is connected to the drain of the fifth PMOS tube mp5 and the source of the fourth PMOS tube mp4<7:0> at the same time, the gate of the sixth PMOS tube mp6 is connected to upb, the source of the sixth PMOS tube mp6 is connected to the source of the sixth NMOS tube mn6, and is connected to the inverter opa1 at the same time, and outputs Cp_Out, the drain of the sixth NMOS tube mn6 ​​is connected to the drain of the fifth NMOS tube mn5 at the same time, and the drain of the sixth NMOS tube mn6 ​​and the drain of the fifth NMOS tube mn5 are connected to the source of the third NMOS tube mn3 at the same time.

[0053] Compared with the prior art, the charge pump 130 adds a fourth NMOS tube mn4<7:0> and a fourth PMOS tube mp4<7:0> for calibration control as a mismatch calibration structure of the charge pump 130 to achieve charge and discharge control current mirror regulation, such as Figure 5 Circuit diagram of charge pump 130.

[0054] The calculation module 200 includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate and an OR gate. The charge and discharge control signal up pulse signal and the calibration clock are ANDed through the first AND gate, and the up pulse signal _calck is output. The charge and discharge control signal dn pulse signal and the calibration clock are ANDed through the second AND gate, and dn_calck is output. Up_calck and dn_calck are used as counting clocks. An output end of the state machine module 500 is connected to the third AND gate and the fourth AND gate, up_calck and the output signal of the state machine module 500 are ANDed through the third AND gate, the output end of the third AND gate is connected to the first counting module 300, dn_calck and the output signal of the state machine module 500 are ANDed through the fourth AND gate. The OR gate is connected to the fourth AND gate, Cal_stop output by the first counting module 300, dn_calck and the output signal of the state machine module 500 are ANDed through the fourth AND gate, and then ORed through the OR gate 250, and the output end of the OR gate is connected to the second counting module 400.

[0055] In summary, this embodiment performs current mismatch calibration by controlling the size of the charge and discharge current mirror of the output charge pump 130 through the first counting module 300 and the second counting module 400 in cooperation with the state of the state machine module 500, and can calibrate any PLL output frequency in any situation, and has the advantage of strong applicability and small current mismatch of the charge pump 130 after calibration.

[0056] Note that the above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected, and the scope of the present invention to be protected is defined by the attached claims and their equivalents.

Claims

1. A charge pump (130) current mismatch calibration method, characterized in that: include: The frequency division module (100) receives an input reference clock and outputs a charge and discharge control signal up pulse signal, a dn pulse signal and a calibration clock; The calibration clock and the charge and discharge control signals up pulse signal and dn pulse signal are AND-operated through four AND gates and output to the first counting module (300) and the second counting module (400) respectively; The first counting module (300) presets a counting overflow value count_num_ctrl<10:0>; When the count of the first counting module (300) is greater than the preset count overflow value count_num_ctrl<10:0>, cal_stop is output, and the input of the second counting module (400) is set to 1, and counting stops; The state machine module (500) outputs Idn_ctrl<7:0>, Iup_ctrl<7:0>, cal_done and cal_fail according to the result of comparing count_num_ctrl<10:0> with the count value C<10:0> of the second counting module (400).

2. The charge pump (130) current mismatch calibration method according to claim 1, characterized in that: The calibration clock and the charge and discharge control signal up pulse signal and dn pulse signal are operated by four AND gates, including: The calibration clock performs AND operation with the up pulse signal and the dn pulse signal respectively and outputs up_calck and dn_calck respectively as counting clocks; After passing through an AND gate, up_calck is output to a first counting module (300) for counting, and after passing through an AND gate, dn_calck is output to a second counting module (400) for counting.

3. The charge pump (130) current mismatch calibration method according to claim 1, characterized in that: The result of the state machine module (500) comparing count_num_ctrl<10:0> with the count value C<10:0> of the second counting module (400) includes: When the count value of C<10:0> is less than count_num_ctrl<10:0>, the phase difference △T between the up pulse signal and the dn pulse signal is greater than 0, and the state machine module (500) controls Idn_ctrl<7:0> to increase, then clear outputs 1, and clears the count value to wait for the next count; After Idn_ctrl<7:0> increases, it waits for the preset time and outputs active=1 to start a new counting cycle; When the count value of C<10:0> is greater than count_num_ctrl<10:0>, the phase difference △T between the up pulse signal and the dn pulse signal is <0, and the state machine controls Iup_ctrl<7:0> to increase.

4. The charge pump (130) current mismatch calibration method according to claim 3, characterized in that: The preset time is the phase-locked loop locking time.

5. The charge pump (130) current mismatch calibration method according to claim 3, characterized in that: The result of the state machine module (500) comparing count_num_ctrl<10:0> and the count value C<10:0> of the second counting module (400) further includes: When the difference between count_num_ctrl<10:0> and C<10:0> is less than the input error value, the calibration is completed and the final values ​​of Iup_ctrl<7:0> and Idn_ctrl<7:0> are output, cal_done=1, cal_fail=0; When the difference between count_num_ctrl<10:0> and C<10:0> is greater than the input error value, the calibration is completed and the final values ​​of Iup_ctrl<7:0> and Idn_ctrl<7:0> are output, cal_done=1, cal_fail=1.

6. The charge pump (130) current mismatch calibration method according to any one of claims 1 to 5, characterized in that: The state machine module (500) outputs Idn_ctrl<7:0>, Iup_ctrl<7:0>, cal_done and cal_fail according to the result of comparing count_num_ctrl<10:0> with the count value C<10:0> of the second counting module (400), and further includes: Adjust the reference clock divider value and the feedback divider value for normal working state.

7. The charge pump (130) current mismatch calibration method according to any one of claims 1 to 5, characterized in that: The method for the frequency division module (100) to output a charge and discharge control signal up pulse signal, a dn pulse signal and a clock calibration comprises: A reference clock frequency divider (110) divides the reference clock to obtain a reference frequency; The frequency and phase detector (120) performs frequency and phase discrimination on the input reference frequency and feedback frequency, and outputs charge and discharge control signals up pulse signal, dn pulse signal, and reverse signals upb pulse signal, dnb pulse signal; The charge pump (130) converts the charge and discharge control signals up pulse signal, dn pulse signal and reverse signals upb pulse signal, dnb pulse signal into current signals; The low-pass filter (140) converts the current signal into a control voltage Vctrl of a voltage-controlled oscillator (150); The voltage-controlled oscillator (150) outputs a clock of a preset frequency; The phase-locked loop feedback frequency divider (160) divides the frequency of the clock output by the voltage-controlled oscillator (150); The mismatch calibration frequency divider (170) divides the clock output by the voltage-controlled oscillator (150) in a phase-locked loop locked state to generate the calibration clock.

8. A charge pump (130) current mismatch calibration circuit, characterized in that: Used to execute the charge pump (130) current mismatch calibration method according to any one of claims 1 to 7, the charge pump (130) current mismatch calibration circuit comprising: A frequency division module (100) is configured to receive an input reference clock and output a charge and discharge control signal up pulse signal, a dn pulse signal and a calibration clock; A calculation module (200) is signal-connected to the frequency division module (100), the calculation module (200) comprising four AND gates, the calibration clock and the charge and discharge control signal up pulse signal and dn pulse signal being AND-operated and outputted through the four AND gates; A first counting module (300) connected to the calculation module (200); A second counting module (400) connected to the calculation module (200), the first counting module (300) and the second counting module (400) being connected to each other; A state machine module (500) is connected to the first counting module (300), the second counting module (400) and the calculation module (200).

9. The charge pump (130) current mismatch calibration circuit according to claim 8, characterized in that: The frequency division module (100) comprises: ReferenceClockDivider(110); A frequency detector and a phase detector (120), connected to the reference clock divider (110); A charge pump (130) connected to the frequency and phase detector (120) by signal; A filter (140) connected to the charge pump (130); A voltage-controlled oscillator (150) connected to the filter (140); A phase-locked loop feedback divider (160), two ends of which are respectively connected to the voltage-controlled oscillator (150) and the phase frequency detector (120), and the phase frequency detector (120) is configured to output a feedback clock to the phase frequency detector (120); and A calibration frequency divider (170) is connected to the voltage-controlled oscillator (150), and the calibration frequency divider (170) is configured to output the calibration clock.

10. The charge pump (130) current mismatch calibration circuit according to claim 8 or 9, characterized in that: The calculation module (200) comprises: A first AND gate, through which the charge and discharge control signal up pulse signal and the calibration clock are ANDed, and outputs up_calck; A second AND gate, through which the charge and discharge control signal dn pulse signal and the calibration clock are ANDed, and dn_calck, up_calck and dn_calck are output as counting clocks; a third AND gate and a fourth AND gate, an output end of the state machine module (500) is connected to the third AND gate and the fourth AND gate, the up_calck and the output signal of the state machine module (500) are AND-operated through the third AND gate, the output end of the third AND gate is connected to the first counting module (300), and the dn_calck and the output signal of the state machine module (500) are AND-operated through the fourth AND gate; An OR gate is connected to the fourth AND gate, Cal_stop and dn_calck output by the first counting module (300) and the output signal of the state machine module (500) are ANDed through the fourth AND gate and then ORed through the OR gate, and the output end of the OR gate is connected to the second counting module (400).

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