Assembly line analog-to-digital converter, control chip and electronic equipment

Abstract

The invention relates to a pipelined analog-to-digital converter, a control chip and an electronic device, the pipelined analog-to-digital converter comprises a plurality of cascaded pipelined processing units, each pipelined processing unit comprises a sub analog-to-digital converter used for performing analog-to-digital conversion on a received input analog signal to obtain a first digital signal; the digital-to-analog converter is used for performing digital-to-analog conversion on the first digital signal to obtain a first analog signal; the signal processing module is used for performing subtraction operation on the input analog signal and the first analog signal to obtain a residual error signal; the first residual error amplifier and the second residual error amplifier are both used for amplifying residual error signals, the output end of the first residual error amplifier is connected to the digital-to-analog converter of the next-stage pipeline processing unit, and the output end of the second residual error amplifier is connected to the sub-analog-to-digital converter of the next-stage pipeline processing unit. According to the embodiment of the invention, the energy efficiency can be improved, the establishment time can be prolonged, and the energy efficiency of the residual error amplification circuit is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a pipeline analog-to-digital converter, a control chip, and an electronic device. Background Art

[0002] Pipeline ADC is a type of ADC that is suitable for high-speed and high-precision ADC design. Its main applications include wireless communications, radar, etc. Pipeline ADC consists of multiple pipeline stages. Each stage alternately completes the coarse quantization of the signal and the generation and amplification of the residual, and sends the residual to the subsequent stage for further quantization. The core circuit module of the pipeline ADC is the residual generation and amplification circuit, which is usually implemented through a switched capacitor circuit. The speed and accuracy of the residual amplification often determine the overall speed and accuracy of the pipeline ADC. Therefore, how to better achieve the amplification of the residual is a key indicator for improving the performance of the pipeline ADC.

[0003] In the traditional pipeline ADC architecture, each pipeline stage consists of a coarse quantization ADC (usually flash, referred to as flash in the following text, but it can also be other types of coarse quantizers), a capacitor DAC (capacitive digital-to-analog converter) and a residual amplifier. The residual is amplified by a residual amplifier and sent to the next stage capacitor DAC and flash ADC for sampling and coarse quantization.

[0004] This classic structure has two disadvantages:

[0005] First, the capacitor DAC and flash ADC in the later stage are driven by an amplifier, but the requirements for the accuracy of the two are inconsistent. For example, for the first stage of a 14-bit pipeline ADC, assuming that the inter-stage gain is 4, the capacitor voltage of the second stage needs to be established to 12 bits of accuracy. The flash of the second stage only needs to be established to 3-4 bits (usually flash is designed to be 3-4 bits), but it is still driven to 12 bits of accuracy, which results in a large waste of power consumption.

[0006] The second disadvantage is that coarse quantization of flash often produces nonlinear kick-back errors (due to the parasitic capacitance of transistors, the voltage changes of the source and drain of the transistors will in turn affect the gate voltage (usually the input port). The quantizer (comparator) can be regarded as a nonlinear amplifier. The nonlinear amplification in the comparison process will cause interference to the input end, which is called kick-back error).

[0007] The above two shortcomings will be more significant in high-speed applications. Therefore, it is urgent to propose a new analog-to-digital conversion scheme to improve the energy efficiency of residual amplification. Summary of the invention

[0008] According to one aspect of the present disclosure, a pipeline analog-to-digital converter is provided, the pipeline analog-to-digital converter comprising: a plurality of cascaded pipeline processing units, each pipeline processing unit comprising a signal processing module, a sub-analog-to-digital converter, a first residual amplifier, and a second residual amplifier, wherein:

[0009] The sub-analog-to-digital converter is used to perform analog-to-digital conversion on the received input analog signal to obtain a first digital signal;

[0010] The signal processing module is used to perform digital-to-analog conversion on the first digital signal to obtain a first analog signal;

[0011] The signal processing module is used to perform a subtraction operation on the input analog signal and the first analog signal to obtain a residual signal;

[0012] The first residual amplifier and the second residual amplifier are both used to amplify the residual signal, the output end of the first residual amplifier is connected to the signal processing module of the next stage pipeline processing unit, and the output end of the second residual amplifier is connected to the sub-analog-to-digital converter of the next stage pipeline processing unit.

[0013] The size of the first residual amplifier is larger than that of the second residual amplifier, and the bandwidth of the first residual amplifier is larger than that of the second residual amplifier.

[0014] The first digital signal output by the sub-analog-to-digital converter in each pipeline processing unit serves as the analog-to-digital conversion result of the input analog signal.

[0015] In a possible implementation manner, a bandwidth ratio of the first residual amplifier to that of the second residual amplifier is: a precision ratio of the first residual amplifier to that of the second residual amplifier.

[0016] In a possible implementation manner, the size ratio of the first residual amplifier to the second residual amplifier is: the product of the bandwidth ratio and the load ratio of the first residual amplifier to the second residual amplifier.

[0017] In a possible implementation, each pipeline processing unit is configured to perform sampling, quantization, and residual transfer operations based on a target clock signal, wherein the target clock signal is set to a first phase and a second phase that periodically alternate, wherein:

[0018] In the first phase, the Nth stage pipeline processing unit samples the received signal to obtain a sampled signal, quantizes the signal using the sub-analog-to-digital converter to obtain a quantization result, and obtains a residual signal using the signal processing module, wherein N is a positive integer;

[0019] In the second phase, the Nth stage pipeline processing unit uses the first residual amplifier and the second residual amplifier to amplify the residual signal, and transmits the amplified residual signal to the signal processing module and the sub-analog-to-digital converter of the N+1th stage pipeline processing unit respectively.

[0020] In a possible implementation manner, in the first sub-phase of the second phase, in the first sub-phase of the second phase, the Nth stage pipeline processing unit transmits the residue signal amplified by the first residue amplifier and the second residue amplifier to the signal processing module and the sub-analog-to-digital converter of the N+1th stage pipeline processing unit respectively;

[0021] In the second sub-phase of the second phase, the sub-analog-to-digital converter of the N+1th stage pipeline processing unit performs analog-to-digital conversion on the amplified residual signal transmitted from the second residual amplifier of the Nth stage pipeline processing unit,

[0022] In the second sub-phase of the second phase, the first residual amplifier of the Nth stage pipeline processing unit continues to transmit the amplified residual signal.

[0023] The start time of the first sub-phase is earlier than the start time of the second sub-phase.

[0024] In a possible implementation manner, an interstage switch is provided between the first residual amplifier and the signal processing module of the next stage pipeline processing unit.

[0025] The inter-stage switches of the N-th stage pipeline processing unit are turned on during the second phase.

[0026] In a possible implementation, the sub-analog-to-digital converter includes a flash analog-to-digital converter, and the signal processing module includes a capacitive digital-to-analog converter.

[0027] According to one aspect of the present disclosure, a control chip is provided, wherein the control chip includes the pipeline analog-to-digital converter.

[0028] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the control chip.

[0029] In a possible implementation, the electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, and an access control device.

[0030] In the embodiment of the present disclosure, the size of the first residue amplifier is set to be larger than the size of the second residue amplifier, the bandwidth of the first residue amplifier is set to be larger than the bandwidth of the second residue amplifier, the first residue amplifier and the second residue amplifier are used to amplify the residue signal respectively, and the corresponding amplified residue signals are used to drive the signal processing module and the sub-analog-to-digital converter of the next stage respectively, so as to achieve energy efficiency improvement and extension of the settling time, thereby improving the energy efficiency of the residue amplifier circuit.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0033] Figure 1a A schematic diagram of a pipelined analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0034] Figure 1b A schematic diagram of a pipeline processing unit according to an embodiment of the present disclosure is shown.

[0035] Figure 2 A schematic diagram of the operation timing of the pipeline analog-to-digital converter of an embodiment of the present disclosure under a target clock signal is shown.

[0036] Figure 3 The pipeline processing unit 10 in the pipeline analog-to-digital converter according to the embodiment of the present disclosure is shown in the second phase Schematic diagram of residual error transfer. DETAILED DESCRIPTION

[0037] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0038] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0040] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0041] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0042] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0043] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0044] See also Figure 1a, Figure 1a A schematic diagram of a pipelined analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0045] like Figure 1a As shown, the pipeline analog-to-digital converter includes: a plurality of cascaded pipeline processing units 10, each pipeline processing unit 10 includes a signal processing module 110, a sub-analog-to-digital converter 120, a first residual amplifier 140, and a second residual amplifier 150, wherein:

[0046] The sub-analog-to-digital converter 120 is used to perform analog-to-digital conversion on the received input analog signal to obtain a first digital signal;

[0047] The signal processing module 110 is used to perform digital-to-analog conversion on the first digital signal to obtain a first analog signal;

[0048] The signal processing module 110 is used to perform a subtraction operation on the input analog signal and the first analog signal to obtain a residual signal (V res1 );

[0049] The first residual amplifier 140 and the second residual amplifier 150 are both used to amplify the residual signal. The output end of the first residual amplifier 140 is connected to the signal processing module 110 of the next-stage pipeline processing unit 10, and the output end of the second residual amplifier 150 is connected to the sub-analog-to-digital converter 120 of the next-stage pipeline processing unit 10.

[0050] The size of the first residual amplifier 140 is greater than that of the second residual amplifier 150 , and the bandwidth of the first residual amplifier 140 is greater than that of the second residual amplifier 150 .

[0051] The first digital signal (D n ~D1, n is a positive integer representing the accuracy of the analog-to-digital converter) as the analog-to-digital conversion result of the input analog signal.

[0052] The size of the residual amplifier in the embodiment of the present disclosure may refer to the size of each transistor forming the residual amplifier.

[0053] In the embodiment of the present disclosure, the size of the first residual amplifier 140 is set to be larger than the size of the second residual amplifier 150, the bandwidth of the first residual amplifier 140 is set to be larger than the bandwidth of the second residual amplifier 150, the first residual amplifier 140 and the second residual amplifier 150 are used to amplify the residual signal respectively, and the corresponding amplified residual signal is used to drive the next-stage signal processing module 110 and the sub-analog-to-digital converter 120 respectively, so as to improve the energy efficiency of the residual amplifier circuit.

[0054] The embodiment of the present disclosure does not limit the specific number of cascaded pipeline processing units 10, and those skilled in the art may set it according to actual conditions and needs. For example, the corresponding number of stages may be configured according to the accuracy of analog-to-digital conversion.

[0055] The embodiments of the present disclosure do not limit the specific implementation of the signal processing module 110, the sub-analog-to-digital converter 120, the first residual amplifier 140, and the second residual amplifier 150. Those skilled in the art may implement them using relevant technologies according to actual conditions and needs.

[0056] Exemplarily, the sub-analog-to-digital converter 120 may include a coarse quantizer such as a flash analog-to-digital converter, and the first residual amplifier 140 and the second residual amplifier 150 may both be implemented based on operational amplifiers, as long as the size of the first residual amplifier 140 is larger than the size of the second residual amplifier 150, and the bandwidth of the first residual amplifier 140 is larger than the bandwidth of the second residual amplifier 150.

[0057] Exemplarily, the signal processing module 110 can be implemented by a capacitive digital-to-analog converter (CDAC). Since the capacitive digital-to-analog converter is formed by a capacitor array, it can sample the analog voltage signal and perform a difference between the sampled signal and the first analog signal to obtain a residual signal. Of course, the signal processing module 110 can also be implemented in other ways, which are exemplarily introduced below.

[0058] See also Figure 1b , Figure 1b A schematic diagram of a pipeline processing unit according to an embodiment of the present disclosure is shown.

[0059] For example, Figure 1b As shown, the signal processing module 110 can be implemented by a capacitive digital-to-analog converter CDAC as well as a sampling circuit 1100, a common digital-to-analog converter 1110 and a subtractor 1120. The sampling circuit 1100 samples the input signal and transmits it to the subtractor. The digital-to-analog converter 1110 performs digital-to-analog conversion of the first digital signal to obtain a first analog signal, and transmits it to the subtractor 1120. The subtractor 1120 performs a subtraction operation between the sampling signal and the first analog signal to obtain a residual signal.

[0060] Of course, the embodiments of the present disclosure do not limit the specific implementation of the sampling circuit 1100, the digital-to-analog converter 1110 and the subtractor 1120, and those skilled in the art may implement them using relevant technologies according to actual conditions and needs.

[0062] As an example, the signal processing module 110 can, on the one hand, sample the input signal (wherein the input signal of the first-stage pipeline processing unit is an analog signal that needs to be converted into analog-to-digital, and the input signal of the remaining pipeline processing units is the residual signal amplified by the first residual amplifier 140 of the previous stage) to obtain a sampled signal; on the other hand, the signal processing module 110 can perform digital-to-analog conversion on the first digital signal output by the sub-analog-to-digital converter 120 to obtain a first analog signal, and can also perform a subtraction operation between the sampled signal and the first analog signal to obtain a residual signal. The embodiments of the present disclosure do not limit the specific implementation methods and working processes of sampling, quantization, and generating residuals, and those skilled in the art can refer to relevant technical implementations according to actual conditions and needs.

[0063] In a possible implementation manner, the bandwidth ratio of the first residual amplifier 140 to the bandwidth ratio of the second residual amplifier 150 may be: the accuracy ratio of the first residual amplifier 140 to the accuracy ratio of the second residual amplifier 150 .

[0064] In a possible implementation manner, the size ratio of the first residue amplifier 140 to the second residue amplifier 150 may be: the product of the bandwidth ratio and the load ratio of the first residue amplifier 140 to the second residue amplifier 150 .

[0065] By setting the bandwidth of the first residual amplifier 140 and the second residual amplifier 150 , the embodiment of the present disclosure can establish the two paths where the first residual amplifier 140 and the second residual amplifier 150 are located to appropriate precision, thereby maximizing energy efficiency.

[0066] In the disclosed embodiment, the first residual amplifier 140 (main amplifier) ​​driving the signal processing module 110 of the next-stage pipeline processing unit has a larger size and a higher bandwidth, and can establish a higher precision. The second residual amplifier 150 (auxiliary amplifier) ​​driving the sub-ADC 120 has a smaller size and a lower bandwidth, and only needs to drive the sub-ADC 120 to the required minimum precision.

[0067] Of course, the accuracy of the first residual amplifier 140 and the second residual amplifier 150 can be adaptively set according to actual conditions and needs, and the embodiments of the present disclosure are not limited to this. For example, the accuracy of the first residual amplifier 140 and the second residual amplifier 150 can be configured according to the accuracy of the analog-to-digital converter.

[0068] For example, for a pipeline ADC with 14-bit precision, assuming that the quantization precision of each stage is 3 bits and the inter-stage gain is 4, the main amplifier (the first residual amplifier 140) needs to be established to 12-bit precision, while the auxiliary amplifier (the second residual amplifier 150) only needs to be established to 3-bit precision, then the bandwidth of the auxiliary amplifier only needs to be set to 1 / 4 of the main amplifier (bandwidth ratio = precision ratio).

[0069] For example, assuming that the capacitive load of the two paths (the paths where the first residual amplifier 140 and the second residual amplifier 150 are located) is 1 / 2 of that of the main path, then the size of the auxiliary amplifier only needs to be 1 / 8 of that of the first residual amplifier 140 (size ratio = bandwidth ratio * load ratio). Of course, the specific load size is set according to actual conditions and needs, and the embodiments of the present disclosure do not limit this.

[0070] For example, for the traditional method using one amplifier, the output of the error amplifier is directly connected to the digital-to-analog converter and the sub-analog-to-digital converter of the next-stage pipeline processing unit. In the traditional method, both paths (the two paths from the error amplifier to the digital-to-analog converter and the sub-analog-to-digital converter) are established to 12 bits of accuracy, which is equivalent to the size of the auxiliary amplifier being 1 / 2 of the main amplifier (the bandwidth is the same, and the size ratio is the load ratio). However, by adopting the technical solution of the embodiment of the present disclosure, the size of the auxiliary amplifier can be significantly reduced. For example, in one example, the total size can be reduced from 1.5 to 1.125, thereby significantly improving energy efficiency.

[0071] It is worth mentioning that in the pipeline analog-to-digital converter of the embodiment of the present disclosure, the mismatch between the two amplifiers of the current-stage pipeline processing unit 10 can be absorbed by the inter-stage redundancy of the subsequent-stage pipeline processing unit 10, and will not affect the performance of the pipeline ADC.

[0072] In addition, due to the use of dual-path amplification, there is isolation between the kickback error of the sub-ADC 120 and the input of the capacitor, so it will not affect the sampling accuracy. Therefore, the sampling time of the capacitor DAC path (the first residual amplifier 140 of the Nth stage to the signal processing module 110 of the N+1th stage) of the N+1th pipeline processing unit 10 can be postponed until the Flash ADC path (the second residual amplifier 150 of the Nth stage to the sub-ADC 120 of the N+1th stage) is activated, which further prolongs the settling time and improves the settling accuracy.

[0073] Among them, the mismatch between the two amplifiers causes the signal seen by the coarse quantizer (sub-analog-to-digital converter 120) of the subsequent pipeline processing unit 10 to be inconsistent with the signal sampled by the sampling capacitor in the signal processing module 110. This difference will cause the signal to not be correctly quantized, and thus make the actual conversion residual range larger than the ideal residual range. Generally speaking, the residual range that the pipeline processing unit 10 can produce will be larger than the ideal residual range (usually 2 times or 4 times larger, corresponding to 1 bit or 2 bits of redundancy). Therefore, as long as the expansion of the residual range caused by the above mismatch does not exceed the redundant range, it will not affect the subsequent conversion.

[0074] The working mode of the pipeline analog-to-digital converter is exemplarily introduced below.

[0075] See also Figure 2 , Figure 2 A schematic diagram of the operation timing of the pipeline analog-to-digital converter of an embodiment of the present disclosure under a target clock signal is shown.

[0076] For example, Figure 2 As shown, the target clock signal is set to the first phase Second Phase In the form of periodic alternation, different phases can correspond to different control signals to control the operation of corresponding components. For example, in the first phase The first control signal is at a high level and the second control signal is at a low level. The first control signal controls the corresponding component to perform sampling and quantization operations. In the second phase The second control signal is at a high level and the first control signal is at a low level. The second control signal controls the corresponding components to perform residual amplification and residual transmission operations. Of course, the received signal can also be sampled and quantized at the same time.

[0077] In a possible implementation, each stage of the pipeline processing unit 10 is configured to perform sampling, quantization, and residue transfer operations based on a target clock signal.

[0078] For example, Figure 1a and Figure 2 As shown, in the first phase The Nth stage pipeline processing unit 10 samples the received signal to obtain a sampling signal (such as a sampling capacitor in the digital-to-analog converter 1110), uses the sub-analog-to-digital converter 120 to quantize the signal to obtain a quantization result, and uses the signal processing module to obtain a residual signal (V res1 ), where N is a positive integer;

[0079] In the second phase, the Nth stage pipeline processing unit 10 uses the first residual amplifier 140 and the second residual amplifier 150 to amplify the residual signal, and transmits the amplified residual signal to the signal processing module 110 and the sub-analog-to-digital converter 120 of the N+1th stage pipeline processing unit 10 respectively.

[0080] Figure 2 Taking N as 1 as an example, the first-level pipeline processing unit and the second-level pipeline processing unit are introduced. Figure 2 As shown, in the first phase The signal processing module 110 of the first-stage pipeline processing unit samples the received signal to obtain a sampled signal, quantizes the signal using the sub-ADC 120 to obtain a quantized result, and obtains a residual signal (V res1 ), in the second phase The first stage pipeline processing unit uses the first residual amplifier 140 and the second residual amplifier 150 to amplify the residual signal, and transmits the amplified residual signal to the signal processing module 110 and the sub-analog-to-digital converter 120 of the second stage pipeline processing unit respectively. At this time (in the second phase ), the signal processing module 110 of the second-stage pipeline processing unit 10 samples the residual signal received from the first-stage pipeline processing unit 10 to obtain a sampling signal, quantizes the signal using the sub-analog-to-digital converter 120 to obtain a quantization result, and obtains the residual signal of the second-stage pipeline processing unit 10 using the signal processing module 110.

[0081] In the embodiment of the present disclosure, the first phase Second Phase The specific duration of is not limited, for example, the first phase Second Phase The duration can be equal.

[0082] The disclosed embodiments do not limit the generation method of control signals such as the target clock signal, the first control signal, and the second control signal. For example, the pipeline analog-to-digital converter may include a control module, which generates a corresponding target clock signal through the control module and controls each component of the pipeline analog-to-digital converter to work in a corresponding phase. For example, the control module may include a processing component. In one example, the processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller having an execution instruction function in an electronic device. The processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Inside the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0083] The disclosed embodiment can be in the second phase The amplified residual signals generated by the first residual amplifier 140 and the second residual amplifier 150 are transmitted respectively in different sub-phases to isolate the sampling and amplification operations of the next-stage pipeline processing unit 10, avoid the interference of the quantization operation on the sampling operation, and improve the signal establishment accuracy.

[0084] See also Figure 3 , Figure 3 The pipeline processing unit 10 in the pipeline analog-to-digital converter according to the embodiment of the present disclosure is shown in the second phase Schematic diagram of residual error transfer.

[0085] In a possible implementation, Figure 2 and Figure 3 As shown, in the second phase The first sub-phase The Nth stage pipeline processing unit 10 transmits the residual signals amplified by the first residual amplifier 140 and the second residual amplifier 150 to the signal processing module 110 and the sub-analog-to-digital converter 120 of the N+1th stage pipeline processing unit 10 respectively;

[0086] In the second phase The second sub-phase The sub-ADC 120 of the N+1th stage pipeline processing unit 10 performs analog-to-digital conversion on the amplified residual signal transmitted from the second residual amplifier 150 of the Nth stage pipeline processing unit.

[0087] Among them, in the second phase The second sub-phase The first residual amplifier 140 of the Nth stage pipeline processing unit continues to transmit the amplified residual signal.

[0088] Among them, the first sub-phase The start time is earlier than the second sub-phase The start time of the

[0089] In the embodiment of the present disclosure, the first sub-phase The second sub-phase There is no limit on the end time, as long as the second phase The end time of the second sub-phase The end time of the second phase The end time of the first sub-phase The end time can be in the second sub-phase The start time of the second sub-phase That is, the embodiment of the present disclosure can adjust the first sub-phase according to the needs. The effective time length is controlled to improve the sampling accuracy, that is, the embodiment of the present disclosure has the flexibility of adjustable extension time, such as Figure 3 As shown, by setting the first sub-phase The end time can be in the second sub-phase The start time of the second sub-phase The embodiment of the present disclosure can adjust the voltage (V in,c 、V in,f )The error is controlled within the tolerable error and has high accuracy.

[0090] As an example, the first sub-phase The end time of the second sub-phase The start time to the second phase At any time between the end time and the end time (including the boundary), the second sub-phase The end time of the second phase The end time of .

[0091] Exemplarily, as mentioned above, in the first phase In the second phase, the Nth pipeline processing unit 10 samples and quantizes the signal. The residual is amplified in the second phase and passed to the N+1th pipeline processing unit 10. The N+1th pipeline processing unit 10 also needs to The sampling and quantization operations of the residual signal of the Nth stage pipeline processing unit 10 are completed within the time period. Figure 3 As shown, the first sub-phase Indicates that the N+1th stage pipeline processing unit 10 is in the second phase The residual signal of the Nth stage pipeline processing unit 10 is sampled (the sampling capacitor C in the signal processing module 110 S ) phase period, the second sub-phase Indicates that the N+1th stage pipeline processing unit 10 is in the second phase The phase period for performing the quantization operation on the residual signal of the Nth stage pipeline processing unit 10. Then in the next first phase The stage transmits the residual signal of the N+1th stage pipeline processing unit 10 to the N+2th stage pipeline processing unit 10.

[0092] For the traditional method, since the next-level signal processing module 110 and the sub-analog-to-digital converter 120 are driven by an error amplifier, the two paths are connected together. In order to avoid the interference of quantization on sampling, the related technology must first end the sampling and then perform quantization. The dual-path amplification structure proposed in the embodiment of the present disclosure isolates the two operations, so sampling can be performed later. The longer the sampling time, the higher the signal establishment accuracy. Therefore, the embodiment of the present disclosure can further improve the establishment accuracy.

[0093] In a possible implementation manner, an interstage switch is provided between the first residual amplifier 140 and the signal processing module 110 of the next stage pipeline processing unit 10.

[0094] The interstage switch of the Nth stage pipeline processing unit 10 is turned on during the second phase. Thus, in the second sub-phase of the second phase, when the sub-analog-to-digital converter of the N+1th stage pipeline processing unit performs analog-to-digital conversion on the amplified residual signal transmitted from the second residual amplifier of the Nth stage pipeline processing unit, the first residual amplifier of the Nth stage pipeline processing unit can continue to transmit the amplified residual signal, which can be free from the interference of the sub-analog-to-digital converter, so that the signal can be transmitted for a longer time.

[0095] The embodiments of the present disclosure do not limit the specific type of the interstage switch, and those skilled in the art can select suitable devices as needed. For example, the interstage switch can include any one of a relay, a reed switch, a thyristor, a switching diode, a switching transistor, an electronic bidirectional switch, a photocoupler, a transistor, etc. The transistor can be a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), wherein the transistor can be based on silicon carbide SiC or gallium nitride GaN to improve performance.

[0096] The pipeline analog-to-digital converter of the disclosed embodiment has two main advantages:

[0097] 1. Improved the energy efficiency of the residual amplifier circuit.

[0098] 2. The kick-back error of the sub-quantizer and the main signal path is solved, thereby further extending the settling time and improving the settling accuracy.

[0099] According to one aspect of the present disclosure, a control chip is provided, wherein the control chip includes the pipeline analog-to-digital converter.

[0100] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the control chip.

[0101] In a possible implementation, the electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, and an access control device.

[0102] Of course, the electronic device may also be a terminal device, and the terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device or a vehicle-mounted device, etc. For example, some examples of terminals are: mobile phones, tablet computers, laptop computers, PDAs, mobile Internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control (Industrial Control), wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids (Smart Grid), wireless terminals in transportation safety (Transportation Safety), wireless terminals in smart cities (Smart City), wireless terminals in smart homes (Smart Home), wireless terminals in Internet of Vehicles, etc. For example, the server may be a local server or a cloud server.

[0103] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A pipeline analog-to-digital converter, characterized in that: The pipeline analog-to-digital converter comprises: a plurality of cascaded pipeline processing units, each of which comprises a signal processing module, a sub-analog-to-digital converter, a first residual amplifier, and a second residual amplifier, wherein: The sub-analog-to-digital converter is used to perform analog-to-digital conversion on the received input analog signal to obtain a first digital signal; The signal processing module is used to perform digital-to-analog conversion on the first digital signal to obtain a first analog signal; The signal processing module is further used to perform a subtraction operation on the input analog signal and the first analog signal to obtain a residual signal; The first residual amplifier and the second residual amplifier are both used to amplify the residual signal, the output end of the first residual amplifier is connected to the signal processing module of the next stage pipeline processing unit, and the output end of the second residual amplifier is connected to the sub-analog-to-digital converter of the next stage pipeline processing unit. The size of the first residual amplifier is larger than that of the second residual amplifier, and the bandwidth of the first residual amplifier is larger than that of the second residual amplifier. The first digital signal output by the sub-analog-to-digital converter in each pipeline processing unit serves as the analog-to-digital conversion result of the input analog signal.

2. The pipeline analog-to-digital converter according to claim 1, characterized in that: The ratio of the bandwidths of the first residual amplifier to that of the second residual amplifier is: the ratio of the precisions of the first residual amplifier to that of the second residual amplifier.

3. The pipeline analog-to-digital converter according to claim 1 or 2, characterized in that: The size ratio of the first residual amplifier to the second residual amplifier is: the product of the bandwidth ratio of the first residual amplifier to the second residual amplifier and the load ratio.

4. The pipeline analog-to-digital converter according to claim 1, characterized in that: Each stage of the pipeline processing unit is configured to perform sampling, quantization and residual transfer operations based on a target clock signal, wherein the target clock signal is set to a form of periodic alternation of a first phase and a second phase, wherein: In the first phase, the Nth stage pipeline processing unit samples the received signal to obtain a sampled signal, quantizes the signal using the sub-analog-to-digital converter to obtain a quantization result, and obtains a residual signal using the signal processing module, wherein N is a positive integer; In the second phase, the Nth stage pipeline processing unit uses the first residual amplifier and the second residual amplifier to amplify the residual signal, and transmits the amplified residual signal to the signal processing module and the sub-analog-to-digital converter of the N+1th stage pipeline processing unit respectively.

5. The pipeline analog-to-digital converter according to claim 4, characterized in that: In the first sub-phase of the second phase, the Nth stage pipeline processing unit transmits the residue signals amplified by the first residue amplifier and the second residue amplifier to the signal processing module and the sub-analog-to-digital converter of the N+1th stage pipeline processing unit respectively; In the second sub-phase of the second phase, the sub-analog-to-digital converter of the N+1th stage pipeline processing unit performs analog-to-digital conversion on the amplified residual signal transmitted from the second residual amplifier of the Nth stage pipeline processing unit, In the second sub-phase of the second phase, the first residual amplifier of the Nth stage pipeline processing unit continues to transmit the amplified residual signal. The start time of the first sub-phase is earlier than the start time of the second sub-phase.

6. The pipeline analog-to-digital converter according to claim 5, characterized in that: An interstage switch is provided between the first residual amplifier and the signal processing module of the next stage pipeline processing unit. The inter-stage switches of the N-th stage pipeline processing unit are turned on during the second phase.

7. The pipeline analog-to-digital converter according to claim 1, characterized in that: The sub-analog-to-digital converter includes a flash analog-to-digital converter, and the signal processing module includes a capacitive digital-to-analog converter.

8. A control chip, characterized in that: The control chip comprises a pipeline analog-to-digital converter as described in any one of claims 1-7.

9. An electronic device, characterized in that: The electronic device comprises the control chip as claimed in claim 8.

10. The electronic device according to claim 9, characterized in that: The electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, and an access control device.

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