Delta-Sigma modulator adopting three-level quantization

Abstract

The invention discloses a Delta-Sigma modulator adopting three-level quantization, and the Delta-Sigma modulator comprises a first-stage integrator circuit, a second-stage integrator circuit, an analog adder, a three-level quantizer, a reference voltage feedback circuit, and a digital control signal generation circuit used for overall time sequence control, the first-stage integrator circuit is used for carrying out sampling integration on an input signal to obtain a primary integration result; the second-stage integrator circuit is used for carrying out sampling integration on the primary integration result to obtain a secondary integration result; the analog adder is used for summing the primary integration result and the secondary integration result, and obtaining a summing result at a summing node; the three-level quantizer is used for carrying out 1.5 bit quantization on the summation result to obtain an output result QAQBQC; and the reference voltage feedback circuit is used for carrying out (VREFP-VREFN), 0 and-(VREFP-VREFN) three-level feedback on the first-stage integrator circuit according to the output result QAQBQC. According to the Delta-Sigma modulator disclosed by the invention, higher precision can be realized.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a Delta-Sigma modulator using three-level quantization. Background Art

[0002] Analog-to-digital converter (ADC) is the bridge between the analog world and the digital world. There are many technical routes for ADC. The most common classification method is to classify according to the relationship between sampling rate and signal bandwidth. It can be divided into two categories: Nyquist rate ADC and oversampling ADC. The sampling frequency of oversampling ADC is much greater than twice the signal bandwidth, mainly Sigma-Delta ADC. Compared with Nyquist rate ADC, the technologies used by Sigma-Delta ADC are: oversampling technology (Over sampling), noise shaping technology and digital filtering technology. The analog-to-digital converter based on the Sigma Delta modulation principle is a typical example. It relies on oversampling and noise shaping technology to modulate and suppress the noise power in the signal frequency band, and the digital extraction filter completes the extraction of redundant data and the suppression of noise at high frequencies. It is precisely because of this technical feature that Sigma-Delta ADC has achieved an accuracy of more than 16 bits that is difficult to achieve with traditional ADCs.

[0003] Delta-SigmaADC achieves higher accuracy with lower design complexity and has good compatibility with digital CMOS processes, making it very suitable for use in mixed-signal CMOS circuits.

[0004] With the above advantages, Sigma-Delta ADC occupies an important position in the field of high-precision ADC and is widely used in bridge sensors, four-corner balance weighing, pressure detection, industrial control, chemical analysis and other fields. Therefore, the design of high-precision and high-performance Sigma-Delta ADC has important scientific research value and engineering significance.

[0005] At present, in the design of Delta-Sigma ADC, the commonly used quantizers are generally single-bit quantization and multi-bit quantization. However, single-bit quantization uses a comparator to feedback high and low reference voltages according to the high and low levels of the comparator output. The quantization accuracy obtained by this two-level quantization method is limited; multi-bit quantization, that is, the quantizer uses multi-bit quantization, and the feedback circuit performs multiple voltage feedback according to the quantization result. This multi-level feedback can achieve higher accuracy, but the matching requirements between multi-level quantization components are high. The mismatch between components will introduce distortion, and complex digital calibration technology needs to be introduced to solve the mismatch problem between components, which requires additional overhead. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a Delta-Sigma modulator using three-level quantization to solve the above-mentioned problems.

[0007] According to the present invention, a Delta-Sigma modulator using three-level quantization is provided, comprising a first-stage integrator circuit, a second-stage integrator circuit, an analog adder, a three-level quantizer, a reference voltage feedback circuit, and a digital control signal generating circuit for overall timing control, wherein the first-stage integrator circuit is used to sample and integrate an input signal to obtain a primary integration result; the second-stage integrator circuit is used to sample and integrate the primary integration result to obtain a secondary integration result; the analog adder is used to sum the primary integration result and the secondary integration result to obtain a summation result at a summation node; the three-level quantizer is used to perform 1.5-bit quantization on the summation result to obtain an output result Q A Q B Q C The reference voltage feedback circuit is used to output the result Q A Q B Q C , a three-level feedback of (VREFP-VREFN), 0, -(VREFP-VREFN) is performed on the first-stage integrator circuit, wherein VREFP and VREFN are respectively the positive and negative terminal levels of the reference voltage.

[0008] In one embodiment, the first stage integrator circuit oversamples and integrates the input signal at a frequency CK; and the second stage integrator circuit samples and integrates the one-time integration result at a frequency CK or CK / 2, wherein CK is a clock signal frequency.

[0009] In one embodiment, the first-stage integrator circuit includes bootstrap switches S1 to S18, first sampling capacitors Cs1-P and Cs1-N, first integrating capacitors Ci1-P and Ci1-N, and a first operational amplifier OTA1, wherein the left ends of S1 and S2 are connected to the positive input signal VIP input terminal, the left ends of S3 and S4 are connected to the negative input signal VIN input terminal, the right ends of S1 and S3 are connected to one end of S5 and the left plate of Cs1-P, the right ends of S2 and S4 are connected to one end of S6 and the left plate of Cs1-N, and the other ends of S5 and S6 are commonly connected to the common mode level Vcm; one end of S7 is connected to one end of S9 and the right plate of Cs1-P, one end of S8 is connected to one end of S10 and the right plate of Cs1-N, and the other ends of S7 and S8 are connected to the common mode level Vcm. One end is commonly connected to the common mode level Vcm; the other end of S9 is directly connected to the positive input terminal of OTA1, and the other end of S10 is directly connected to the negative input terminal of OTA1; the left pole plate of Ci1-P is connected to one end of S11 and S12, the left pole plate of Ci1-N is connected to one end of S13 and S14, the other ends of S11 and S13 are connected together and commonly connected to the positive input terminal of OTA1, and the other ends of S12 and S14 are connected together and commonly connected to the negative input terminal of OTA1; the right pole plate of Ci1-P is connected to one end of S15 and S17, the right pole plate of Ci1-N is connected to one end of S16 and S18, the other ends of S15 and S16 are connected to the negative output terminal of OTA1, and the other ends of S17 and S18 are connected to the positive output terminal of OTA1.

[0010] In one embodiment, the capacitance ratio of the first sampling capacitor to the first integrating capacitor is 1:10.

[0011] In one embodiment, the second stage integrator circuit includes CMOS switches S19 to S26, second sampling capacitors Cs2-P and Cs2-N, second integrating capacitors Ci2-P and Ci2-N, and a second operational amplifier OTA2, wherein the left end of S9 is connected to the right ends of S15 and S17 and the right plate of Ci1-P, the left end of S20 is connected to the right ends of S16 and S18 and the right plate of Ci1-N, the right end of S9 is connected to one end of S21 and the left plate of Cs2-P, the right end of S20 is connected to one end of S22 and the left plate of Cs2-N, and the left end of S21 and S22 is connected to the left plate of The other end is commonly connected to the common mode level Vcm; one end of S25 is connected to one end of S23 and the right plate of Cs2-P, one end of S26 is connected to one end of S24 and the right plate of the sampling capacitor Cs2-N, and the other ends of S23 and S24 are commonly connected to the common mode level Vcm; the other end of S25 is directly connected to the positive input terminal of OTA2 and the left plate of Ci2-P, and the other end of S26 is directly connected to the negative input terminal of OTA2 and the left plate of Ci2-N; the right plate of Ci2-P is connected to the negative output terminal of OTA2, and the right plate of Ci2-N is connected to the positive output terminal of OTA2.

[0012] In one embodiment, the capacitance ratio of the second sampling capacitor to the second integrating capacitor is 1:4.

[0013] In one embodiment, the analog adder includes summing capacitors Cadder1-P, Cadder1-N, Cadder2-P and Cadder2-N and CMOS switches S27 to S36, wherein the left end of S27 is connected to the right ends of S15 and S17 and the right plate of Ci1-P, and the right end of S27 is connected to one end of S29 and the left plate of Cadder1-P; the left end of S28 is connected to the right ends of S16 and S18 and the right plate of Ci1-N, the right end of S28 is connected to one end of S30 and the left plate of Cadder1-N, and the other ends of S29 and S30 are both connected to the common mode level Vcm; the left end of S31 is connected to the right plate of Ci2-P, and the right end of S27 is connected to one end of S29 and the left plate of Cadder1-P. The left end of S32 is connected to the right plate of Ci2-N, the right end of S31 is connected to one end of S34 and the left plate of Cadder2-P, the right end of S32 is connected to one end of S33 and the left plate of Cadder2-N, and the other ends of S33 and S34 are both connected to the common mode level Vcm; the right plates of Cadder1-P and Cadder2-P are connected to one end of S36 and the positive input end of the three-level quantizer to form a summing node SUM-P; the right plates of Cadder1-N and Cadder2-N are connected to one end of S35 and the negative input end of the three-level quantizer to form a summing node SUM-N, and the other ends of S35 and S36 are connected to the common mode level Vcm.

[0014] In one embodiment, the three-level quantizer is a four-input comparator, wherein when (SUM-P)-(SUM-N)>(V TH+ -V TH- ) A Q B Q C =100; when (V TH+ -V TH- )≥(SUM-P)-(SUM-N)≥-(V TH+ -V TH- ), Q A Q B Q C =001; when -(V TH+ -V TH- )>(SUM-P)-(SUM-N), Q A Q B Q C =010; where V TH+ and V TH- is the positive and negative threshold voltage of the comparator.

[0015] In one embodiment, the reference voltage feedback circuit includes feedback capacitors Cf-P and Cf-N and COMS switches S37 to S50, wherein the left ends of S37 and S38 are connected to VREFP, the left ends of S39 and S40 are connected to VREFN, the right ends of S37 and S39 are connected to the left plate of Cf-P, and the right ends of S38 and S40 are connected to the left plate of Cf-N; one end of S41, S43, S44 and S47 is connected to the right plate of Cf-P, one end of S42, S45, S46 and S48 is connected to the right plate of Cf-N, and the other ends of S41, S42, S47 and S48 are commonly connected to the common mode level Vcm; the other ends of S43 and S45 are connected to the left plate of Ci1-P, and the other ends of S44 and S46 are connected to the left plate of Ci1-N.

[0016] In one embodiment, the digital control signal generating circuit includes a non-overlapping clock generating circuit, and the non-overlapping clock generating circuit is used to generate the control signals S1-S48.

[0017] Since three-level quantization can achieve higher accuracy than single-bit quantization without the need for a complex digital calibration circuit, the accuracy of the Delta-Sigma modulator of the present invention can reach more than 16 bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a circuit diagram of a Delta-Sigma modulator using three-level quantization according to an embodiment of the present invention;

[0019] Figure 2 yes Figure 1 The control signal timing relationship diagram of the main modules in the Delta-Sigma modulator shown;

[0020] Figure 3 yes Figure 1 The circuit connection state diagram of the first-stage integrator circuit in the Delta-Sigma modulator shown in FIG. 1 when the chopping phase A arrives;

[0021] Figure 4 yes Figure 1 The circuit connection state diagram of the first-stage integrator circuit in the Delta-Sigma modulator shown in FIG. 1 when the chopping phase B arrives;

[0022] Figure 5 yes Figure 1 The main circuit diagram of the operational amplifier OTA1 of the first stage integrator circuit in the Delta-Sigma modulator shown;

[0023] Figure 6 is a common-mode feedback circuit diagram according to an embodiment of the present invention;

[0024] Figure 7 is a circuit schematic diagram of a three-level quantizer according to an embodiment of the present invention;

[0025] Figure 8 is a circuit diagram of a four-input comparator according to an embodiment of the present invention;

[0026] Fig. 9 4 is a circuit diagram of a non-overlapping clock generation circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0029] See also Figure 1 , Figure 1 The circuit diagram of a Delta-Sigma modulator using three-level quantization of the present invention is shown. The Delta-Sigma modulator mainly includes a two-stage integrator circuit (a first-stage integrator circuit and a second-stage integrator circuit), an analog adder, a three-level quantizer, a reference voltage feedback circuit, and a digital control signal generating circuit for overall timing control. The overall function of the circuit is described as follows:

[0030] First, the first-stage integrator circuit oversamples the input signal at a frequency of CK, and then integrates the input signal at a frequency of CK. During the integration period, a suitable feedback level ((VREFP-VREFN), 0, -(VREFP-VREFN) three levels) is obtained in the reference voltage feedback circuit according to the result of the three-level quantizer to feed back the first-stage integrator circuit; the second-stage integrator circuit samples and integrates the first-stage integration result of the first-stage integrator circuit at a frequency of CK or CK / 2 to obtain a second-stage integration result; thereafter, the analog adder sums the first-stage integration result and the first-stage integration result to obtain the summation result at the summation node; then, the three-level quantizer performs 1.5-bit quantization according to the signal at the summation node to obtain the output result Q A Q B Q C Finally, the reference voltage feedback circuit is based on the output result Q of the three-level quantizer. A Q B Q C , the first-stage integrator circuit is fed back with three levels of (VREFP-VREFN), 0, and -(VREFP-VREFN), thus completing a loop modulation, where VREFP and VREFN are the positive and negative terminal levels of the reference voltage respectively.

[0031] Compared with multi-level quantization, three-level quantization does not require a complex digital calibration circuit, but can achieve higher precision than single-bit quantization. Therefore, the precision of the Delta-Sigma modulator of the present invention can reach more than 16 bits. The specific structure and function of each module of the Delta-Sigma modulator are described in detail below.

[0032] First stage integrator circuit:

[0033] like Figures 1 to 5As shown, the first-stage integrator circuit includes bootstrap switches S1 to S18, first sampling capacitors Cs1-P and Cs1-N, first integration capacitors Ci1-P and Ci1-N, and a first operational amplifier OTA1. To provide sampling linearity, S1-S18 are all bootstrap switches of the same model; the first sampling capacitors Cs1-P and Cs1-N are of the same model, the first integration capacitors Ci1-P and Ci1-N are of the same model, and the first sampling capacitor: first integration capacitor = 1:10. The sampling clock frequency and the integration clock frequency are both ck. However, for the accuracy of sampling integration, the sampling integration clocks are non-overlapping, and a fully differential structure is used to reduce common-mode interference.

[0034] In the first-stage integrator circuit, the left ends of S1 and S2 are connected to the positive input signal VIP input terminal, the left ends of S3 and S4 are connected to the negative input signal VIN input terminal, the right ends of S1 and S3 are connected to one end of S5 and the left plate of Cs1-P, the right ends of S2 and S4 are connected to one end of S6 and the left plate of Cs1-N, and the other ends of S5 and S6 are connected to the common mode level Vcm; one end of S7 is connected to one end of S9 and the right plate of Cs1-P, one end of S8 is connected to one end of S10 and the right plate of Cs1-N, and the other ends of S7 and S8 are connected to the common mode level Vcm; the other end of S9 is directly connected to the positive input terminal of OTA1 , the other end of S10 is directly connected to the negative input terminal of OTA1; the left pole plate of Ci1-P is connected to one end of S11 and S12, the left pole plate of Ci1-N is connected to one end of S13 and S14, the other ends of S11 and S13 are connected together and commonly connected to the positive input terminal of OTA1, and the other ends of S12 and S14 are connected together and commonly connected to the negative input terminal of OTA1; the right pole plate of Ci1-P is connected to one end of S15 and S17, the right pole plate of Ci1-N is connected to one end of S16 and S18, the other ends of S15 and S16 are connected to the negative output terminal of OTA1, and the other ends of S17 and S18 are connected to the positive output terminal of OTA1.

[0035] The working phase of the first-stage integrator circuit is divided into a sampling phase and an integration phase. In the sampling phase: S1~S4, S7 and S8 are sampling switches, which form a sampling circuit with the first sampling capacitors Cs1-P and Cs1-N. When the sampling clock arrives, S7-S8 is controlled by the signal PS1 to close and turn on first, so that the right plates of the first sampling capacitors Cs1-P and Cs1-N are connected to the common mode level Vcm, and then two of the switches S1-S4 are closed and turned on one step later by the signal PS1-d, so that the left plates of the first sampling capacitors Cs1-P and Cs1-N are connected to the input signal. At the trailing edge of the sampling phase, switches S7-S8 are disconnected first, and S1-S4 are disconnected later. At this time, the sampling capacitor completes the sampling of the input signal; the timing relationship of the sampling signal is detailed in Figure 2. In the integration stage: S5, S6, S9 and S10, the first sampling capacitors Cs1-P and Cs1-N, the first integrating capacitors Ci1-P and Ci1-N and the first operational amplifier OTA1 form an integrating circuit. When the integration clock arrives, S9-S10 is controlled by the signal PI1 to close and conduct first, so that the right plates of the first sampling capacitors Cs1-P and Cs1-N are connected to the input terminal of the first operational amplifier OTA1, and then the switches S5-S6 are delayed by the signal PI1-d to be turned on and closed one step later, so that the left plates of the first sampling capacitors Cs1-P and Cs1-N are connected to the common mode level Vcm. The charge accumulated on the first sampling capacitors Cs1-P and Cs1-N during the sampling stage will be transferred to the first integrating capacitors Ci1-P and Ci1-N to complete the integration of the input signal. For details on the timing relationship of the integration signal, see Figure 2 .

[0036] From the characteristics of the Delta-Sigma modulation loop, it can be seen that the operational amplifier of the first-stage integrator circuit has the greatest impact on the overall loop. Therefore, in this design, the operational amplifier of the first-stage integrator needs to be chopped. The chopping frequency can be set to 1 / 128 or 1 / 256 of the sampling and integration frequency of the first-stage integrator circuit, that is, the chopping switch is switched once every 64 / 128 sampling and integration. The timing relationship of the chopping circuit control signal is detailed in Figure 2 .

[0037] The chopper circuit is composed of three groups of chopper switches, namely switches S1~S4, S11~S14 and S15~S18. The design adopts a design method that separates the input signal and feedback signal paths. The right plate of the first sampling capacitor is directly connected to the input terminal of the first operational amplifier OTA1 through a switch, and the reference voltage feedback is connected to the input terminal of the first operational amplifier OTA1 after passing through the switch. Therefore, two pairs of chopper switches S1-S4 and S15-S18 are set on the input signal path to form a pair of choppers, which can reduce the mismatch effect of the sampling capacitor; two pairs of chopper switches S11-S14 and S15-S18 form a pair of choppers, which can "chop off" the low-frequency noise of the operational amplifier and reduce the effect of the operational amplifier offset on the modulation loop.

[0038] The specific chopping operation is as follows:

[0039] like Figure 3As shown, when the chopping phase A arrives (see the circuit connection state diagram when the chopping phase A arrives): switches S11 and S14 are controlled by the signal chopA to be turned on and closed, while switches S12 and S13 are disconnected, so the left plate of the first integral capacitor Ci1-P is connected to the positive input of OTA1 via S11, and the left plate of the first integral capacitor Ci1-N is connected to the negative input of OTA1 via S14; later, switches S15 and S18 are controlled by the signal chopA-d to be turned on and closed, switches S16 and S17 are disconnected, the right plate of the first integral capacitor Ci1-P is connected to the negative output of OTA1 via switch S15, and the right plate of the first integral capacitor Ci1-N is connected to the positive output of OTA1 via switch S18. At the same time, in the adopted switch, S2 and S3 are in a forced disconnection state, but S1 and S4 are normally controlled by the sampling signal, and the first sampling capacitors Cs1-P and Cs1-N sample the input signals VIP and VIN respectively.

[0040] like Figure 4 As shown, when the chopping phase B arrives: switches S12 and S13 are controlled by the signal chopB to be turned on and closed, while S11 and S14 are disconnected, so the left plate of the first integrating capacitor Ci1-P is connected to the negative input terminal of OTA1 via S12, and the left plate of the first integrating capacitor Ci1-N is connected to the positive input terminal of OTA1 via S13; later, switches S16 and S17 are controlled by the signal chopB-d to be turned on and closed, switches S15 and S18 are disconnected, the right plate of the first integrating capacitor Ci1-P is connected to the positive output terminal of OTA1 via S17, and the right plate of the first integrating capacitor Ci1-N is connected to the negative output terminal of OTA1 via S16. At the same time, in the adopted switch, S1 and S4 are in a forced disconnection state, but S2 and S3 are normally controlled by the sampling signal, and the first sampling capacitors Cs1-P and Cs1-N sample the input signals VIN and VIP respectively.

[0041] Second stage integrator circuit:

[0042] The circuit structure of the second-stage integrator is similar to that of the first-stage integrator. Specifically, the second-stage integrator circuit includes CMOS switches S19-S26, second sampling capacitors Cs2-P and Cs2-N, second integration capacitors Ci2-P and Ci2-N, and a second operational amplifier OTA2. CMOS switches S19-S26 are of the same model, the second sampling capacitors Cs2-P and Cs2-N are of the same model, the second integration capacitors Ci2-P and Ci2-N are of the same model, and the second sampling capacitor: second integration capacitor = 1:4, the sampling clock frequency is the same as the integration clock frequency, and the frequency is ck or ck / 2, but for the accuracy of sampling integration, the sampling integration clocks are non-overlapping, and a fully differential structure is adopted to reduce common-mode interference.

[0043] In the second-stage integrator circuit, the left end of S9 is connected to the right ends of S15 and S17 and the right plate of Ci1-P, the left end of S20 is connected to the right ends of S16 and S18 and the right plate of Ci1-N, the right end of S9 is connected to one end of S21 and the left plate of Cs2-P, the right end of S20 is connected to one end of S22 and the left plate of Cs2-N, and the other ends of S21 and S22 are connected to the common mode level Vcm; one end of S25 is connected to one end of S23 and the left plate of Cs2-P. The right plate is connected, one end of S26 is connected to one end of S24 and the right plate of the sampling capacitor Cs2-N, and the other ends of S23 and S24 are commonly connected to the common mode level Vcm; the other end of S25 is directly connected to the positive input terminal of OTA2 and the left plate of Ci2-P, and the other end of S26 is directly connected to the negative input terminal of OTA2 and the left plate of Ci2-N; the right plate of Ci2-P is connected to the negative output terminal of OTA2, and the right plate of Ci2-N is connected to the positive output terminal of OTA2.

[0044] Similarly, the working phase of the second-stage integrator circuit is divided into a sampling phase and an integration phase. In the sampling phase: switches S19, S20, S23 and S24 are sampling switches, and form a sampling circuit with the second sampling capacitors Cs2-P and Cs2-N; when the sampling clock arrives, S23 and S24 are controlled by the clock signal PS2 to close and conduct first, so that the right plates of the second sampling capacitors Cs2-P and Cs2-N are connected to the common mode level Vcm, and then switches S19 and S20 are controlled by the signal PS2-d to close and conduct one step later, so that the left plates of the second sampling capacitors Cs2-P and Cs2-N are connected to the input signal. At the trailing edge of the sampling phase, switches S23 and S24 are disconnected first, and S19 and S20 are disconnected later. At this time, the sampling capacitor completes the sampling of the input signal; the timing relationship of the sampling signal is detailed in Figure 2 . In the integration stage: switches S21, S22, S25 and S26, the second sampling capacitors Cs2-P and Cs2-N, the second integrating capacitors Ci2-P and Ci2-N and the second operational amplifier OTA2 form an integrating circuit. When the integration clock arrives, S25 and S26 are controlled by the clock signal PI2 to close and conduct first, so that the right plates of the second sampling capacitors Cs2-P and Cs2-N are connected to the input terminal of OTA2. Then switches S21-S22 are controlled by the clock signal PI2-d to be turned on and closed one step later, so that the left plates of the second sampling capacitors Cs2-P and Cs2-N are connected to the common mode level Vcm. The charges accumulated on the second sampling capacitors Cs2-P and Cs2-N during the sampling stage will be transferred to the second integrating capacitors Ci2-P and Ci2-N to complete the integration of the input signal. For details on the timing relationship of the integration signal, see Figure 2 .

[0045] According to the design requirements, the operational amplifiers in the integrator circuit (i.e., OTA1 and OTA2) are folded cascode fully differential operational amplifiers. In view of the high gain requirement of OTA1, gain boosting technology (GainBoosting) is used on the basis of folded cascode - the same as auxiliary operational amplifier A Aux The introduction of OTA1 can increase the gain of A Aux Considering the characteristics of discrete time integration, switch capacitor common mode feedback is used to provide appropriate common mode feedback for OTA1. For detailed circuit, see Figure 5 and Figure 6 As for OTA2 in the second-stage integrator circuit, since the requirements for OTA2 are lower than those for OTA1, the second-stage requirements can be met by reasonable scaling of the structure of OTA1 (such as removing the gain-boosting auxiliary op amp, etc.), and the structure is similar to OTA1 and will not be described in detail.

[0046] Analog adder:

[0047] In the circuit design, it is necessary to sum the signal from the first-stage integrator output and the signal from the second-stage integrator output. Considering the characteristics of the circuit, an analog adder is used. This analog adder uses a switched capacitor to achieve the summation operation of the signal. Figure 1 As shown, the analog adder includes summing capacitors Cadder1-P, Cadder1-N, Cadder2-P and Cadder2-N and CMOS switches S27 to S36. The summing time is the sampling phase of the first-stage integrator (the first-stage integration has ended) and the integration phase of the second-stage integrator, and the summing result is obtained at a moment before the integration of the second-stage integrator ends.

[0048] Among them, the left end of S27 is connected to the positive output signal of the first-stage integrator circuit (i.e., the right ends of S15 and S17 and the right plate of Ci1-P), and the right end of S27 is connected to one end of S29 and the left plate of Cadder1-P; the left end of S28 is connected to the negative output signal of the first-stage integrator circuit (i.e., the right ends of S16 and S18 and the right plate of Ci1-N), the right end of S28 is connected to one end of S30 and the left plate of Cadder1-N, and the other ends of S29 and S30 are both connected to the common mode level Vcm; the left end of S31 is connected to the right plate of Ci2-P, the left end of S32 is connected to the right plate of Ci2-N, and S31 The right end of S32 is connected to one end of S33 and the left plate of Cadder2-N, and the other ends of S33 and S34 are connected to the common mode level Vcm; the right plates of Cadder1-P and Cadder2-P are connected to one end of S36 and the positive input end of the three-level quantizer to form a summing node SUM-P; the right plates of Cadder1-N and Cadder2-N are connected to one end of S35 and the negative input end of the three-level quantizer to form a summing node SUM-N, and the other ends of S35 and S36 are connected to the common mode level Vcm.

[0049] The specific operation is as follows: before summing, switches S29, S30, S33, S34, S35 and S36 are closed and turned on by the clock PS2-d signal, so that the left and right plates of the summing capacitors Cadder1-P, Cadder1-N, Cadder2-P and Cadder2-N are connected to the common mode level Vcm, the charge on the summing capacitor is cleared, and the summing capacitor is reset. At the leading edge of the summing clock, the PS2-d signal is low, and switches S29, S30, S33, S34, S35 and S36 are disconnected, and both ends of the summing capacitor are suspended; when summing, the summing capacitors Cadder1-P, Cadder1-N, Cadder2-P and Cadder2-N are connected to the common mode level Vcm, and the charge on the summing capacitor is cleared, and the summing capacitor is reset. At the leading edge of the summing clock, the PS2-d signal is low, and switches S29, S30, S33, S34, S35 and S36 are disconnected, and both ends of the summing capacitor are suspended. The right plates of Cadder2-P and Cadder2-N are connected together as summing nodes SUM-P and SUM-N. Switches S27, S28, S31 and S32 are closed and turned on by clock PI2-d, so that the left plates of summing capacitors Cadder1-P, Cadder1-N, Cadder2-P and Cadder2-N are connected to their respective input signal paths. According to the law of charge conservation, the summation results of the two input signal paths are obtained at the summing nodes SUM-P and SUM-N, so that the summation operation of the primary integration result from the first-stage integrator circuit and the secondary integration result from the second-stage integrator circuit can be realized; the timing relationship of the summation signal is detailed in Figure 2 .

[0050] Three-level quantizer:

[0051] This design adopts a three-level quantization design, so the three-level quantizer is a four-input comparator. The specific circuit implementation method is detailed in Figure 7 and Figure 8 Among them, V TH+ and V TH- is the threshold voltage of the comparator. According to the input range of the comparator (SUM-P)-(SUM-N), the threshold voltage V TH+ and V TH- The input range is divided into three equal parts. When the PI2 falling edge arrives, the comparison is performed according to the comparator input. When the PS2 falling edge arrives, the comparison result is latched, and the modulation loop is fed back according to the latched result. When the comparison signal PI2 falls, the comparator obtains Q according to the input relationship. A , Q B and Q C Three outputs. For details on the timing relationship of the comparator signals, see Figure 2 . Among them: When (SUM-P)-(SUM-N)>(V TH+ -V TH- ) A Q B Q C =100; when (V TH+- V TH- )≥(SUM-P)-(SUM-N)≥-(V TH+ -V TH- ), Q A Q B Q C =001; when -(V TH+ -V TH- )>(SUM-P)-(SUM-N), Q A Q B Q C =010.

[0052] Reference voltage feedback circuit:

[0053] The reference voltage feedback circuit includes feedback capacitors Cf-P and Cf-N and CMOS switches S37 to S50. S49 and S50 are gain control switches. When the switches are closed, the feedback capacitance doubles and the feedback coefficient is reduced by half, resulting in the overall gain of the modulator being reduced by half and the equivalent input signal being reduced by half. S49 and S50 are disconnected by default.

[0054] Among them, the left ends of S37 and S38 are connected to VREFP, the left ends of S39 and S40 are connected to VREFN, the right ends of S37 and S39 are connected to the left plate of Cf-P, and the right ends of S38 and S40 are connected to the left plate of Cf-N; one end of S41, S43, S44 and S47 is connected to the right plate of Cf-P, one end of S42, S45, S46 and S48 is connected to the right plate of Cf-N, and the other ends of S41, S42, S47 and S48 are commonly connected to the common mode level Vcm; the other ends of S43 and S45 are connected to the left plate of Ci1-P of the first-stage integrator circuit (that is, the right ends of S11 and S12), and the other ends of S44 and S46 are connected to the left plate of Ci1-N of the first-stage integrator circuit (that is, the right ends of S13 and S14). According to the comparison output result of the three-level quantizer, the feedback circuit can feedback three feedback voltages of (VREFP-VRTEFN), 0, and -(VREFP-VRTEFN) to the modulation loop to realize three-level feedback.

[0055] Before feedback, the reference voltage needs to be sampled, that is: first, S41 and S42 are closed and turned on under the control of signal PS2, so that the right plates of Cf-P and Cf-N are connected to the common mode level Vcm, then S37~S40 are closed and turned on under the control of signal PS2-d, so that the left plate of Cf-P is connected to the reference voltage VREFP, and the left plate of Cf-N is connected to the reference voltage VREFN, and the sampling of VREFP and VREFN is preliminarily completed; before the next phase arrives, S38 and S39 are controlled by signal PI2-d to be closed and turned on, so that the left plate of Cf-P is connected to VREFN, and the left plate of Cf-N is connected to VREFP. As a result, the voltage of the left plate of Cf-P changes from VREFP to VREFN, so that the feedback voltage obtained at Cf-P is (VREFP-VREFN); similarly, the feedback voltage obtained on the feedback capacitor Cf-N is -(VREFP-VREFN), so that feedback preparation is provided for specific feedback control. The timing relationship of the feedback circuit control signal is detailed in Figure 2 .

[0056] When the actual feedback signal arrives (i.e. the quantized result output), there is:

[0057] If the quantized output is Q A Q B Q C =100, S44 and S45 are affected by Q AThe signal control is closed and turned on, then the right plate of Cf-P is connected to the negative input terminal of OTA1 through S44, that is, the feedback voltage (VREFP-VREFN) is provided for the negative input integral capacitor, and the right plate of the feedback capacitor Cf-N is connected to the positive input terminal of OTA1 through S45, that is, the feedback voltage -(VREFP-VREFN) is provided for the positive input integral capacitor;

[0058] If the quantized output is Q A Q B Q C =010, S43 and S46 are affected by Q B The signal control is closed and turned on, then the right plate of Cf-P is connected to the positive input terminal of OTA1 through S43, that is, the feedback voltage (VREFP-VREFN) is provided for the positive input integral capacitor, and the right plate of the feedback capacitor Cf-N is connected to the negative input terminal of OTA1 through S46, that is, the feedback voltage -(VREFP-VREFN) is provided for the negative input integral capacitor;

[0059] If the quantized output is Q A Q B Q C =001, S47 and S48 are affected by Q C When the signal control is closed and turned on, the right plate of Cf-P is connected to the common mode voltage Vcm through S47, and the right plate of Cf-N is connected to the common mode voltage Vcm through S48, that is, the feedback circuit does not provide feedback to the positive input integral capacitor and the negative input integral capacitor, that is, the feedback voltage is 0.

[0060] Digital control signal generation circuit:

[0061] The main circuit is designed with various clock control scenarios such as sampling integration, chopping, summation, and comparison, and some operating frequencies are inconsistent. Combined with the working timing requirements, the digital control signal generation circuit mainly includes clock frequency division circuits, sampling integration of each module, and non-overlapping clock generation circuits for chopping control. The frequency division circuit is a 1 / 2 / 4 / 8 / 16 / 32 / 64 / 128 / 256-fold frequency division circuit composed of commonly used triggers for use by different modules. Non-overlapping clocks are designed according to the non-overlapping timing requirements of each module. The main body of the non-overlapping clock circuit is similar, and each module makes appropriate delay extensions on the main non-overlapping clock circuit. Therefore, only one non-overlapping circuit is listed here, such as Fig. 9 For non-overlapping results, see Figure 2 .

[0062] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A Delta-Sigma modulator using three-level quantization, characterized in that: The invention comprises a first-stage integrator circuit, a second-stage integrator circuit, an analog adder, a three-level quantizer, a reference voltage feedback circuit and a digital control signal generating circuit for overall timing control, wherein the first-stage integrator circuit is used to sample and integrate the input signal to obtain a primary integration result; the second-stage integrator circuit is used to sample and integrate the primary integration result to obtain a secondary integration result; the analog adder is used to sum the primary integration result and the secondary integration result to obtain a summation result at a summation node; the three-level quantizer is used to perform 1.5-bit quantization on the summation result to obtain an output result Q A Q B Q C The reference voltage feedback circuit is used to generate a reference voltage according to the output result Q A Q B Q C , a three-level feedback of (VREFP-VREFN), 0, -(VREFP-VREFN) is performed on the first-stage integrator circuit, wherein VREFP and VREFN are respectively the positive and negative terminal levels of the reference voltage.

2. The Delta-Sigma modulator using three-level quantization according to claim 1, characterized in that: The first-stage integrator circuit oversamples and integrates the input signal at a frequency of CK; and the second-stage integrator circuit samples and integrates the one-time integration result at a frequency of CK or CK / 2, wherein CK is a clock signal frequency.

3. The Delta-Sigma modulator using three-level quantization according to claim 1, characterized in that: The first-stage integrator circuit includes bootstrap switches S1 to S18, first sampling capacitors Cs1-P and Cs1-N, first integrating capacitors Ci1-P and Ci1-N, and a first operational amplifier OTA1, wherein the left ends of S1 and S2 are connected to the positive input signal VIP input terminal, the left ends of S3 and S4 are connected to the negative input signal VIN input terminal, the right ends of S1 and S3 are connected to one end of S5 and the left plate of Cs1-P, the right ends of S2 and S4 are connected to one end of S6 and the left plate of Cs1-N, and the other ends of S5 and S6 are connected to the common mode level Vcm; one end of S7 is connected to one end of S9 and the right plate of Cs1-P, one end of S8 is connected to one end of S10 and the right plate of Cs1-N, and the other ends of S7 and S8 are connected to the common mode level Vcm. Connected to the common mode level Vcm; the other end of S9 is directly connected to the positive input terminal of OTA1, and the other end of S10 is directly connected to the negative input terminal of OTA1; the left pole plate of Ci1-P is connected to one end of S11 and S12, the left pole plate of Ci1-N is connected to one end of S13 and S14, the other ends of S11 and S13 are connected together and commonly connected to the positive input terminal of OTA1, and the other ends of S12 and S14 are connected together and commonly connected to the negative input terminal of OTA1; the right pole plate of Ci1-P is connected to one end of S15 and S17, the right pole plate of Ci1-N is connected to one end of S16 and S18, the other ends of S15 and S16 are connected to the negative output terminal of OTA1, and the other ends of S17 and S18 are connected to the positive output terminal of OTA1.

4. The Delta-Sigma modulator using three-level quantization according to claim 3, characterized in that: The capacitance ratio of the first sampling capacitor to the first integrating capacitor is 1:

10.

5. The Delta-Sigma modulator using three-level quantization according to claim 3, characterized in that: The second-stage integrator circuit includes CMOS switches S19 to S26, second sampling capacitors Cs2-P and Cs2-N, second integrating capacitors Ci2-P and Ci2-N, and a second operational amplifier OTA2, wherein the left end of S9 is connected to the right ends of S15 and S17 and the right plate of Ci1-P, the left end of S20 is connected to the right ends of S16 and S18 and the right plate of Ci1-N, the right end of S9 is connected to one end of S21 and the left plate of Cs2-P, the right end of S20 is connected to one end of S22 and the left plate of Cs2-N, and the other ends of S21 and S22 are connected. Commonly connected to the common mode level Vcm; one end of S25 is connected to one end of S23 and the right plate of Cs2-P, one end of S26 is connected to one end of S24 and the right plate of the sampling capacitor Cs2-N, and the other ends of S23 and S24 are commonly connected to the common mode level Vcm; the other end of S25 is directly connected to the positive input terminal of OTA2 and the left plate of Ci2-P, and the other end of S26 is directly connected to the negative input terminal of OTA2 and the left plate of Ci2-N; the right plate of Ci2-P is connected to the negative output terminal of OTA2, and the right plate of Ci2-N is connected to the positive output terminal of OTA2.

6. The Delta-Sigma modulator using three-level quantization according to claim 5, characterized in that: The capacitance ratio of the second sampling capacitor to the second integrating capacitor is 1:

4.

7. The Delta-Sigma modulator using three-level quantization according to claim 5, characterized in that: The analog adder includes summing capacitors Cadder1-P, Cadder1-N, Cadder2-P and Cadder2-N and CMOS switches S27 to S36, wherein the left end of S27 is connected to the right ends of S15 and S17 and the right plate of Ci1-P, and the right end of S27 is connected to one end of S29 and the left plate of Cadder1-P; the left end of S28 is connected to the right ends of S16 and S18 and the right plate of Ci1-N, the right end of S28 is connected to one end of S30 and the left plate of Cadder1-N, and the other ends of S29 and S30 are both connected to the common mode level Vcm; the left end of S31 is connected to the right plate of Ci2-P, and the left end of S32 is connected to the left plate of Ci1-N. The right end of S31 is connected to the right plate of Ci2-N, the right end of S31 is connected to one end of S34 and the left plate of Cadder2-P, the right end of S32 is connected to one end of S33 and the left plate of Cadder2-N, and the other ends of S33 and S34 are both connected to the common mode level Vcm; the right plates of Cadder1-P and Cadder2-P are connected to one end of S36 and the positive input end of the three-level quantizer to form a summing node SUM-P; the right plates of Cadder1-N and Cadder2-N are connected to one end of S35 and the negative input end of the three-level quantizer to form a summing node SUM-N, and the other ends of S35 and S36 are connected to the common mode level Vcm.

8. The Delta-Sigma modulator using three-level quantization according to claim 7, characterized in that: The three-level quantizer is a four-input comparator, where (SUM-P)-(SUM-N)>(V TH+ -V TH- ) A Q B Q C =100; when (V TH+ -V TH- )≥(SUM-P)-(SUM-N)≥-(V TH+ -V TH- ), Q A Q B Q C =001; when -(V TH+ -V TH- )>(SUM-P)-(SUM-N), Q A Q B Q C =010; where V TH+ and V TH- is the positive and negative threshold voltage of the comparator.

9. The Delta-Sigma modulator using three-level quantization according to claim 7, characterized in that: The reference voltage feedback circuit includes feedback capacitors Cf-P and Cf-N and COMS switches S37~S50, wherein the left ends of S37 and S38 are connected to VREFP, the left ends of S39 and S40 are connected to VREFN, the right ends of S37 and S39 are connected to the left plate of Cf-P, and the right ends of S38 and S40 are connected to the left plate of Cf-N; one end of S41, S43, S44 and S47 is connected to the right plate of Cf-P, one end of S42, S45, S46 and S48 is connected to the right plate of Cf-N, and the other ends of S41, S42, S47 and S48 are commonly connected to the common mode level Vcm; the other ends of S43 and S45 are connected to the left plate of Ci1-P, and the other ends of S44 and S46 are connected to the left plate of Ci1-N.

10. The Delta-Sigma modulator using three-level quantization according to claim 9, characterized in that: The digital control signal generating circuit comprises a non-overlapping clock generating circuit, and the non-overlapping clock generating circuit is used to generate control signals S1-S48.

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