Electronic device and manufacturing method thereof

Abstract

An electronic device includes a first substrate, a first lead, a side lead, and a second lead. The first substrate has a first surface, a second surface opposite to the first surface, a side surface between the first surface and the second surface, and a chamfered surface between the second surface and the side surface. The first wires are arranged on the first surface of the first substrate. The second lead is arranged on the second surface of the first substrate. The side wires are arranged on the side surface, the chamfered surface and the second surface of the first substrate, and are electrically connected with the first wires and the second wires. The side wire has a first portion located on the side surface, a second portion located on the chamfered surface, and a third portion located on the second surface, wherein the width of the second portion of the side wire is less than or equal to the width of the second wire.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device including a side wire. Background Art

[0002] With the development of digital technology, electronic devices have been widely used in all aspects of daily life. Seamless electronic devices can provide users with better experience.

[0003] Currently, seamless electronic devices are prepared by forming side wires on the side surfaces of electronic devices. However, the side wires located at the corners of the electronic devices have problems such as high contact impedance and easy breakage and damage. Summary of the invention

[0004] In view of the above problems, the present disclosure provides an electronic device including a side wire with an improved structure.

[0005] Some embodiments of the present disclosure provide an electronic device, which includes a first substrate, a first wire, a side wire, and a second wire. The first substrate has a first surface, a second surface relative to the first surface, a side surface between the first surface and the second surface, and a chamfer surface between the second surface and the side surface. The first wire is disposed on the first surface of the first substrate. The second wire is disposed on the second surface of the first substrate. The side wire is disposed on the side surface, the chamfer surface, and the second surface of the first substrate, and is electrically connected to the first wire and the second wire. The side wire has a first portion located on the side surface, a second portion located on the chamfer surface, and a third portion located on the second surface, wherein a width W2 of the second portion of the side wire is less than or equal to a width W3 of the second wire.

[0006] Some embodiments of the present disclosure provide a method for manufacturing an electronic device, comprising: providing a first substrate, the first substrate having a first surface, a second surface opposite to the first surface, a side surface located between the first surface and the second surface, and a chamfer surface located between the second surface and the side surface; forming a first wire on the first surface; forming a second wire on the second surface; forming a conductive layer on the side surface, the chamfer surface and the second surface; patterning the conductive layer to form a side wire, and the side wire electrically connects the first wire and the second wire, wherein a first portion of the side wire located on the side surface has a first width W1, a second portion of the side wire located on the chamfer surface has a second width W2, the second wire has a third width W3, and the second width W2 is less than or equal to the third width W3. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1The present disclosure can be more fully understood from the following detailed description when read together. It is worth noting that, in accordance with standard practice in the industry, the various features are not shown in equal proportions. In fact, for the sake of clarity, the size of various features can be arbitrarily enlarged or reduced.

[0008] Figure 1 is a schematic cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0009] Figure 2 yes Figure 1 An enlarged schematic diagram of area A of the electronic device is shown.

[0010] Figure 3 yes Figure 1 FIG. 1 is a schematic plan view of area A of the electronic device shown.

[0011] Figure 4 is a schematic cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0012] Figure 5 is a schematic cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0013] Figure 6 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0014] FIG. 7A to FIG. 7C It is a partial plan view of an electronic device in the step of patterning a conductive layer in a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0015] FIG. 8A to FIG. 8C It is a partial plan view of an electronic device in the step of patterning a conductive layer in a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0016] 9A to 9D It is a partial plan view of an electronic device in the step of patterning a conductive layer in a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0017] FIG. 10A to FIG. 10C It is a partial plan view of an electronic device in the step of patterning a conductive layer in a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0018] FIG. 11A to FIG. 11C It is a partial plan view of an electronic device in the step of patterning a conductive layer in a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0019]

Explanation of symbols

[0020] 1,2,3: Electronic devices

[0021] 10: First substrate

[0022] 10S1: First surface

[0023] 10S2: Second surface

[0024] 10S3: Side surface

[0025] 10S4: Chamfered surface

[0026] 10S41: First sub-surface

[0027] 10S43: Second sub-surface

[0028] 10S45: Third subsurface

[0029] C1: First interface

[0030] C2: Center of chamfered surface

[0031] C3: Second interface

[0032] 12,16: Electronic components

[0033] 13: First wire

[0034] 14: Electronic components

[0035] 15: Side wire

[0036] 15': Conductive layer

[0037] 15”: Additional conductive layer

[0038] 151: Part 1

[0039] 153: Part 2

[0040] 155: Part 3

[0041] 1503: first conductive layer

[0042] 1531: First subsection

[0043] 1533: Second subsection

[0044] 17: Second wire

[0045] 20: Second substrate

[0046] 30: First insulation layer

[0047] 40: Functional layer

[0048] 50: Barrier layer

[0049] A: Area

[0050] D1,D2: Direction

[0051] W,1W2,W3: Width

[0052] S101-S109: Steps DETAILED DESCRIPTION

[0053] The following is a detailed description of the electronic device of the embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and are not limitations of the present disclosure. In addition, similar and / or corresponding numbers may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding numbers is only for the purpose of simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0054] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in the embodiments to describe the relative relationship of one component to another component in the drawings. It is understood that if the device in the drawings is turned upside down, the component described on the "lower" side will become the component on the "upper" side. The embodiments of the present disclosure may be used in conjunction with the attached drawings. Figure 1 It is also understood that the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not drawn to scale, and in fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0055] Furthermore, when a first material layer is mentioned as being located on or above a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer or the first material layer and the second material layer may not be in direct contact with each other, that is, there may be one or more other material layers between the first material layer and the second material layer. However, when a first material layer is mentioned as being directly located on the second material layer, it means a situation where the first material layer and the second material layer are in direct contact with each other.

[0056] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify components, do not imply or represent any previous ordinal numbers of the (or these) components, nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The claims and the specification may not use the same words, for example, the first component in the specification may be the second component in the claims.

[0057] In some embodiments of the present disclosure, terms such as "connection", "interconnection", etc., related to bonding and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein another structure is disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "coupled" include any direct and indirect electrical connection means.

[0058] In the text, the terms "about" and "substantially" generally indicate a range within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value. The numbers given here are approximate numbers, that is, in the absence of a specific description of "about" and "substantially", the meaning of "about" and "substantially" can still be implied. The term "a range between a first value and a second value" means that the range includes the first value, the second value, and other values ​​between them.

[0059] It should be understood that the following embodiments may replace, reorganize, or combine features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0061] The electronic device disclosed herein may include a display device, an antenna device, a sensing device, a touch display, a packaging device, a curved display, or a non-rectangular electronic device (free shape display), but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The antenna device may, for example, include an antenna splicing device, but is not limited thereto. The packaging device may be a packaging device suitable for wafer-level packaging (Wafer-Level Package, WLP) technology or panel-level packaging (Panel-Level Package, WLP) technology, such as a chip first process or a chip after loading (RDL first) process. It should be noted that the electronic device may be any combination of the foregoing, but is not limited thereto. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may include an electronic component. The electronic device may have a peripheral system such as a drive system, a control system, a light source system, a shelf system, etc. to support the display device, the antenna device, or the splicing device.

[0062] One aspect of the present disclosure provides an electronic device. Figures 1 to 3 The structure of the electronic device according to the embodiment of the present disclosure is described in detail. Figure 1 is a cross-sectional schematic diagram of an electronic device 1 according to an embodiment of the present disclosure. Figure 2 yes Figure 1 An enlarged schematic diagram of area A of the electronic device 1 is shown. Figure 3 yes Figure 1 A schematic plan view of area A is shown.

[0063] like Figures 1 to 3As shown, the electronic device 1 of the present disclosure includes a first substrate 10 and a first wire 13, a side wire 15, and a second wire 17 disposed on the first substrate 10. The first substrate 10 has a first surface 10S1, a second surface 10S2 relative to the first surface 10S1, a side surface 10S3 located between the first surface 10S1 and the second surface 10S2, and a chamfer surface 10S4 located between the second surface 10S2 and the side surface 10S3. The first wire 13 is disposed on the first surface 10S1 of the first substrate 10. The second wire 17 is disposed on the second surface 10S2 of the first substrate 10. The side wire 15 is disposed on the side surface 10S3, the chamfer surface 10S4, and the second surface 10S2 of the first substrate 10, and is electrically connected to the first wire 13 and the second wire 17. The side conductive line 15 has a first portion 151 located on the side surface 10S3 , a second portion 153 located on the chamfered surface 10S4 , and a third portion 155 located on the second surface 10S2 , wherein a width W2 of the second portion 153 of the side conductive line 15 is less than or equal to a width W3 of the second conductive line 17 .

[0064] The first substrate 10 may include a flexible substrate, a rigid substrate, or a combination of the foregoing, but is not limited thereto. In some embodiments, the first substrate 10 may be a light-transmitting substrate or a semi-transmitting substrate. According to some embodiments, the material of the first substrate 10 may include glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials, or any combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the first substrate 10 may further include a conductive layer, an insulating layer, a dielectric layer, a display medium layer, an air layer, a vacuum layer, or any combination of the foregoing, but the present disclosure is not limited thereto.

[0065] The first substrate 10 has a first surface 10S1, a second surface 10S2 opposite to the first surface 10S1, a side surface 10S3 located between the first surface 10S1 and the second surface 10S2, and a chamfer surface 10S4 located between the second surface 10S2 and the side surface 10S3. The normal direction D1 of the electronic device 1 is substantially perpendicular to the first surface 10S1 and the second surface 10S2 of the electronic device 1. The normal direction D1 of the electronic device 1 is substantially parallel to the side surface 10S3 of the electronic device 1. The chamfer surface 10S4 connects the second surface 10S2 and the side surface 10S3. In some embodiments, the chamfer surface 10S4 may be an inclined plane with a single slope. In some embodiments, the chamfer surface 10S4 may include a plurality of inclined planes with different slopes. For example, in some embodiments, the chamfer surface 10S4 includes a first sub-surface 10S41, a second sub-surface 10S43, and a third sub-surface 10S45. The first sub-surface 10S41 is adjacent to the side surface 10S3, the third sub-surface 10S45 is adjacent to the second surface 10S2, the second sub-surface 10S43 is located between the first sub-surface 10S41 and the third sub-surface 10S45, and the first sub-surface 10S41, the second sub-surface 10S43 and the third sub-surface 10S45 have different plane slopes. Figure 2 As shown, but the present disclosure is not limited thereto. The interface between the chamfered surface 10S4 and the second surface 10S2 is defined as the first interface C1 of the first substrate 10, and the interface between the chamfered surface 10S4 and the side surface 10S3 is defined as the second interface C3 of the first substrate 10. The chamfered surface center C2 of the first substrate 10 is located between the first interface C1 and the second interface C3, and the distance between the chamfered surface center C2 and the first interface C1 is equal to the distance between the chamfered surface center C2 and the second interface C3.

[0066] The first conductive line 13 is formed on the first surface 10S1 of the first substrate 10 and extends along the first conductive line direction. The first conductive line 13 may include a single layer or a multilayer structure. The first conductive line 13 may include copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium, alloys thereof, any combination thereof or other metal materials with good conductivity. The formation method of the first conductive line 13 may include but is not limited to a printing process, an inkjet process, electroplating, chemical plating, a deposition process, a photolithography process, an etching process or other commonly used processes. The deposition process may include chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method. In some embodiments of the present disclosure, the chemical vapor deposition method may be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or other commonly used methods, but the present disclosure is not limited thereto. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other suitable processes or combinations of the foregoing. In addition, the photolithography process may be performed or replaced by other appropriate methods, such as unshielded lithography, electron-beam writing and ion-beam writing. The etching process includes dry etching, wet etching or other etching methods, but the present disclosure is not limited thereto.

[0067] The second conductive line 17 may be formed on the second surface 10S2 and extend along the second conductive line direction. The second conductive line 17 has a width W3 in a direction perpendicular to the second conductive line direction. The "width W3" of the second conductive line 17 refers to the maximum width of the second conductive line 17 in the direction perpendicular to the second conductive line direction. Figure 3 In some embodiments, the first interface C1 of the first substrate 10 is located between the boundary of the second conductive line 17 and the center C2 of the chamfered surface of the first substrate 10 , but the present disclosure is not limited thereto. In some embodiments, the first interface C1 of the substrate 10 may be flush with the boundary of the second conductive line 17 .

[0068] The second wire 17 may include a single layer or a multilayer structure. The second wire 17 may include copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium, alloys thereof, any combination thereof or other metal materials with good conductivity. The material and structure of the second wire 17 may be the same as or different from the material and structure of the first wire 13. The method for forming the second wire 17 may include a printing process, an inkjet process, electroplating, chemical plating, a deposition process, a photolithography process, an etching process or other commonly used processes. The method for forming the second wire 17 may be the same as or different from the method for forming the first wire 13.

[0069] The side wire 15 is formed on the side surface 10S3, the chamfered surface 10S4 and the second surface 10S2 of the first substrate 10 and electrically connects the first wire 13 and the second wire 17. The side wire 15 may include a single layer or a multilayer structure. In some embodiments, for example, the side wire 15 may include a first conductive layer 1503, but the present disclosure is not limited thereto. In some embodiments, the side wire 15 may further include a second conductive layer located on the first conductive layer 1503. The formation method of the side wire 15 may include a printing process, an inkjet process, electroplating, a sputtering process, chemical plating, a deposition process, a photolithography process, an exposure process, a laser patterning process, an etching process or other commonly used processes. The formation method of the side wire 15 may be the same as or different from the formation method of the second wire 17 and / or the first wire 13. The side wire 15 may include copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium, alloys thereof, any combination thereof or other metal materials with good conductivity. The first conductive layer 1503 and the second conductive layer may include materials that are the same or different from each other. The side wire 15 may include a first portion 151 located on the side surface 10S3, a second portion 153 located on the chamfered surface 10S4, and a third portion 155 located on the second surface 10S2. The first portion 151, the second portion 153, and the third portion 155 of the side wire 15 are arranged along the side wire direction. In the side wire direction, the second portion 153 of the side wire 15 is located between the first portion 151 and the third portion 155 and electrically connects the first portion 151 and the third portion 155.

[0070] The first portion 151 of the side wire 15 has a width W1 in a direction perpendicular to the direction of the side wire. The second portion 153 of the side wire 15 has a width W2 in a direction perpendicular to the direction of the side wire. The width W2 of the second portion 153 is less than or equal to the width W3 of the second wire 17, and is greater than the width W1 of the first portion 151 of the side wire 15. In some embodiments, the difference between the width W2 of the second portion 153 of the side wire 15 and the width W1 of the first portion 151 of the side wire 15 is between 10 and 100 um, but the present disclosure is not limited thereto. In some embodiments, the difference between the width W2 of the second portion 153 of the side wire 15 and the width W1 of the first portion 151 of the side wire 15 is between 15 and 95 um, 20 to 80 um, or 25 to 75 um. In some embodiments, the width of the third portion 155 of the side wire 15 is greater than the width W1 of the first portion 151 of the side wire 15 and less than the width W3 of the second wire 17.

[0071] The second portion 153 of the side conductor 15 has a first sub-portion 1531 and a second sub-portion 1533 connected to the first sub-portion 1531. The first sub-portion 1531 of the second portion 153 is adjacent to the first portion 151, and the second sub-portion 1533 is adjacent to the third portion 155. In some embodiments, the interface between the first sub-portion 1531 and the second sub-portion 1533 overlaps with the chamfered surface center C2, but the present disclosure is not limited thereto. In a direction perpendicular to the direction of the side conductor, the width of the second sub-portion 1533 of the side conductor 15 is greater than the width of the first sub-portion 1531 of the side conductor 15, but the present disclosure is not limited thereto. In some embodiments, the width of the second portion 153 increases gradually from the second interface C3 between the chamfered surface 10S4 and the side surface 10S3 toward the first interface C1 between the chamfered surface 10S4 and the second surface 10S2. That is, the width of the first sub-portion 1531 of the side conductor 15 gradually increases from the second interface C3 between the chamfered surface 10S4 and the side surface 10S3 toward the interface between the first sub-portion 1531 and the second sub-portion 1533. The width of the second sub-portion 1533 of the side conductor 15 gradually increases from the interface between the first sub-portion 1531 and the second sub-portion 1533 toward the first interface C1 between the chamfered surface 10S4 and the second surface 10S2.

[0072] The width of each portion of the side conductor 15 is the maximum width of the portion of the side conductor 15 in the direction perpendicular to the side conductor direction. For example, the "width W1" of the first portion 151 of the side conductor 15 is the maximum width of the first portion 151 of the side conductor 15 in the direction perpendicular to the side conductor direction, and the "width W1" of the second portion 153 of the side conductor 15 is the maximum width of the second portion 153 of the side conductor 15 in the direction perpendicular to the side conductor direction. Figure 3By making the first portion 151 , the second portion 153 , and the third portion 155 of the side conductive line 15 have the above-mentioned width design, the side conductive line of the present disclosure can have a lower contact impedance and / or is not easy to be broken or damaged.

[0073] In some embodiments, the electronic device of the present disclosure may include an electronic component 14 disposed on the second surface 10S2 of the first substrate 10. The electronic component 14 may be electrically connected to the second wire 17. Examples of the electronic component 14 may include, but are not limited to, an integrated circuit, a chip-on-film device (COF), and a flexible printed circuit board (FPC). In some embodiments, a plurality of electronic components 14 may be disposed on the second surface 10S2, and these electronic components 14 may be the same or different from each other.

[0074] In some embodiments, the electronic device of the present disclosure may further include an electronic component disposed on the first surface 10S1 of the first substrate 10. The electronic component may be electrically connected to the first wire 13. Examples of electronic components may include, but are not limited to, passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light emitting diode or a photodiode. The light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (quantum dot LED), but the present disclosure is not limited thereto. In some embodiments, a plurality of electronic components may be disposed on the first surface 10S1, and these electronic components may be the same or different from each other.

[0075] Figure 4 FIG. 2 is a cross-sectional schematic diagram of an electronic device 2 according to an embodiment of the present disclosure. Figure 4 As shown, the electronic device 2 of the present disclosure includes a first substrate 10 , a second substrate 20 opposite to the first substrate 10 , a first wire 13 , a side wire 15 , a second wire 17 , a first electronic component 12 , an electronic component 14 , a second electronic component 16 , a first insulating layer 30 and a functional layer 40 .

[0076] The first substrate 10 has a first surface 10S1, a second surface 10S2 opposite to the first surface 10S1, a side surface 10S3 located between the first surface 10S1 and the second surface 10S2, and a chamfered surface 10S4 located between the second surface 10S2 and the side surface 10S3. Except that the chamfered surface 10S4 is an inclined plane with a single slope, the first substrate 10 of the electronic device 2 is substantially the same as the first substrate 10 of the electronic device 1, so it is not repeated here. Except that it does not have the chamfered surface 10S4, the second substrate 20 is substantially the same as the first substrate 10, so it is not repeated here.

[0077] The first conductive line 13, the first electronic component 12, the second electronic component 16, the first insulating layer 30 and the functional layer 40 of the electronic device 2 are disposed between the second substrate 20 and the first substrate 10. The first substrate 10 of the electronic device 2 is disposed between the electronic component 14 and the second substrate 20. The second conductive line 17 of the electronic device 2 is disposed between the electronic component 14 and the first substrate 10. The side conductive line 15 is disposed on the chamfered surface 10S4, the second surface 10S2 and the side surface 10S3 of the first substrate 10, and extends from the side surface 10S3 of the first substrate 10 to a portion of the side surface of the second substrate 20, as shown in FIG. Figure 4 As shown, but the present disclosure is not limited thereto. The first wire 13, the second wire 17, and the electronic component 14 of the electronic device 2 are substantially the same as the first wire 13, the second wire 17, and the electronic component 14 of the electronic device 1, so they are not repeated here. The first electronic component 12 and the second electronic component 16 of the electronic device 2 are substantially the same as the above-mentioned electronic components, so they are not repeated here. The first electronic component 12 can be the same as or different from the second electronic component 16. In some embodiments, the first electronic component 12 can be a thin film transistor (TFT), and the second electronic component 16 can be a micro light emitting diode (micro LED).

[0078] The first insulating layer 30 of the electronic device 2 may be formed on the first substrate 10 and cover the first wire 13, the first electronic component 12, and the second electronic component 16. The first insulating layer 30 may include a single layer or a multi-layer structure. The first insulating layer 30 may include but is not limited to optical adhesive, such as OCA (optical clear adhesive) or OCR (optical clear resin).

[0079] The functional layer 40 of the electronic device 2 may be formed on the first insulating layer 30, and the first insulating layer 30 may be located between the functional layer 40 and the first substrate 10. The functional layer 40 may include a single layer or a multilayer structure. In some embodiments, the functional layer 40 may include an optical layer, such as a polarizing layer, a filter layer, a reflective layer, a refractive layer, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the functional layer 40 may include a light conversion layer and a color filter layer, and the light conversion layer may include quantum dots, fluorescent powder, phosphorescent powder, etc.

[0080] Figure 5 FIG. 1 is a cross-sectional schematic diagram of an electronic device 3 according to an embodiment of the present disclosure. Figure 5As shown, the electronic device 3 of the present disclosure includes a first substrate 10, a first wire 13, a side wire 15, a second wire 17, a first electronic component 12, a second electronic component 16, and a first insulating layer 30. Except for further including the first insulating layer 30, the electronic device 3 of the present disclosure is substantially the same as the electronic device 1, so it is not repeated here.

[0081] The side wire 15 of the electronic device with the above structure can have a lower contact impedance and / or be less prone to breakage or damage through a special width design. Therefore, the electronic device of the present disclosure can have better reliability and / or electronic characteristics.

[0082] Another aspect of the present disclosure provides a method for manufacturing an electronic device. Figure 6 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0083] like Figure 6 As shown, the method for manufacturing an electronic device disclosed in the present invention includes: step S101 of providing a first substrate, wherein the first substrate has a first surface, a second surface opposite to the first surface, a side surface between the first surface and the second surface, and a chamfered surface between the second surface and the side surface; step S103 of forming a first wire on the first surface of the first substrate; step S105 of forming a second wire on the second surface of the first substrate; step S107 of forming a conductive layer on the side surface, the chamfered surface, and the second surface of the first substrate; and step S109 of patterning the conductive layer to form a side wire. The side wire formed in step S109 electrically connects the first wire and the second wire and has a first portion, a second portion, and a third portion. The first portion of the side wire is located on the side surface of the first substrate and has a first width W1, the second portion of the side wire is located on the chamfered surface and has a second width W2, and the third portion of the side wire is located on the second surface of the first substrate. The second wire has a third width W3. The second width W2 of the second portion of the side wire is less than or equal to the third width W3 of the second wire.

[0084] In the method for manufacturing an electronic device disclosed in the present invention, the first substrate 10 provided in step S101 is substantially the same as the first substrate 10 described in the above electronic devices 1 to 3, and thus will not be described in detail herein.

[0085] In the method for manufacturing an electronic device disclosed herein, the structures, materials, and forming methods of the first conductive lines 13 and the second conductive lines 17 formed in steps S101 and S103 are substantially the same as those of the first conductive lines 13 and the second conductive lines 17 in the electronic devices 1 to 3 , and thus are not described in detail herein.

[0086] In step S107, a conductive layer 15' is formed on the side surface 10S3, the chamfered surface 10S4, and the second surface 10S2 of the first substrate 10. The conductive layer 15' can be formed by various suitable processes of copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium, alloys thereof, any combination thereof, or other metal materials with good conductivity. The conductive layer 15' may include a single layer or a multilayer structure. In some embodiments, the conductive layer 15' may include a double-layer structure including different materials. In some embodiments, the conductive layer 15' may include a double-layer structure having the same or different materials formed by different process parameters. In some embodiments, the conductive layer 15' may have a double-layer structure including different materials formed by a sputtering process, but the present disclosure is not limited thereto.

[0087] FIG. 7A to FIG. 7C FIG. 1 is a partial plan view of an electronic device in step S109 of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 6 as well as FIG. 7A to FIG. 7C The step of patterning a conductive layer in a method for manufacturing an electronic device according to an embodiment of the present disclosure is further described.

[0088] like FIG. 7A to FIG. 7C As shown, the step S109 of patterning the conductive layer 15' includes forming a barrier layer 50, patterning the barrier layer 50, and etching the conductive layer 15' using the barrier layer 50 as a mask. The step of forming the barrier layer 50 includes coating the barrier layer 50 on the conductive layer 15' to completely cover the conductive layer 15', such as Fig. 7A As shown. The method for forming the barrier layer 50 may include but is not limited to screen printing, spraying, spin coating, and / or any combination thereof. The step of patterning the barrier layer 50 may include a photoresist layer forming process, an exposure process, and a development process. The photoresist layer may include a positive photoresist or a negative photoresist. In this embodiment, the photoresist layer includes a negative photoresist, but the present disclosure is not limited thereto. Examples of the exposure process may include but are not limited to a mask exposure process, a laser direct exposure (LDI) process, or a combination thereof. The barrier layer 50 after the exposure process may form a patterned barrier layer 50 after the development process, such as Figure 7B As shown. The step of patterning the barrier layer 50 may include one patterning step or multiple patterning steps. In some embodiments, the step of patterning the barrier layer 50 may include a first patterning step and a second patterning step. The first patterning step may include patterning the barrier layer 50 located on the side surface 10S3 and patterning a portion of the barrier layer 50 located on the chamfered surface 10S4. The second patterning step may include patterning the barrier layer 50 located on the second surface 10S2 and patterning another portion of the barrier layer 50 located on the chamfered surface 10S4. The patterned barrier layer 50 may be used as a mask to etch the conductive layer 15' to form the side conductive line 15, as shown. Figure 7CIn this embodiment, the barrier layer 50 has better adhesion and can form the side conductive line 15 with good quality.

[0089] FIG. 8A to FIG. 8C FIG. 1 is a partial plan view of an electronic device in step S109 of a method for manufacturing an electronic device according to an embodiment of the present disclosure. In this embodiment, except that the step of patterning the barrier layer 50 uses a laser patterning process instead of an exposure process and a development process, the remaining processes are the same as those of FIG. FIG. 7A to FIG. 7C The embodiments shown are substantially the same and are not described in detail herein. The laser patterning process may include laser direct imaging or laser ablation, but the present disclosure is not limited thereto. The laser used in the laser patterning process may be a UV, DUV, or green laser, but the present disclosure is not limited thereto. The use of a lower frequency laser in the laser patterning process may reduce thermal damage during the process and / or improve the adhesion of the barrier layer 50 to form a side conductive line 15 with good quality.

[0090] 9A to 9D FIG. 1 is a partial plan view of an electronic device in step S109 of a method for manufacturing an electronic device according to an embodiment of the present disclosure. In this embodiment, except for first forming an additional conductive layer 15" on the conductive layer 15', the rest of the process is the same as FIG. 7A to FIG. 7C The embodiments shown are substantially the same and will not be described in detail herein. In some embodiments, the process parameters for forming the additional conductive layer 15" may be different from the process parameters for forming the conductive layer 15'. The additional conductive layer 15" may adjust the quality of the subsequently formed side conductive line 15, or increase the process margin of the side conductive line 15. In addition, before the step of forming the additional conductive layer 15", the conductive layer 15' may be cleaned to remove foreign matter attached to the conductive layer 15', thereby improving the yield.

[0091] FIG. 10A to FIG. 10C It is a partial plan view of an electronic device in the step of patterning a conductive layer 15 ′ in a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0092] like FIG. 10A to FIG. 10CAs shown, the step of patterning the conductive layer 15' includes forming a barrier layer 50 on the side surface 10S3 and the second surface 10S4 of the first substrate 10, patterning the barrier layer 50, forming a conductive layer 15' on the patterned barrier layer 50, and patterning the conductive layer 15'. The step of forming the barrier layer 50 includes coating the barrier layer 50 on the first substrate 10 to completely cover the first substrate 10. The method for forming the barrier layer 50 may include, but is not limited to, screen printing, spraying, spin coating, and / or any combination thereof. The step of patterning the barrier layer 50 may include a photoresist layer forming process, an exposure process, and a development process. The barrier layer 50 may include a photoresist layer. The photoresist layer may include a positive photoresist or a negative photoresist. In this embodiment, the photoresist layer includes a positive photoresist, but the present disclosure is not limited thereto. The patterning barrier layer 50 may include an exposure process and a development process. Examples of the exposure process may include, but are not limited to, a mask exposure process, a laser direct exposure (LDI) process, or a combination thereof. The photoresist layer after the exposure process can form a patterned barrier layer 50 after the development process. The patterned barrier layer 50 is formed on the first substrate 10 and exposes the first substrate 10. Fig. 10A The conductive layer 15' is formed on the patterned barrier layer 50 and covers the barrier layer 50 and the first substrate 10, as shown. Fig. 10B Finally, the barrier layer 50 is removed to pattern the conductive layer 15' and form the side wire 15, as shown in FIG. Fig. 10C In this embodiment, the barrier layer 50 has better adhesion and can form a side wire 15 with good quality and / or the side wire 15 can be well adhered to the first substrate 10 to improve the reliability of the electronic device including the side wire 15.

[0093] FIG. 11A to FIG. 11C FIG. 1 is a partial plan view of an electronic device in the step of patterning the conductive layer 15' in a method for manufacturing an electronic device according to an embodiment of the present disclosure. In this embodiment, except that the step of patterning the barrier layer 50 uses a laser patterning process instead of an exposure process and a development process, the remaining processes are the same as those of FIG. FIG. 10A to FIG. 10C The embodiments shown are substantially the same and are not described in detail herein. The laser patterning process may include laser direct imaging or laser ablation, but the present disclosure is not limited thereto. The laser used in the laser patterning process may be a UV, DUV, or green laser, but the present disclosure is not limited thereto. In this embodiment, the better adhesion of the barrier layer 50 can form a side conductor 15 with good quality and / or the side conductor 15 can be well adhered to the first substrate 10 to improve the reliability of the electronic device including it. Furthermore, the use of a lower frequency laser in the laser patterning process can reduce thermal damage during the process and / or improve the adhesion of the barrier layer 50 to form a side conductor 15 with good quality.

[0094] The side wire 15 formed in the above-mentioned embodiments has a first portion 151 located on the side surface 10S3 of the first substrate 10, a second portion 153 located on the chamfered surface 10S4 of the first substrate 10, and a third portion 155 located on the second surface 10S2 of the first substrate 10. The second portion 153 of the side wire 15 has a second width W2 and the first portion 151 of the side wire 15 has a first width W1, as shown in FIGS. 7C to 8C. Fig. 11C In some embodiments, the second width W2 of the second portion 153 of the lateral conductive line 15 is less than or equal to the third width W3 of the second conductive line 17 , and the second width W2 of the second portion 153 of the lateral conductive line 15 is greater than the first width W1 of the first portion 151 of the lateral conductive line 15 .

[0095] In some embodiments, the second portion 153 of the side conductive line 15 may include a first sub-portion 1531 and a second sub-portion 1533 connected to the first sub-portion 1531. The first sub-portion 1531 is adjacent to the first portion 151, and the second sub-portion 1533 is adjacent to the third portion 155. The maximum width of the first sub-portion 1531 is different from the maximum width of the second sub-portion 1533. The maximum width here refers to the maximum width of the first sub-portion 1531 and the second sub-portion 1533 in a direction perpendicular to the connection direction of the first sub-portion 1531 and the second sub-portion 1533. In some embodiments, the width of the first sub-portion 1531 increases from the first portion 151 toward the second sub-portion 1533 and the width of the second sub-portion 1533 increases from the first sub-portion 1531 toward the third portion 155, as shown in FIGS. 8C and 11C. In some embodiments, the width difference between the second portion 153 of the side conductive line 15 and the first portion 151 of the side conductive line 15 is between 10 and 100 um, but the present disclosure is not limited thereto. In some embodiments, the width difference between the second portion 153 of the lateral conductive line 15 and the first portion 151 of the lateral conductive line 15 is between 15 and 95 um, 20 and 80 um, or 25 and 75 um.

[0096] The side wire 15 of the electronic device with the above structure can have a lower contact impedance and / or be less prone to breakage or damage through a special width design. Therefore, the electronic device of the present disclosure can have better reliability and / or electronic characteristics.

[0097] The features of the above-mentioned embodiments are helpful for those skilled in the art to understand the present invention. The features of the various embodiments can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above-mentioned embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be combined, changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. An electronic device, characterized in that: include: A first substrate having a first surface, a second surface opposite to the first surface, a side surface located between the first surface and the second surface, and a chamfer surface located between the second surface and the side surface; A first conductive line is disposed on the first surface; A side wire is disposed on the side surface, the chamfered surface and the second surface, and the side wire is electrically connected to the first wire, and the side wire has a first portion located on the side surface, a second portion located on the chamfered surface, and a third portion located on the second surface; as well as A second wire is disposed on the second surface and is electrically connected to the side wire; The width W2 of the second portion is less than or equal to the width W3 of the second conductive line.

2. The electronic device according to claim 1, wherein: The width W2 of the second portion is greater than the width W1 of the first portion.

3. The electronic device according to claim 1, wherein: The second portion of the side wire located on the chamfered surface comprises a first sub-portion and a second sub-portion, wherein the first sub-portion is adjacent to the first portion, the second sub-portion is adjacent to the third portion, and the width of the second sub-portion is greater than that of the first sub-portion.

4. The electronic device as claimed in claim 3, characterized in that: The chamfered surface has a first sub-surface, a second sub-surface and a third sub-surface, the first sub-surface is adjacent to the side surface, the third sub-surface is adjacent to the second surface, the second sub-surface is located between the first sub-surface and the third sub-surface, and the interface between the first sub-portion and the second sub-portion is located on the second sub-surface.

5. The electronic device according to claim 1, wherein: The width of the second portion of the side wire located on the chamfered surface gradually increases from the interface between the side surface and the chamfered surface toward the interface between the chamfered surface and the second surface.

6. The electronic device as claimed in claim 1, wherein: The width difference between the second portion and the first portion is between 10 and 100 um.

7. The electronic device according to claim 1, wherein: The width of the third portion is greater than the width W1 of the first portion and smaller than the width W3 of the second conductive line.

8. The electronic device as claimed in claim 1, wherein: The side conductive line includes a first conductive layer and a second conductive layer, and the second conductive layer is located on the first conductive layer.

9. The electronic device as claimed in claim 8, characterized in that: The first conductive layer and the second conductive layer include the same material.

10. The electronic device as claimed in claim 8, characterized in that The first conductive layer and the second conductive layer include different materials.

11. The electronic device according to claim 1, wherein: It further includes an electronic component disposed on the first surface, and the electronic component is electrically connected to the first wire.

12. A method for manufacturing an electronic device, characterized in that: include: Providing a first substrate, the first substrate having a first surface, a second surface opposite to the first surface, a side surface located between the first surface and the second surface, and a chamfer surface located between the second surface and the side surface; forming a first conductive line on the first surface; forming a second conductive line on the second surface; forming a conductive layer on the side surface, the chamfered surface, and the second surface; The conductive layer is patterned to form a side conductive line, and the side conductive line is electrically connected to the first conductive line and the second conductive line. The first portion of the side wire on the side surface has a first width W1, the second portion of the side wire on the chamfered surface has a second width W2, the second wire has a third width W3, and the second width W2 is less than or equal to the third width W3.

13. The method for manufacturing an electronic device according to claim 12, wherein: The second width W2 is greater than the first width W1.

14. The method for manufacturing an electronic device according to claim 12, wherein: The step of patterning the conductive layer comprises: forming a barrier layer on the conductive layer; patterning the barrier layer; and The conductive layer is etched using the barrier layer as a mask.

15. The method for manufacturing an electronic device according to claim 14, wherein: The method for patterning the barrier layer is laser direct imaging.

16. The method for manufacturing an electronic device according to claim 14, wherein: The method for patterning the barrier layer is laser ablation.

17. The method for manufacturing an electronic device according to claim 14, wherein: The steps of patterning the barrier layer include: patterning a portion of the barrier layer, the portion being located on the side surface and a portion of the chamfered surface; and Another portion of the barrier layer is patterned, where the other portion is located on the second surface and the chamfered surface of the other portion.

18. The method for manufacturing an electronic device according to claim 12, wherein: Before the step of forming a conductive layer on the side surface, the chamfered surface and the second surface, the method further includes: forming a barrier layer on the side surface, the chamfered surface and the second surface; and The barrier layer is patterned.

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