Printed circuit board and manufacturing method thereof

Abstract

The invention provides a printed circuit board and a method of manufacturing the same. The printed circuit board according to an embodiment may include: an insulating layer; a wiring layer embedded in the insulating layer; and a pad portion protruding from the insulating layer in a height direction, in which the pad portion may include a first portion and a second portion disposed below the first portion in the height direction, the second portion being disposed below the first portion in a plane direction perpendicular to the height direction. A width of the second portion of the pad portion may be larger than a width of the first portion of the pad portion, a side wall of the second portion may have a curved shape in the height direction, and the side wall of the second portion may be embedded in the insulating layer.

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board and a method for manufacturing the same. Background Art

[0002] As electronic devices in the field of information technology (IT), including mobile phones, become smaller, the size of metal posts formed on a printed circuit board on which electronic components are mounted is also decreasing.

[0003] As the size of metal posts on a printed circuit board decreases, the metal posts may become separated from the printed circuit board and lost. Summary of the invention

[0004] The present disclosure provides a printed circuit board and a method of manufacturing the same which are capable of preventing a pad portion from being separated from the printed circuit board and being lost.

[0005] However, the problems to be solved by the present disclosure are not limited to the above-mentioned problems, and various extensions can be made within the scope of the technical ideas included in the present disclosure.

[0006] According to one aspect of the present disclosure, a printed circuit board may include: an insulating layer; a wiring layer buried in the insulating layer; and a pad portion protruding from the insulating layer along a height direction, wherein the pad portion may include a first portion and a second portion arranged below the first portion along the height direction, and along a plane direction perpendicular to the height direction, a width of the second portion of the pad portion may be greater than a width of the first portion of the pad portion, a side wall of the second portion may have a curved shape along the height direction, and the side wall of the second portion may be buried in the insulating layer.

[0007] According to another aspect of the present disclosure, a printed circuit board may include: an insulating layer; a wiring layer buried in the insulating layer; and a pad portion protruding from the insulating layer along a height direction, wherein the pad portion may include a first portion, a second portion arranged below the first portion along the height direction and buried in the insulating layer, and a third portion arranged above the first portion along the height direction and protruding from the insulating layer, and along a plane direction perpendicular to the height direction, a width of the second portion of the pad portion may be greater than a width of the first portion of the pad portion, and along the plane direction, a width of the third portion of the pad portion may be greater than a width of the first portion of the pad portion.

[0008] At least a portion of the first portion of the pad portion may protrude from the insulating layer in the height direction.

[0009] The pad portion may further include a third portion disposed above the first portion in the height direction, and a width of the third portion of the pad portion may be greater than a width of the first portion of the pad portion in the plane direction.

[0010] At least a portion of the first portion and the third portion of the pad portion may protrude from the insulating layer in the height direction.

[0011] A side wall of the pad portion may have a curved shape in the height direction, and the side wall of the pad portion may have a shape recessed toward an inner side of the pad portion.

[0012] The insulating layer may have a via hole overlapping the pad portion, and the pad portion may contact a via hole disposed in the via hole.

[0013] The insulating layer may include a first insulating layer and a second insulating layer disposed below the first insulating layer, and the wiring layer may include a first wiring layer buried in the second insulating layer and a second wiring layer disposed below the second insulating layer.

[0014] The first insulating layer may have a first via hole, the second insulating layer may have a second via hole, the first wiring layer and the pad portion may be connected to each other through a first via hole provided in the first via hole, and the first wiring layer and the second wiring layer may be connected to each other through a second via hole provided in the second via hole.

[0015] The printed circuit board may further include a passivation layer disposed under the second insulating layer, wherein the passivation layer may expose at least a portion of the second wiring layer.

[0016] The printed circuit board may further include a surface treatment layer disposed over the pad portion.

[0017] A method for manufacturing a printed circuit board may include: stacking metal layers; forming a photoresist pattern on the metal layers; forming a pad portion by etching the metal layers using the photoresist pattern as an etching mask; stacking an insulating layer in which the pad portion is buried; forming a wiring layer buried in the insulating layer; and removing a portion of the insulating layer to expose a portion of the pad portion from the insulating layer along a height direction, wherein the pad portion may include a first portion and a second portion arranged below the first portion along the height direction, and along a plane direction perpendicular to the height direction, the width of the second portion of the pad portion may be formed to be larger than the width of the first portion of the pad portion, the side wall of the second portion may be formed to have a curved shape along the height direction, and the side wall of the second portion may be buried in the insulating layer.

[0018] According to the embodiments, a printed circuit board capable of preventing a pad portion from being separated from the printed circuit board and lost and a method of manufacturing the same may be provided.

[0019] However, it is easily understood that the effects of the embodiment are not limited to the above-mentioned effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a cross-sectional view of a printed circuit board according to an embodiment.

[0021] Figure 2 yes Figure 1 A magnified view of a portion of .

[0022] Figures 3 to 19 is a cross-sectional view illustrating a method of manufacturing a printed circuit board according to an embodiment.

[0023] Description of reference numerals: IL, IL1, IL2: insulation layer, ML, ML11, ML12, ML21, ML22: wiring layer, MP, MP1, MP2: pad part, VH, VH1, VH2: via holes, VL, VL1, VL2: vias, SC: Sidewall, PL: passivation layer. DETAILED DESCRIPTION

[0024] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily implement the present disclosure. However, the present disclosure can be implemented in various different forms and is not limited to the embodiments provided herein.

[0025] In order to clearly describe the present disclosure, parts irrelevant to the description will be omitted, and the same or similar components will be denoted by the same or similar reference numerals throughout the specification.

[0026] Furthermore, it should be understood that the drawings are provided only to allow easy understanding of the embodiments of the present disclosure, and the spirit of the present disclosure is not limited to the drawings, but the present disclosure includes all modifications, equivalents, and replacements included within the spirit and scope of the present disclosure.

[0027] In addition, for the convenience of description, the size (such as thickness) of each component shown in the drawings is arbitrarily shown, and the present disclosure is not necessarily limited to the shown size (such as thickness). In the drawings, the sizes of layers, films, panels, regions, etc. are exaggerated for clarity. In addition, in the drawings, the thickness of some layers and regions has been exaggerated for the convenience of explanation.

[0028] Furthermore, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be "directly on" the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements between them. Furthermore, when an element is referred to as being "on" a reference element, it can be located above or below the reference element, and is not necessarily "above" the reference element in a direction opposite to the direction of gravity.

[0029] In addition, unless explicitly described to the contrary, the words “comprising,” “including,” and “having” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0030] Furthermore, throughout the specification, the word “plan view” refers to a view when an object is viewed from the top, and the word “cross-sectional view” refers to a view of a cross section taken in a vertical direction when an object is viewed from the side.

[0031] Furthermore, throughout the specification, the term "connected" not only means that two or more elements are directly connected but also means that two or more elements are indirectly connected via another element, that two or more elements are physically and / or electrically connected, or that two or more elements are integrally formed although referred to by different names according to their positions or functions.

[0032] Hereinafter, embodiments in the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] Reference Figure 1 and Figure 2 , a printed circuit board according to an embodiment will be described. Figure 1 is a cross-sectional view of a printed circuit board according to an embodiment. Figure 2 yes Figure 1 A magnified view of a portion of .

[0034] Reference Figure 1 According to the present embodiment, the printed circuit board 100 may include: a plurality of stacked insulating layers IL; a plurality of wiring layers ML buried in the plurality of insulating layers IL or disposed on a portion of the plurality of insulating layers IL; a plurality of vias VL disposed in a plurality of through holes VH of the plurality of insulating layers IL; a plurality of pad portions MP; and a passivation layer PL.

[0035] The plurality of insulating layers IL may include a first insulating layer IL1 and a second insulating layer IL2 stacked along the height direction DRH. The first insulating layer IL1 and the second insulating layer IL2 are made of a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material (for example, a prepreg) prepared by impregnating a reinforcing material (such as glass fiber) with an inorganic filler in a thermosetting resin or a thermoplastic resin, but the embodiment is not limited thereto. In the illustrated embodiment, the plurality of insulating layers IL include a first insulating layer IL1 and a second insulating layer IL2, but the embodiment is not limited thereto and may further include an additional insulating layer. In addition, the plurality of insulating layers IL may further have a via hole VH stacked with the pad portion MP.

[0036] The plurality of wiring layers ML may include first and second wiring layers ML11 and ML12 buried in the second insulating layer IL2 , and third and fourth wiring layers ML21 and ML22 disposed on the second insulating layer IL2 .

[0037] The plurality of via holes VL may include a first via hole VL1 disposed in a first via hole VH1 formed in the first insulating layer IL1 and a second via hole VL2 disposed in a second via hole VH2 formed in the second insulating layer IL2. The plurality of via holes VL may contact the pad portion MP.

[0038] The plurality of pad parts MP may include a first pad part MP1 and a second pad part MP2 partially buried in the first insulating layer IL1 .

[0039] A portion of the first wiring layer ML11 and a portion of the first pad portion MP1 may be connected to each other through a first via hole VL1, and a portion of the first wiring layer ML11 and a portion of the third wiring layer ML21 may be connected to each other through a second via hole VL2. In the illustrated embodiment, the first via hole VL1 and the second via hole VL2 are shown to have a tapered shape whose diameter decreases upward along the height direction DRH, but the embodiment is not limited thereto.

[0040] Each of the plurality of wiring layers ML, the plurality of vias VL, and the plurality of pad parts MP may include a conductive metal, for example, may include copper, but the embodiment is not limited thereto.

[0041] The passivation layer PL is disposed under the second insulating layer IL2 and may expose at least a portion of the third wiring layer ML21 and at least a portion of the fourth wiring layer ML22. The passivation layer PL may be a photoresist layer, but the embodiment is not limited thereto.

[0042] The exposed portion of the third wiring layer ML21 and the exposed portion of the fourth wiring layer ML22 may be electrically connected to an external layer.

[0043] The surface finish layer SL may be located on the first pad portion MP1 and the second pad portion MP2 .

[0044] Reference Figure 2 Combined with Figure 1 , the pad part MP of the printed circuit board 100 according to the embodiment will be described in more detail.

[0045] The pad portion MP of the printed circuit board 100 according to the embodiment may have a side wall SC recessed toward the inside of the pad portion MP.

[0046] The plane direction DRW is perpendicular to the height direction DRH, and the pad portion MP may include: 1) a relatively narrow middle portion MPA (i.e., a first portion), and at least a portion of the middle portion MPA may protrude from the insulating layer IL (e.g., the first insulating layer IL1) in the height direction DRH; 2) a lower portion MPB1 (i.e., a second portion), connected to the middle portion MPA, disposed below the middle portion MPA along the height direction DRH, and having a width greater than that of the middle portion MPA in the plane direction DRW; and 3) an upper portion MPB2 (i.e., a third portion), disposed above the middle portion MPA, and having a width greater than that of the middle portion MPA in the plane direction DRW. The lower portion MPB1 may be buried in the insulating layer IL (e.g., the first insulating layer IL1), and the upper portion MPB2 may protrude from the insulating layer IL (e.g., the first insulating layer IL1) in the height direction DRH. Here, the width may refer to an average width.

[0047] The sidewall SC of the lower portion MPB1 having a width greater than that of the middle portion MPA may have a curved shape along the height direction DRH. Alternatively, at least one of the sidewall SC of the lower portion MPB1, the sidewall SC of the upper portion MPB2, and the sidewall SC of the middle portion MPA may have a curved shape along the height direction DRH. And the sidewall SC of the pad portion MP has a shape that is recessed toward the inside of the pad portion MP.

[0048] Among the sidewalls SC of the pad portion MP, at least the sidewalls SC of the lower portion MPB1 may be covered with the insulating layer IL (e.g., the first insulating layer IL1). That is, the sidewalls SC of the lower portion MPB1 may be buried in the first insulating layer IL1. In addition, among the sidewalls SC of the pad portion MP, the sidewalls SC of the lower portion MPB1 and a portion of the sidewalls SC of the intermediate portion MPA may be covered with the insulating layer IL (e.g., the first insulating layer IL1).

[0049] According to the printed circuit board 100 according to the embodiment, the pad portion MP includes: a relatively narrow middle portion MPA having a side wall SC recessed toward the inside of the pad portion MP; a lower portion MPB1 connected to the middle portion MPA, disposed below the middle portion MPA along the height direction DRH and having a width greater than the width of the middle portion MPA; and an upper portion MPB2 connected to the middle portion MPA, disposed above the middle portion MPA along the height direction DRH and having a width greater than the width of the middle portion MPA, and the side wall SC of the lower portion MPB1 may be covered with the first insulating layer IL1. In this way, the lower portion MPB1 of the pad portion MP having a relatively wide width is covered with the insulating layer IL (e.g., the first insulating layer IL1) and protected by the insulating layer IL (e.g., the first insulating layer IL1), thereby preventing the pad portion MP from being separated from the printed circuit board 100 and lost.

[0050] Therefore, the contact characteristics of the printed circuit board 100 and the additional layer connected through the pad portion MP of the printed circuit board 100 may be improved.

[0051] Will refer to Figures 3 to 19 Combined with Figure 1 and Figure 2 A method of manufacturing a printed circuit board according to an embodiment is described. Figures 3 to 19 is a cross-sectional view illustrating a method of manufacturing a printed circuit board according to an embodiment.

[0052] Reference Figure 3 , a barrier layer BL and a copper foil layer SD are sequentially formed on both surfaces of a carrier substrate CS in a height direction DRH, and the carrier substrate CS includes a core CL and a thin metal layer MS stacked on both surfaces of the core CL in the height direction DRH.

[0053] Reference Figure 4 The first metal layer MLL is formed on the copper foil layer SD disposed on both sides of the carrier substrate CS in the height direction DRH. The first metal layer MLL may be formed on the copper foil layer SD by plating, but the embodiment is not limited thereto.

[0054] Reference Figure 5 , stacking a first photoresist layer PLL on the first metal layer MLL disposed on both sides of the carrier substrate CS in the height direction DRH, and as Figure 6 As shown in , a plurality of photoresist patterns PLP may be formed at locations where a plurality of pad parts MP are to be formed.

[0055] Reference Figure 7, the first metal layer MLL is etched using the plurality of photoresist patterns PLP as an etching mask to form a first pad portion MP1 and a second pad portion MP2. In this case, the etching conditions may be adjusted so that the plurality of pad portions MP including the first pad portion MP1 and the second pad portion MP2 have sidewalls SC recessed toward the inner side of the pad portion MP.

[0056] like Figure 1 and Figure 2 As shown in the figure, the first pad portion MP1 and the second pad portion MP2 may include: a relatively narrow middle portion MPA; a lower portion MPB1, connected to the middle portion MPA, disposed below the middle portion MPA along the height direction DRH and having a width greater than that of the middle portion MPA; and an upper portion MPB2, connected to the middle portion MPA, disposed above the middle portion MPA along the height direction DRH and having a width greater than that of the middle portion MPA.

[0057] like Figure 8 As shown in , the plurality of photoresist patterns PLP may be removed.

[0058] like Fig. 9 As shown in FIG, the first insulating layer IL1 may be stacked so that a plurality of pad portions MP including a first pad portion MP1 and a second pad portion MP2 are buried.

[0059] like Fig.10 As shown in FIG. 1 , a first via hole VH1 exposing at least a portion of the first pad portion MP1 may be formed in the first insulating layer IL1 .

[0060] like Fig.11 As shown in FIG. 1 , a first via hole VL1 is formed in a first via hole VH1 of a first insulating layer IL1 , and a first wiring layer ML11 connected to the first via hole VL1 and a second wiring layer ML12 not connected to the first via hole VL1 may be formed on the first insulating layer IL1 .

[0061] like Fig.12 As shown in FIG, the second insulating layer IL2 may be stacked on the first insulating layer IL1 so that the first wiring layer ML11 and the second wiring layer ML12 are buried.

[0062] like Fig.13 As shown in FIG. 1 , a second via hole VH2 exposing at least a portion of the first wiring layer ML11 may be formed in the second insulating layer IL2 .

[0063] like Fig.14 As shown in FIG. 1 , a second via hole VL2 may be formed in the second via hole VH2 of the second insulating layer IL2 , and a third wiring layer ML21 connected to the second via hole VL2 and a fourth wiring layer ML22 not connected to the second via hole VL2 may be formed on the second insulating layer IL2 .

[0064] like Fig.15 As shown in FIG. 1 , a passivation layer PL may be formed on the second insulating layer IL2 to expose a portion of the third wiring layer ML21 and a portion of the fourth wiring layer ML22 .

[0065] like Fig.16 As shown in , the substrate portion SUB is peeled off from both sides of the carrier substrate CS.

[0066] Hereinafter, one substrate portion SUB peeled off from one side of the carrier substrate CS will be described.

[0067] like Fig.17 As shown in FIG. 1 , the barrier layer BL is removed from the substrate portion SUB, and as shown in FIG. Fig.18 As shown in , the copper foil layer SD is removed.

[0068] like Fig.19 As shown in , a portion of the first insulating layer IL1 may be removed so that the first insulating layer IL1 may cover the relatively wide lower sidewall SC of each of the first pad portion MP1 and the second pad portion MP2, and may not cover the upper sidewall SC of each of the first pad portion MP1 and the second pad portion MP2.

[0069] More specifically, the pad portion MP may include a relatively narrow middle portion MPA having an inwardly recessed sidewall SC, and a lower portion MPB1 and an upper portion MPB2 connected to the middle portion MPA and disposed below and above the middle portion MPA along the height direction DRH, respectively, and the lower portion MPB1 of the pad portion MP having a relatively wider width may be covered with an insulating layer IL (e.g., a first insulating layer IL1).

[0070] Then, if Figure 1 As shown in FIG. 1 , a surface treatment layer SL may be formed on the surface of the first pad portion MP1 and the surface of the second pad portion MP2 .

[0071] The surface finishing layer SL may be formed by any one of electroplating gold, immersion gold, organic solderability preservative (OSP), immersion tin, immersion silver, electroless nickel immersion gold (ENIG) (electroless nickel / replacement gold plating), direct immersion gold (DIG plating), and hot air solder leveling (HASL).

[0072] In this way, according to the method for manufacturing a printed circuit board according to an embodiment, the pad portion MP may include a relatively narrow middle portion MPA having an inwardly recessed side wall SC, and a lower portion MPB1 and an upper portion MPB2 connected to the middle portion MPA and respectively disposed below and above the middle portion MPA along the height direction DRH, and the lower portion MPB1 having a relatively wider width of the pad portion MP is formed to be covered with an insulating layer IL (e.g., a first insulating layer IL1), thereby preventing the pad portion MP from being separated from the printed circuit board 100 and being lost, and improving the contact characteristics of the printed circuit board 100 with an additional layer connected through the pad portion MP of the printed circuit board 100.

[0073] Although the preferred embodiments have been described above, the present disclosure is not limited thereto, and various modifications can be made within the scope of the present disclosure, and the various modifications naturally also fall within the scope of the present disclosure.

Claims

1. A printed circuit board, comprising: Insulation layer; A wiring layer, buried in the insulating layer; as well as a pad portion protruding from the insulating layer in a height direction, The pad portion includes a first portion and a second portion disposed below the first portion in the height direction. In a plane direction perpendicular to the height direction, a width of the second portion of the pad portion is greater than a width of the first portion of the pad portion, The side wall of the second portion has a curved shape along the height direction, and The sidewall of the second portion is buried in the insulating layer.

2. The printed circuit board according to claim 1, wherein: The pad portion further includes a third portion disposed above the first portion in the height direction, and In the planar direction, the third portion of the pad portion has a width greater than a width of the first portion of the pad portion.

3. The printed circuit board according to claim 2, wherein: At least a portion of the first portion and the third portion of the pad portion protrude from the insulating layer in the height direction.

4. The printed circuit board according to claim 3, wherein: The side wall of the pad portion has a curved shape along the height direction, and the side wall of the pad portion has a shape recessed toward an inner side of the pad portion.

5. The printed circuit board according to claim 1, wherein: The insulating layer has a via hole overlapping the pad portion, and The pad portion contacts a via hole provided in the via hole.

6. The printed circuit board according to claim 1, wherein: The insulating layer includes a first insulating layer and a second insulating layer disposed below the first insulating layer, The wiring layer includes a first wiring layer buried in the second insulating layer and a second wiring layer provided below the second insulating layer, The first insulating layer has a first via hole, The second insulating layer has a second via hole, The first wiring layer and the pad portion are connected to each other through a first via hole provided in the first via hole, and The first wiring layer and the second wiring layer are connected to each other through a second via hole provided in the second via hole.

7. The printed circuit board according to claim 6, further comprising: A passivation layer is disposed below the second insulating layer, The passivation layer exposes at least a portion of the second wiring layer.

8. The printed circuit board according to claim 7, further comprising: The surface treatment layer is arranged above the pad portion.

9. The printed circuit board according to claim 1, wherein: A side wall of the pad portion has a curved shape along the height direction, and the side wall of the pad portion has an inwardly recessed shape.

10. A printed circuit board, comprising: Insulation layer; A wiring layer, buried in the insulating layer; as well as a pad portion protruding from the insulating layer in a height direction, The pad portion includes a first portion, a second portion disposed below the first portion in the height direction and buried in the insulating layer, and a third portion disposed above the first portion in the height direction and protruding from the insulating layer. In a plane direction perpendicular to the height direction, a width of the second portion of the pad portion is greater than a width of the first portion of the pad portion, and In the planar direction, the third portion of the pad portion has a width greater than a width of the first portion of the pad portion.

11. The printed circuit board according to claim 10, wherein: A side wall of the pad portion has a curved shape along the height direction, and the side wall of the pad portion has an inwardly recessed shape.

12. A method for manufacturing a printed circuit board, comprising: Stacking metal layers; forming a photoresist pattern on the metal layer; forming a pad portion by etching the metal layer using the photoresist pattern as an etching mask; stacking an insulating layer to bury the pad portion; forming a wiring layer buried in the insulating layer; as well as removing a portion of the insulating layer so that a portion of the pad portion is exposed from the insulating layer in a height direction, The pad portion includes a first portion and a second portion disposed below the first portion in the height direction. In a plane direction perpendicular to the height direction, the width of the second portion of the pad portion is formed to be larger than the width of the first portion of the pad portion, The side wall of the second portion is formed to have a curved shape along the height direction, and The sidewall of the second portion is buried in the insulating layer.

13. The manufacturing method according to claim 12, wherein: At least a portion of the first portion of the pad portion protrudes from the insulating layer in the height direction.

14. The manufacturing method according to claim 12, wherein: The pad portion further includes a third portion disposed above the first portion in the height direction, and The third portion of the pad portion is formed to have a width greater than a width of the first portion of the pad portion in the planar direction.

15. The manufacturing method according to claim 14, wherein: At least a portion of the first portion and the third portion of the pad portion protrude from the insulating layer in the height direction.

16. The manufacturing method according to claim 15, wherein: The side wall of the pad portion has a curved shape in the height direction, and the side wall of the pad portion is formed to have a shape recessed toward an inner side of the pad portion.

17. The manufacturing method according to claim 12, further comprising: forming a via hole in the insulating layer to overlap the pad portion; as well as A via hole is formed in contact with the pad portion and disposed within the via hole.

18. The manufacturing method according to claim 12, wherein: The insulating layer includes a first insulating layer and a second insulating layer disposed below the first insulating layer, and In the step of forming the wiring layer, a first wiring layer buried in the second insulating layer is formed and a second wiring layer provided below the second insulating layer is formed.

19. The manufacturing method according to claim 18, further comprising: forming a first via hole in the first insulating layer; forming a second via hole in the second insulating layer; connecting the first wiring layer to the pad portion and forming a first via hole disposed in the first via hole; as well as The first wiring layer is connected to the second wiring layer and a second via hole provided in the second via hole is formed.

20. The manufacturing method according to claim 12, wherein: A side wall of the pad portion has a curved shape in the height direction, and the side wall of the pad portion is formed to have an inwardly recessed shape.

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