Static random access memory and preparation method thereof
By setting a bias electrode covering the upper surface of the first gate structure and the upper surface of the buffer in the static random memory, the problem of leakage easily in the edge area of the static random memory is solved, and the effect of reducing leakage risk and improving device performance is achieved.
Patent Information
- Application Number
- CN202510049030.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2025-05-13
AI Technical Summary
The edge area of the static random memory is prone to leakage from the well region electrode to the drain, affecting device performance.
A bias electrode covering the upper surface of the first gate structure and the upper surface of the buffer region away from the cell region is provided in the static random memory to ensure that when the contact region deviates to the buffer, the potentials of the first gate conductive layer, the well region, the contact region deviating to the buffer region and the doped region remain flat, so that when the static random memory is silent, the conductive channel directly below the first gate structure is turned off to avoid leakage.
It effectively reduces the risk of leakage of the device, improves the performance of the device, and improves the interlaced deviation coupling balance forming the contact area, without increasing the area of the device, and the process is simple.
Smart Images
Figure CN119997498A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a static random access memory and a preparation method thereof. Background Art
[0002] With the continuous development of microelectronics technology, memory has shown a development trend of high integration, fast speed and low power consumption. Static Random-Access Memory (abbreviated as SRAM) is a kind of high-speed memory. It is widely used because it can save the data stored in the internal standard without refreshing the circuit. At present, in static random access memory, the edge cells of the static random access memory cell array are usually used to set the well electrode (WellPickup) of the well area, and are also used to avoid the influence of graphic mutation on the internal array. Due to the size requirements of the device, the area of the edge cells needs to be minimized. For the edge cells of static random access memory, a shallow trench isolation structure (STI) is usually used to isolate the P+ region in the edge cell close to the cell region and the N+ contact region away from the cell region and electrically connected to the well region electrode. In the process of making the N+ contact region, due to the overlay offset, the N+ contact region deviates to the P+ region of the edge cell. In order to save the area of the edge cell, the gate in the edge cell is not biased, resulting in the formation of a leakage path between the source and drain of the edge cell. In particular, when the SRAM enters the sleep mode, that is, the drain voltage driving the SRAM to work is lower than the normal working voltage, leakage from the well region electrode to the drain will be formed, affecting the performance of the device.
[0003] Therefore, there is an urgent need to find a static random access memory that can improve the leakage of the edge area of the static random access memory. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a static random access memory and a preparation method thereof, so as to solve the problem that leakage from the well electrode to the drain is easily generated in the edge area of the static random access memory in the prior art.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides a static random access memory, comprising:
[0006] A semiconductor structure, comprising an adjacent cell region and an edge region, wherein the edge region comprises a buffer region and a lead-out region located on a side of the buffer region away from the cell region, and a first conductive type well region is provided on the upper surface of the cell region and the edge region;
[0007] A first gate structure is located on the upper surface of the well region in the buffer region and the area directly below the first gate structure is adjacent to the cell region;
[0008] A second gate structure, located on an upper surface of the well region in the cell region and spaced apart from the first gate structure by a preset distance;
[0009] A second conductive type doped region is located on an upper surface layer of the well region on a side of the first gate structure away from the cell region;
[0010] A second conductive type source region and a second conductive type drain region are respectively located on the upper surface layer of the well region at two opposite sides of the second gate structure, and the drain region near the edge of the cell region is adjacent to the buffer region;
[0011] A first conductive type contact region, at least located on the upper surface layer of the lead-out region;
[0012] a bias electrode, covering the well region on a side of the first gate structure away from the cell region and an upper surface of the first gate structure and being electrically connected to the first gate structure and the doped region respectively;
[0013] A lead-out electrode electrically connected to the contact area on the upper surface of the lead-out area;
[0014] The source electrode, the drain electrode and the gate electrode are electrically connected to the source region, the drain region and the second gate structure respectively.
[0015] Optionally, the semiconductor structure further includes an isolation structure embedded in the well region between the buffer region and the lead-out region.
[0016] Optionally, the isolation structure includes an isolation trench and an isolation filling layer.
[0017] Optionally, the first gate structure includes a first gate dielectric layer and a first gate conductive layer stacked in sequence, the second gate structure includes a second gate dielectric layer and a second gate conductive layer stacked in sequence, the gate is electrically connected to the second gate conductive layer, and the bias electrode is electrically connected to the first gate conductive layer.
[0018] Optionally, the doping concentration of the doping region is the same as that of the source region and the drain region.
[0019] Optionally, the contact region extends to the buffer region close to a side wall of the cell region.
[0020] Optionally, the edge of the bias electrode further extends to the upper surface of the contact area on the upper surface layer of the buffer zone and is electrically connected to the portion of the contact area.
[0021] Optionally, the bias electrode also covers a side wall of the first gate structure away from the cell region.
[0022] Optionally, an interlayer dielectric layer is further provided in the static random access memory, wherein the interlayer dielectric layer is located directly above the semiconductor structure and covers the exposed surface of the bias electrode, the source electrode penetrates the interlayer dielectric layer and is electrically connected to the source region, the drain electrode penetrates the interlayer dielectric layer and is electrically connected to the drain region, the gate penetrates the interlayer dielectric layer and is electrically connected to the second gate structure, and the lead-out electrode penetrates the interlayer dielectric layer and is electrically connected to the contact region.
[0023] The present invention also provides a method for preparing a static random access memory, comprising the following steps:
[0024] A semiconductor structure is provided, comprising an adjacent cell region and an edge region, wherein the edge region comprises a buffer region and a lead-out region located on a side of the buffer region away from the cell region, and a first conductive type well region is provided on the upper surface of the cell region and the edge region;
[0025] forming a first gate structure and a second gate structure located on the upper surface of the well region, wherein the first gate structure is located above the buffer region and the area directly below the first gate structure is adjacent to the cell region, and the second gate structure is located above the cell region and spaced apart from the first gate structure;
[0026] Forming a second conductive type doped region located on the upper surface of the well region in the buffer region, a second conductive type drain region and a second conductive type source region located on the upper surface of the well region at two opposite sides of the second gate structure, and at least a first conductive type contact region located on the upper surface of the lead-out region, wherein the doped region is located on a side of the first gate structure away from the cell region, and the drain region close to the edge of the cell region is adjacent to the buffer region;
[0027] forming a bias electrode covering the well region on a side of the first gate structure away from the cell region and an upper surface of the first gate structure and electrically connected to the first gate structure and the doped region respectively;
[0028] An extraction electrode electrically connected to the contact area on the upper surface of the extraction area, a source electrode electrically connected to the source area, a drain electrode electrically connected to the drain area, and a gate electrode electrically connected to the second gate structure are formed.
[0029] As described above, the static random access memory and the preparation method thereof of the present invention change the structure of the device, and set a bias electrode in the device to cover the upper surface of the first gate structure and the upper surface of the buffer zone on the side of the first gate structure away from the cell region. When the contact area deviates to the buffer zone, the bias electrode is electrically connected to the first gate conductive layer, the doped area and the contact area respectively, so that the potentials of the first gate conductive layer, the well area, the contact area deviated to the buffer zone and the doped area are kept equal. When the static random access memory is silent, the conductive channel directly below the first gate structure is turned off, thereby avoiding leakage of the device through the contact area, the doped area and the well area below the first gate structure, reducing the leakage risk of the device, improving the performance of the device, and improving the overlay deviation coupling margin of the contact area without causing an increase in the area of the edge area. The process is simple and has high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic cross-sectional structure diagram of the static random access memory of the present invention is shown.
[0031] Figure 2 Display as Figure 1 Schematic diagram of the top structure of the static random access memory.
[0032] Figure 3 Another cross-sectional structural schematic diagram of the static random access memory of the present invention is shown.
[0033] Figure 4 Shown is a process flow chart of a method for preparing a static random access memory of the present invention.
[0034] Figure 5 It is a schematic cross-sectional structure diagram of the semiconductor structure of the static random access memory of the present invention.
[0035] Figure 6 It is a schematic cross-sectional structure diagram of the static random access memory of the present invention after forming the first gate structure and the second gate structure.
[0036] Figure 7 It is a schematic diagram of the cross-sectional structure of the static random access memory of the present invention after forming the source region, the drain region and the doping region.
[0037] Figure 8 It is a schematic diagram showing the cross-sectional structure of the static random access memory of the present invention after the contact region is formed.
[0038] Fig. 9 It is a schematic diagram showing the cross-sectional structure of the static random access memory of the present invention after the bias electrode is formed.
[0039] Description of Figure Numbers
[0040] 1 Semiconductor structure
[0041] 10 Well region
[0042] 11 Cell area
[0043] 12. Fringe
[0044] 13 Buffer
[0045] 14 Lead-out area
[0046] 15 Source area
[0047] 16 Drain area
[0048] 17 Doping region
[0049] 18 Contact area
[0050] 19 Isolation Structure
[0051] 2 First Gate Structure
[0052] 21 Second Gate Structure
[0053] 3 Bias electrode
[0054] 4 Interlayer dielectric layer
[0055] 5 Source
[0056] 6 Drain
[0057] 7. Extraction electrode
[0058] 8 Gate DETAILED DESCRIPTION
[0059] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0060] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0061] Embodiment 1
[0062] This embodiment provides a static random access memory, such as Figure 1 , Figure 2 and Figure 3 As shown in FIG. 1 , they are a schematic diagram of a cross-sectional structure of the static random access memory, Figure 1 A schematic diagram of the top structure of a static random access memory and another schematic diagram of the cross-sectional structure of the static random access memory, comprising a semiconductor structure 1, a first gate structure 2, a second gate structure 21, a first conductive type doped region 17, a second conductive type source region 15, a second conductive type drain region 16, a first conductive type contact region 18, an extraction electrode 7, a source 5, a drain 6 and a gate 8, wherein the semiconductor structure 1 comprises an adjacent cell region 11 and an edge region 12, the edge region 12 comprises a buffer region 13 and an extraction region 14 located on a side of the buffer region 13 away from the cell region 11, and a first conductive type well region 10 is provided on the upper surface of the cell region 11 and the edge region 12; the first gate structure 2 is located on the upper surface of the well region 10 in the buffer region 13 and the area directly below it is adjacent to the cell region; the second gate structure 21 is located on the upper surface of the well region 10 in the cell region 11 and is spaced a preset distance from the first gate structure 2; the doped region 17 is located on the upper surface of the well region 10 on the side of the first gate structure 2 away from the cell region 11; the source region 15 and the drain region 16 are respectively located on the upper surface of the well region 10 on the opposite sides of the second gate structure 21, and the drain region 16 close to the edge of the cell region 11 is adjacent to the buffer region 13; the contact region 18 is at least located on the upper surface of the lead-out region 14; the bias electrode 3 covers the well region 10 on the side of the first gate structure 2 away from the cell region 11 and the upper surface of the first gate structure 2 and is electrically connected to the first gate structure 2 and the doped region 17 respectively; the lead-out electrode 7 is electrically connected to the contact region 18 on the upper surface of the lead-out region 14, and the source 5, the drain 6 and the gate 8 are electrically connected to the source region 15, the drain region 16 and the second gate structure 21 respectively.
[0063] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.
[0064] Specifically, the semiconductor structure 1 usually includes multiple film layers and multiple doped well regions 10. The well region 10 in the cell region 11 is connected to the well region 10 in the edge region 12. The size, shape and structure of the well region 10 can be selected according to actual conditions.
[0065] As an example, the semiconductor structure 1 further includes an isolation structure 19 embedded in the well region 10 between the buffer region 13 and the lead-out region 14 , that is, the buffer region 13 and the lead-out region 14 are isolated from each other by the isolation structure 19 .
[0066] Specifically, the side of the buffer region 13 away from the cell region 11 is adjacent to the lead-out region 14 and the side close to the cell region 11 is adjacent to the cell region 11. The isolation structure 19 is used to isolate the contact region 18 and the doping region 17 formed subsequently to reduce the leakage current of the device.
[0067] As an example, the isolation structure 19 includes an isolation trench and an isolation filling layer.
[0068] Specifically, the upper surface of the isolation filling layer is flush with the upper surface of the well region 10 (i.e., the upper surface of the semiconductor structure 1), and the opening size, opening shape and depth of the isolation trench can be selected according to actual conditions while ensuring the performance of the static random access memory. The depth here refers to the distance between the bottom surface of the isolation trench and the opening of the isolation trench.
[0069] Specifically, the material of the isolation filling layer includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.
[0070] Specifically, while ensuring device performance, the size and shape of the cell area 11 can be selected according to actual conditions; the size and shape of the edge area 12 can be selected according to actual conditions; the size and shape of the buffer area 13 can be selected according to actual conditions; and the size and shape of the lead-out area 14 can be selected according to actual conditions.
[0071] Specifically, the well region 10 is usually used to form a conductive channel of a MOS device in the cell region 11. Under the condition of ensuring the performance of the device, the size, shape, and thickness of the well region 10 can be selected according to actual conditions.
[0072] It should be noted that, usually, the cell area 11 forms a corresponding MOS device cell in a static random access memory, and the lead-out area 14 in the edge area 12 is an electrical connection area for the lead-out electrode 7 that applies voltage to the well area 10. At the same time, the buffer area 13 in the edge area 12 is used to improve the tolerance of process errors in the device manufacturing process and improve the yield of the device.
[0073] As an example, the first gate structure 2 includes a first gate dielectric layer and a first gate conductive layer stacked in sequence, the second gate structure 21 includes a second gate dielectric layer and a second gate conductive layer stacked in sequence, the gate 8 is electrically connected to the second gate conductive layer, and the bias electrode 3 is electrically connected to the first gate conductive layer.
[0074] Specifically, the second gate structure 21 is used to control the opening and closing of the conductive channel of the MOS device in the cell region 11 , and the first gate structure 2 is a dummy gate. Usually, the first gate structure 2 and the second gate structure 21 have the same size and shape.
[0075] Specifically, under the condition of ensuring the performance of the device, the thickness of the first gate dielectric layer and the second gate dielectric layer can be selected according to actual conditions.
[0076] Specifically, the material of the first gate dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials; the material of the second gate dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.
[0077] Specifically, the material of the first gate conductive layer includes polysilicon or other suitable conductive materials; the material of the second gate conductive layer includes polysilicon or other suitable conductive materials.
[0078] Specifically, while ensuring device performance, the distance between the first gate structure 2 and the second gate structure 21 can be selected according to actual conditions.
[0079] As an example, the doping concentration of the doping region 17 is the same as that of the source region 15 and the drain region 16 .
[0080] It should be noted that, usually, the doped region 17, the source region 15 and the drain region 16 are formed simultaneously, and the bottom surfaces of the doped region 17, the source region 15 and the drain region 16 are higher than the bottom surface of the isolation structure 19. They can also be formed in steps while ensuring the device performance.
[0081] Specifically, while ensuring device performance, the size, shape and thickness of the doped region 17 can be selected according to actual conditions; the size, shape and thickness of the source region 15 can be selected according to actual conditions; the size, shape and thickness of the drain region 16 can be selected according to actual conditions. The thickness here refers to the distance between the upper surface and the lower surface of each region.
[0082] Specifically, the contact region 18 is used to achieve ohmic contact between the well region 10 and the lead-out electrode 7. The bottom surfaces of the contact region 18 and the doping region 17 are higher than the bottom surface of the isolation structure 19. While ensuring device performance, the doping concentration, size, shape and thickness of the contact region 18 can be selected according to actual conditions.
[0083] As an example, the contact region 18 extends to the buffer region 13 close to the sidewall of the cell region 11 .
[0084] Specifically, the deviation of the contact region 18 to the buffer region 13 is usually caused by a photolithography process error during the formation of the contact region 18 , and at the upper surface layer of the buffer region 13 , the contact region 18 is adjacent to the sidewall of the doped region 17 .
[0085] It should be noted that, generally, the size of the contact area 18 in the buffer region 13 is related to the error of the photolithography process, which is not limited here.
[0086] As an example, the edge of the bias electrode 3 also extends to the upper surface of the contact area 18 on the upper surface of the buffer zone 13 and is electrically connected to the part of the contact area 18, that is, when the contact area 18 deviates to the upper surface of the buffer zone 13, the edge of the bias electrode 3 close to the lead-out area 14 extends to the upper surface of the part of the contact area 18 and is electrically connected to the contact area 18 below it.
[0087] Specifically, the bias electrode 3 usually covers the upper surface of the first gate conductive layer in the first gate structure 2 and is electrically connected to the first gate conductive layer. The bias electrode 3 is made of titanium nitride, tantalum nitride, titanium, tantalum, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.
[0088] As an example, the bias electrode 3 also covers the sidewall of the first gate structure 2 away from the cell region 11 .
[0089] Specifically, since the bias electrode 3 covers the upper surface of the first gate conductive layer, the side wall of the first gate structure 2 and the upper surface of the buffer region 13 on the side of the first gate structure 2 away from the cell region 11, when the contact region 18 deviates to the buffer region 13, the bias electrode 3 is electrically connected to the first gate conductive layer, the doped region 17 and the contact region 18 deviating to the buffer region 13, and the contact region 18 deviating to the buffer region 13 has the same conductivity type as the well region 10, thereby making the potential of the well region 10, the first gate conductive layer, the doped region 17 and the contact region 18 deviating to the buffer region 13 the same.
[0090] As an example, the static random access memory is also provided with an interlayer dielectric layer 4, which is located directly above the semiconductor structure 1 and covers the exposed surface of the bias electrode 3, the source electrode 5 penetrates the interlayer dielectric layer 4 and is electrically connected to the source region 15, the drain electrode 6 penetrates the interlayer dielectric layer 4 and is electrically connected to the drain region 16, the gate 8 penetrates the interlayer dielectric layer 4 and is electrically connected to the second gate structure 21, and the lead electrode 7 penetrates the interlayer dielectric layer 4 and is electrically connected to the contact region 18.
[0091] It should be noted that when the bias electrode 3 is formed based on an insulating layer that does not need to be removed and covers the exposed upper surface of the semiconductor structure 1 and the exposed surfaces of the first gate structure 2 and the second gate structure 21, the interlayer dielectric layer 4 covers the upper surface of the insulating layer. When the bias electrode 3 is made based on a photoresist layer that needs to be stripped off later, the interlayer dielectric layer 4 also covers the exposed upper surface of the semiconductor structure 1 and the exposed surfaces of the first gate structure 2 and the second gate structure 21.
[0092] Specifically, the interlayer dielectric layer 4 is used to insulate the electrodes of the device in the cell region 11 and the extraction electrode 7 electrically connected to the well region 10, and is also used to protect the front structure of the device.
[0093] Specifically, under the condition of ensuring the device performance, the thickness of the interlayer dielectric layer 4 can be selected according to actual conditions.
[0094] Specifically, the material of the interlayer dielectric layer 4 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.
[0095] It should be noted that, usually, the interlayer dielectric layer 4 is provided with a first contact hole, a second contact hole, a third contact hole and a fourth contact hole. The first contact hole penetrates the interlayer dielectric layer 4 and the bottom surface exposes the source region 15 on the upper surface of the cell region 11. The second contact hole penetrates the interlayer dielectric layer 4 directly above the second gate structure 21 and the bottom surface exposes the second gate conductive layer. The third contact hole penetrates the interlayer dielectric layer 4 and the bottom surface exposes the drain region 16 on the upper surface of the cell region 11. The fourth contact hole penetrates the interlayer dielectric layer 4 directly above the lead-out region 14 and the bottom surface exposes the contact region 18 on the upper surface of the lead-out region 14. The source electrode 5 fills the first contact hole and is electrically connected to the source region 15. The gate electrode 8 fills the second contact hole and is electrically connected to the second gate conductive layer. The drain electrode 6 fills the third contact hole and is electrically connected to the drain region 16. The lead-out electrode 7 fills the fourth contact hole and is electrically connected to the contact region 18 on the upper surface of the lead-out region 14.
[0096] Specifically, while ensuring device performance, the opening size and opening shape of the first contact hole can be selected according to actual conditions; the opening size and opening shape of the second contact hole can be selected according to actual conditions; the opening size and opening shape of the third contact hole can be selected according to actual conditions; the opening size and opening shape of the fourth contact hole can be selected according to actual conditions.
[0097] Specifically, the material of the source electrode 5 includes titanium nitride, tantalum nitride, titanium, tantalum, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the gate electrode 8 includes titanium nitride, tantalum nitride, titanium, tantalum, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the drain electrode 6 includes titanium nitride, tantalum nitride, titanium, tantalum, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the lead-out electrode 7 includes titanium nitride, tantalum nitride, titanium, tantalum, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.
[0098] It should be noted that when the device in the cell area 11 is a pull-up P-type MOS device in a static random access memory, the drain 6 is connected to the V driving the static random access memory. DD Connect the lead electrode 7 to the V pin that controls the static random access memory to read, write and erase operations. DD connect.
[0099] Specifically, by setting a bias electrode 3 in the device that covers the upper surface of the first gate structure 2 and the upper surface of the buffer zone 13 on the side of the first gate structure 2 away from the cell region 11, the bias electrode 3 is electrically connected to the doped region 17 and the first gate conductive layer. The setting of the bias electrode 3 has no effect on the performance of the device. When the contact region 18 deviates to the buffer zone 13, the bias electrode 3 is electrically connected to the first gate conductive layer, the doped region 17 and the contact region 18 that deviates to the buffer zone 13, so that the potentials of the first gate conductive layer, the well region 10, the contact region 18 that deviates to the buffer zone 13 and the doped region 17 are the same. Then, when the static random access memory is silent, the conductive channel directly below the first gate structure 2 is turned off, thereby avoiding leakage of the device through the contact region 18, the doped region 17 and the well region 10 below the first gate structure 2, reducing the leakage risk of the device and improving the performance of the device.
[0100] Specifically, by disposing the bias electrode 3 , the overlay decoupling margin of the contact region 18 can be improved, while avoiding the problem of increasing the area required for the edge region 12 due to the introduction of an external voltage electrode on the unbiased first gate structure 2 .
[0101] The static random access memory of the present embodiment improves the structure of the device, and sets a bias electrode 3 in the device to cover the upper surface of the first gate structure 2 and the upper surface of the buffer zone 13 on the side of the first gate structure 2 away from the cell region 11. When the contact region 18 deviates to the buffer zone 13, the bias electrode 3 is electrically connected to the first gate conductive layer, the doping region 17 and the contact region 18 deviating to the buffer zone 13, so that the potentials of the first gate conductive layer, the well region 10, the contact region 18 deviating to the buffer zone 13 and the doping region 17 are the same. Then, when the static random access memory is silent, the conductive channel directly below the first gate structure 2 is turned off, thereby avoiding leakage of the device through the contact region 18, the doping region 17 and the well region 10 below the first gate structure 2, reducing the leakage risk of the device, improving the performance of the device, and improving the overlay decoupling margin for forming the contact region 18 without increasing the area of the device.
[0102] Embodiment 2
[0103] This embodiment also provides a method for preparing a static random access memory, such as Figure 4 FIG. 1 is a process flow chart of the method for preparing the static random access memory, comprising the following steps:
[0104] S1: providing a semiconductor structure including an adjacent cell region and an edge region, wherein the edge region includes a buffer region and a lead-out region located on a side of the buffer region away from the cell region, and a first conductive type well region is provided on the upper surface of the cell region and the edge region;
[0105] S2: forming a first gate structure and a second gate structure located on the upper surface of the well region, wherein the first gate structure is located above the buffer region and the area directly below the first gate structure is adjacent to the cell region, and the second gate structure is located above the cell region and spaced apart from the first gate structure;
[0106] S3: forming a second conductive type doped region located on the upper surface of the well region in the buffer region, a second conductive type drain region and a second conductive type source region respectively located on the upper surface of the well region at two opposite sides of the second gate structure, and a first conductive type contact region at least located on the upper surface of the lead-out region, wherein the doped region is located on a side of the first gate structure away from the cell region, and the drain region close to the edge of the cell region is adjacent to the buffer region;
[0107] S4: forming a bias electrode covering the well region on a side of the first gate structure away from the cell region and an upper surface of the first gate structure and electrically connected to the first gate structure and the doped region respectively;
[0108] S5: forming an extraction electrode electrically connected to the contact region on the upper surface of the extraction region, a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, and a gate electrode electrically connected to the second gate structure.
[0109] See also Figures 5 and 6 , performing step S1 and step S2: providing a semiconductor structure 1 including an adjacent cell region 11 and an edge region 12, the edge region 12 including a buffer region 13 and a lead-out region 14 located on a side of the buffer region 13 away from the cell region 11, and a first conductive type well region 10 is provided on the upper surface of the cell region 11 and the edge region 12; forming a first gate structure 2 and a second gate structure 21 located on the upper surface of the well region 10, the first gate structure 2 is located above the buffer region 13 and the area directly below it is adjacent to the cell region 11, and the second gate structure 21 is located above the cell region 11 and is spaced apart from the first gate structure 2.
[0110] It should be noted that the cell region 11 is usually used to form a cell region of a MOS device in a static random access memory, the lead-out region 14 in the edge region 12 is a region for making the lead-out electrode 7 of the well region 10, and the buffer region 13 in the edge region 12 is a region for making a structure for improving process tolerance.
[0111] Specifically, Figure 5 As shown, it is a schematic diagram of the cross-sectional structure of the semiconductor structure 1. The doping concentration of the well region 10 is usually normal doping or light doping. Under the condition of ensuring the device performance, the doping concentration of the well region 10 can be selected according to the actual situation.
[0112] Specifically, an isolation structure 19 is formed between the buffer region 13 and the lead-out region 14 to isolate the buffer region 13 and the lead-out region 14 , which is usually used to reduce device leakage current.
[0113] Specifically, Figure 6 As shown, it is a schematic diagram of the cross-sectional structure after the first gate structure 2 and the second gate structure 21 are formed. The formation of the first gate structure 2 and the second gate structure 21 includes the following steps: forming a dielectric material layer covering the upper surface of the well region 10 and a gate conductive material layer covering the upper surface of the dielectric material layer; forming a patterned first shielding layer on the upper surface of the gate conductive material layer, and etching the gate conductive material layer based on the patterned first shielding layer to obtain a second gate conductive layer located directly above the cell region 11 and a first gate conductive layer located directly above the buffer region 13, wherein the dielectric material layer directly below the first gate conductive layer serves as a first gate dielectric layer, and the dielectric material layer directly below the second gate conductive layer serves as a second gate dielectric layer.
[0114] Specifically, the method of forming the dielectric material layer includes chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods. Preferably, the dielectric material layer is formed by a thermal oxidation process.
[0115] Specifically, the method of forming the gate conductive material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0116] Specifically, the method of etching the gate conductive material layer includes dry etching, wet etching or other suitable methods.
[0117] It should be noted that, usually, the source region 15, the drain region 16 and the doped region 17 of the device are formed after the first gate structure 2 and the second gate structure 21 are formed. The dielectric material layer covering the upper surface of the well region 10 can be used to protect the well region 10. During the ion implantation process, the damage to the ion implantation region in the well region 10 is reduced. Therefore, after etching the gate conductive material layer, there is no need to remove the dielectric material layer in areas other than the areas directly below the first gate conductive layer and the second gate conductive layer.
[0118] See also Figures 7 to 9 , performing steps S3, S4 and S5: forming a second conductive type doped region 17 located on the upper surface of the well region 10 in the buffer region 13, a second conductive type drain region 16 and a second conductive type source region 15 located on the upper surface of the well region 10 on opposite sides of the second gate structure 21, and a first conductive type contact region 18 located at least on the upper surface of the lead-out region 14, the doped region 17 is located on the side of the first gate structure 2 away from the cell region 11, and the drain region 16 close to the edge of the cell region 11 is adjacent to the buffer region 13; forming a bias electrode 3 covering the well region 10 on the side of the first gate structure 2 away from the cell region 11 and the upper surface of the first gate structure 2 and electrically connected to the first gate structure 2 and the doped region 17 respectively; forming an lead-out electrode 7 electrically connected to the contact region 18 on the upper surface of the lead-out region 14, a source electrode 5 electrically connected to the source region 15, a drain electrode 6 electrically connected to the drain region 16, and a gate electrode 8 electrically connected to the second gate structure 21.
[0119] Specifically, Figure 7 , which is a schematic diagram of the cross-sectional structure after forming the source region 15, the drain region 16 and the doping region 17, wherein the method for forming the doping region 17 includes ion implantation or other suitable methods; the method for forming the source region 15 includes ion implantation or other suitable methods; the method for forming the drain region 16 includes ion implantation or other suitable methods. Preferably, the doping region 17, the source region 15 and the drain region 16 are formed simultaneously by an ion implantation process.
[0120] Specifically, Figure 8 As shown, it is a schematic diagram of the cross-sectional structure after the contact area 18 is formed. The formation of the contact area 18 includes the following steps: forming a patterned first shielding layer covering the exposed upper surface of the semiconductor structure 1 and the exposed surfaces of the first gate structure 2 and the second gate structure 21; forming the contact area 18 based on the patterned first shielding layer.
[0121] Specifically, a method for forming the patterned first shielding layer is usually a mask patterning method or a photoresist patterning method commonly used in a photolithography process, which will not be described in detail here.
[0122] Specifically, the method of forming the contact region 18 based on the patterned first shielding layer includes ion implantation or other suitable methods.
[0123] It should be noted that due to the process error in making the patterned first shielding layer, a portion of the formed contact area 18 will deviate to the upper surface of the buffer zone 13, and then a partial contact area 18 adjacent to the doped area 17 will be formed on the upper surface of the buffer zone 13, and the contact area 18 located on the upper surface of the buffer zone 13 is close to the side wall of the isolation structure 19 and adjacent to the isolation structure 19.
[0124] Specifically, after forming the contact area 18 and before forming the bias electrode 3, the step of removing the first shielding layer is also included. Usually, the method for removing the second shielding layer is a commonly used mask layer or photoresist layer removal method, which will not be repeated here.
[0125] Specifically, Fig. 9 As shown, it is a schematic diagram of the cross-sectional structure after the star bias electrode 3 is formed. The formation of the bias electrode 3 includes the following steps: forming a patterned second shielding layer covering the exposed upper surface of the semiconductor structure 1 and the exposed surfaces of the first gate structure 2 and the second gate structure 21; based on the patterned second shielding layer, forming a bias electrode 3 electrically connected to the first gate conductive layer and the contact area 18.
[0126] It should be noted that when the contact area 18 deviates to the buffer area 13 , the bias electrode 3 formed also covers the upper surface of the contact area 18 located on the upper surface layer of the buffer area 13 .
[0127] Specifically, the second shielding layer may be an insulating layer that does not need to be removed later, or may be a photoresist layer used in a photolithography process. Preferably, an insulating layer is used as the second shielding layer.
[0128] Specifically, when the second shielding layer is a photoresist layer, the method for forming the patterned second shielding layer is a commonly used photoresist production and development method, and after forming the bias electrode 3, the second shielding layer is removed by a commonly used photoresist stripping method; when the second shielding layer is an insulating layer that does not need to be removed subsequently, a patterned photoresist layer is usually first formed on the upper surface of the second shielding layer, and then the insulating layer is etched based on the patterned photoresist layer to obtain a patterned second shielding layer. At the same time, after forming the patterned second shielding layer, the photoresist layer on the upper surface of the second shielding layer also needs to be removed.
[0129] Specifically, when the second shielding layer is an insulating layer that does not need to be removed subsequently, the upper surface of the second shielding layer is usually not lower than the upper surfaces of the first gate structure 2 and the second gate structure 21 .
[0130] It should be noted that the second shielding layer is an insulating layer. Usually, a through hole is first formed in the second shielding layer, the bottom surface of which exposes the first gate conductive layer and the doping area 17. When the contact area 18 deviates to the upper surface of the buffer zone 13, the bottom surface of the through hole also exposes the contact area 18 that deviates to the upper surface of the buffer zone 13. Then, an electrode material layer covering the bottom surface of the through hole and the upper surface of the second shielding layer is formed. Finally, the electrode material layer located on the upper surface of the second shielding layer is removed to obtain the bias electrode 3.
[0131] Specifically, the method of forming the electrode material layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.
[0132] Specifically, the method of removing the electrode material layer on the upper surface of the second shielding layer includes chemical mechanical polishing or other suitable methods.
[0133] Specifically, after forming the bias electrode 3 and before forming the extraction electrode 7 , the source electrode 5 and the drain electrode 6 , the step of forming the interlayer dielectric layer 4 is also included.
[0134] Specifically, when the second shielding layer above the semiconductor structure 1 is an insulating layer, the interlayer dielectric layer 4 covers the upper surface of the insulating layer and the exposed surface of the bias electrode 3 .
[0135] Specifically, the method of forming the interlayer dielectric layer 4 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0136] Specifically, after forming the interlayer dielectric layer 4 and before forming the lead-out electrode 7, the source electrode 5 and the drain electrode 6, the steps of forming a first contact hole, a second contact hole, a third contact hole and a fourth contact hole are also included. The first contact hole penetrates the interlayer dielectric layer 4 directly above the source region 15 and the source region 15 is exposed on the bottom surface. The second contact hole penetrates the interlayer dielectric layer 4 directly above the second gate structure 21 and the second gate conductive layer is exposed on the bottom surface. The third contact hole penetrates the interlayer dielectric layer 4 directly above the drain region 16 and the drain region 16 is exposed on the bottom surface. The fourth contact hole penetrates the interlayer dielectric layer 4 directly above the contact region 18 on the upper surface of the lead-out region 14 and the contact region 18 is exposed on the bottom surface.
[0137] Specifically, under the condition of ensuring the performance of the device, the contact holes (the first contact hole, the second contact hole, the third contact hole and the fourth contact hole) can be formed simultaneously or in steps.
[0138] Specifically, the method of forming each contact hole may be dry etching, wet etching, or a combination of dry etching and wet etching.
[0139] Specifically, the source electrode 5 fills the first contact hole, the gate electrode 8 fills the second contact hole, the drain electrode 6 fills the third contact hole, and the lead-out electrode 7 fills the fourth contact hole.
[0140] Specifically, the method of forming each electrode (source 5, gate 8, drain 6 and lead electrode 7) includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.
[0141] Specifically, by improving the manufacturing method of the device, after forming the contact area 18, a bias electrode 3 electrically connected to the first gate conductive layer and the doping area 17 is formed, and when the contact area 18 deviates from the alignment and deviates to the upper surface of the buffer area 13, the bias electrode 3 is also electrically connected to the contact area 18, so that the potential of the well area 10, the contact area 18 deviating to the upper surface of the buffer area 13, the doping area 17 and the first gate conductive layer are equal to the potential of the lead-out electrode 7, and the leakage path directly below the first gate structure 2 is cut off, reducing the potential leakage risk caused by the overlay accuracy of the ion implantation of the doping area 17 and the contact area 18, improving the tolerance of the overlay error of the ion implantation of the doping area 17 and the contact area 18, reducing the process difficulty, and improving the performance of the device.
[0142] Specifically, since the bias electrode 3 only covers the upper surface of the first gate conductive layer and the upper surface of the buffer zone 13 on the side of the first gate structure 2 away from the cell region 11, there is no need to lead out the electrode, the device area is not increased, and the process is simple.
[0143] The preparation method of the static random access memory of the present embodiment improves the manufacturing process of the device. After forming the contact area 18 and the doping area 17, a bias electrode 3 is formed to cover the upper surface of the first gate conductive layer and the upper surface of the buffer area 13 on the side of the buffer area 13 away from the cell area 11, thereby avoiding the problem of device leakage caused by the offset of the contact area 18 and the doping area 17, improving the performance of the device, and simplifying the process.
[0144] In summary, the static random access memory and the preparation method thereof of the present invention are provided with a bias electrode covering the upper surface of the first gate structure and the upper surface of the buffer zone on the side of the first gate structure away from the cell region in the device through the structure of the device, and then when the contact area deviates to the buffer zone, the potential of the first gate conductive layer, the well area, the contact area deviated to the buffer zone and the doping area are kept flat, so that when the static random access memory is silent, the conductive channel directly below the first gate structure is turned off, and leakage of the device through the contact area, the doping area and the well area below the first gate structure is avoided, the leakage risk of the device is reduced, the performance of the device is improved, and the overlay decoupling margin of the contact area is improved. In addition, since there is no need to lead out the bias electrode, the setting of the bias electrode will not increase the area of the device, and the process is simple. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0145] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A static random access memory, characterized in that: include: A semiconductor structure, comprising an adjacent cell region and an edge region, wherein the edge region comprises a buffer region and a lead-out region located on a side of the buffer region away from the cell region, and a first conductive type well region is provided on the upper surface of the cell region and the edge region; A first gate structure is located on the upper surface of the well region in the buffer region and the area directly below the first gate structure is adjacent to the cell region; A second gate structure, located on an upper surface of the well region in the cell region and spaced apart from the first gate structure by a preset distance; A second conductive type doped region is located on an upper surface layer of the well region on a side of the first gate structure away from the cell region; A second conductive type source region and a second conductive type drain region are respectively located on the upper surface layer of the well region at two opposite sides of the second gate structure, and the drain region near the edge of the cell region is adjacent to the buffer region; A first conductive type contact region, at least located on the upper surface layer of the lead-out region; a bias electrode, covering the well region on a side of the first gate structure away from the cell region and an upper surface of the first gate structure and being electrically connected to the first gate structure and the doped region respectively; A lead-out electrode electrically connected to the contact area on the upper surface of the lead-out area; The source electrode, the drain electrode and the gate electrode are electrically connected to the source region, the drain region and the second gate structure respectively.
2. The static random access memory according to claim 1, wherein: The semiconductor structure further includes an isolation structure embedded in the well region between the buffer region and the lead-out region.
3. The static random access memory according to claim 2, wherein: The isolation structure includes an isolation trench and an isolation filling layer.
4. The static random access memory according to claim 1, wherein: The first gate structure includes a first gate dielectric layer and a first gate conductive layer stacked in sequence, the second gate structure includes a second gate dielectric layer and a second gate conductive layer stacked in sequence, the gate is electrically connected to the second gate conductive layer, and the bias electrode is electrically connected to the first gate conductive layer.
5. The static random access memory according to claim 1, wherein: The doping concentration of the doping region is the same as that of the source region and the drain region.
6. The static random access memory according to claim 1, wherein: The contact region extends to the buffer region close to the sidewall of the cell region.
7. The static random access memory according to claim 6, wherein: The edge of the bias electrode also extends to the upper surface of the contact area on the upper surface layer of the buffer zone and is electrically connected to the portion of the contact area.
8. The static random access memory according to claim 1, wherein: The bias electrode further covers a sidewall of the first gate structure away from the cell region.
9. The static random access memory according to claim 1, wherein: An interlayer dielectric layer is also provided in the static random access memory. The interlayer dielectric layer is located directly above the semiconductor structure and covers the exposed surface of the bias electrode. The source electrode penetrates the interlayer dielectric layer and is electrically connected to the source region. The drain electrode penetrates the interlayer dielectric layer and is electrically connected to the drain region. The gate electrode penetrates the interlayer dielectric layer and is electrically connected to the second gate structure. The lead-out electrode penetrates the interlayer dielectric layer and is electrically connected to the contact region.
10. A method for preparing a static random access memory, characterized in that: The following steps are involved: A semiconductor structure is provided, comprising an adjacent cell region and an edge region, wherein the edge region comprises a buffer region and a lead-out region located on a side of the buffer region away from the cell region, and a first conductive type well region is provided on the upper surface of the cell region and the edge region; Forming a first gate structure and a second gate structure located on the upper surface of the well region, wherein the first gate structure is located above the buffer region and the area directly below the first gate structure is adjacent to the cell region, and the second gate structure is located above the cell region and spaced apart from the first gate structure; forming a second conductive type doped region located on the upper surface of the well region in the buffer region, a second conductive type drain region and a second conductive type source region located on the upper surface of the well region at two opposite sides of the second gate structure, and at least a first conductive type contact region located on the upper surface of the lead-out region, wherein the doped region is located on a side of the first gate structure away from the cell region, and the drain region close to the edge of the cell region is adjacent to the buffer region; forming a bias electrode covering the well region on a side of the first gate structure away from the cell region and an upper surface of the first gate structure and electrically connected to the first gate structure and the doped region respectively; An extraction electrode electrically connected to the contact area on the upper surface of the extraction area, a source electrode electrically connected to the source area, a drain electrode electrically connected to the drain area, and a gate electrode electrically connected to the second gate structure are formed.