Manufacturing method of groove type semiconductor structure

Abstract

The invention provides a manufacturing method of a groove type semiconductor structure, which comprises the following steps: after forming a groove, growing a thermal oxide layer, depositing an oxide layer on the surface of the thermal oxide layer through chemical vapor deposition, the thickness of the thermal oxide layer is A, the total thickness of the thermal oxide layer and the chemical vapor deposition oxide layer is B, and the range of A / B is 38%-46%. According to the invention, the trench side wall oxide layer is manufactured by several times and by adopting different methods, the stacked trench side wall oxide layer is obtained, the film layer stress is reduced by adjusting the film layer thickness ratio of the thermal oxide layer to the chemical vapor deposition oxide layer, the wafer warping degree is weakened, and the process is optimized on the basis of not influencing the electrical property. In the optional scheme of the invention, the stress of the front surface film layer can be balanced by forming the back surface deposition layer on the back surface of the wafer, the warping degree is further reduced, the method is simple and convenient, the operability is high, and the front surface structure is not influenced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a method for manufacturing a trench-type semiconductor structure. Background Art

[0002] When an object is deformed due to external factors (force, humidity, temperature field changes, etc.), internal forces that interact with each other will be generated between the various parts of the object to resist the effects of such external factors and try to restore the object from its position after deformation to its position before deformation. This internal force is the membrane stress.

[0003] like Figure 1 As shown, a layer structure includes a substrate 101 and a thin film 102 deposited on the substrate 101. In the original state, the layer structure is in a flat state. Figure 2 As shown in FIG. 1 , it is a schematic diagram showing that the substrate 101 is warped downward due to the compressive stress of the film 102. Figure 3 As shown, it is a schematic diagram that the film 102 causes the substrate 101 to warp upward due to the tensile stress.

[0004] Shielded Gate Trench (SGT) is a new type of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) technology. It has a deeper trench depth in structure and can use the epitaxial (EPI) thickness to withstand higher voltages. In terms of performance, it can reduce parasitic capacitance and on-resistance, and has lower switching losses. Other types of trench semiconductor devices, such as Insulated Gate Bipolar Transistor (IGBT), also usually use trench gate structures to improve voltage resistance.

[0005] Because the grooves, especially deep grooves, increase the silicon surface area, in some cases it can cause the wafer bow value to be too large, resulting in the machine displaying a vacuum error (Vacuum error) and being unable to continue operations in subsequent processes, such as during gate polysilicon lithography.

[0006] Therefore, how to improve the manufacturing method of the trench-type semiconductor structure to reduce the wafer warpage and improve the yield has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing a trench-type semiconductor structure, so as to solve the problem that the wafer warpage is too large due to film layer stress during the manufacturing process of the conventional trench-type semiconductor structure.

[0009] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing a trench-type semiconductor structure, comprising the following steps:

[0010] Providing a wafer, the wafer comprising a front side and a back side arranged opposite to each other;

[0011] Forming a groove in the wafer, wherein the groove opens from the front side of the wafer and extends toward the back side of the wafer;

[0012] Growing a thermal oxide layer on the inner wall of the groove, and forming a chemical vapor deposition oxide layer on the surface of the thermal oxide layer by chemical vapor deposition, wherein the thickness of the thermal oxide layer is A, the total thickness of the thermal oxide layer and the chemical vapor deposition oxide layer is B, and the range of A / B is 38% to 46%;

[0013] A gate polysilicon layer is formed, wherein the gate polysilicon layer covers the front side of the wafer and fills the trench.

[0014] Optionally, a thickness A of the thermal oxide layer is in a range of 3700 angstroms to 4500 angstroms.

[0015] Optionally, the chemical vapor deposition oxide layer includes a sub-atmospheric pressure chemical vapor deposition oxide layer or a high-density plasma chemical vapor deposition oxide layer.

[0016] Optionally, after forming the chemical vapor deposition oxide layer, an annealing step is further included, and the annealing is thermal annealing or rapid annealing, and the annealing temperature is lower than 1100°C.

[0017] Optionally, after forming the gate polysilicon layer, the following steps are further included:

[0018] Turning the wafer over so that the back side of the wafer faces upward;

[0019] Using high-density plasma chemical vapor deposition to form a back deposition layer on the back of the wafer to reduce the warpage of the wafer;

[0020] Turning the wafer over so that the front side of the wafer faces upward;

[0021] Perform wafer front side processing.

[0022] Optionally, the backside deposition layer includes a silicon oxide layer or a silicon nitride layer.

[0023] Optionally, forming a back deposition layer on the back side of the wafer by high density plasma chemical vapor deposition includes one or more deposition steps, and when forming the back deposition layer, a single deposition thickness ranges from 5.8 kiloangstroms to 9 kiloangstroms.

[0024] Optionally, the trench semiconductor structure includes a metal-oxide semiconductor field effect transistor, a shielded gate trench field effect transistor or an insulated gate bipolar transistor.

[0025] Optionally, the trench-type semiconductor structure comprises a shielded gate trench field effect transistor, and after forming the chemical vapor deposition oxide layer in the trench, the following steps are included:

[0026] forming a source polysilicon layer, wherein the source polysilicon layer covers the front surface of the wafer and fills the trench;

[0027] Removing the portion of the source polysilicon layer located above the front side of the wafer, and retaining the portion filling the groove;

[0028] Etching back the thermal oxide layer and the chemical vapor deposition oxide layer to make them lower than the front surface of the wafer and the top surface of the source polysilicon layer to form a double gate trench;

[0029] A gate oxide dielectric layer and the gate polysilicon layer are formed, wherein the gate oxide dielectric layer is located on the inner wall of the double gate trench and the surface of the source polysilicon layer after back etching, and the gate polysilicon layer covers the upper side of the wafer front side and fills the double gate trench.

[0030] Optionally, after forming the source polysilicon layer, the method further includes taking the wafer boat loaded with the wafer out of the furnace tube, and the boat outflow rate ranges from 50 mm / min to 100 mm / min.

[0031] As described above, the method for making a trench-type semiconductor structure of the present invention grows a thermal oxide layer after forming a groove, and deposits an oxide layer on the surface of the thermal oxide layer by chemical vapor deposition. The thickness of the thermal oxide layer is A, and the total thickness of the thermal oxide layer and the chemical vapor deposition oxide layer is B, and the range of A / B is 38% to 46%. The present invention makes the trench sidewall oxide layer in batches and by different methods to obtain a superimposed trench sidewall oxide layer, and reduces the film stress by adjusting the film thickness ratio of the thermal oxide layer and the chemical vapor deposition oxide layer, reduces the degree of wafer warpage, and optimizes the process without affecting the electrical properties. In an optional scheme of the invention, the front film stress can be balanced by forming a back deposition layer on the back of the wafer, and the wafer warpage is further reduced. It is simple and convenient, has strong operability, does not affect the front structure, and helps to quickly solve the problem of overstocking of high-warpage products and improve the iteration speed. In another optional method of the present invention, an annealing step is also included after the chemical vapor deposition oxide layer is formed, and the annealing temperature is lower than 1100°C, which is conducive to reducing the film stress and preventing the wafer from being too warped. In the case where the trench semiconductor structure is a shielded gate trench field effect transistor, the boat exit rate can be controlled at 50 mm / min-100 mm / min during the boat exit process after the source polysilicon layer is formed, so as to avoid the increase of film layer stress and additional wafer warping due to the accelerated wafer cooling rate caused by the excessively fast boat exit rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Shown is a schematic diagram of a layer structure.

[0033] Figure 2 Schematic diagram showing the film warping downward due to compressive stress on the substrate.

[0034] Figure 3 Schematic diagram showing that the film warps the substrate upward due to tensile stress.

[0035] Figure 4 Shown is a flow chart of a method for manufacturing a trench semiconductor structure of the present invention.

[0036] Figure 5 A schematic diagram showing the film layer structure of a wafer provided by the method for manufacturing a trench-type semiconductor structure of the present invention is shown.

[0037] Figure 6 It is a schematic diagram showing the structure obtained after forming trenches in a wafer according to the method for manufacturing a trench-type semiconductor structure of the present invention.

[0038] Figure 7 It is a schematic diagram showing the structure obtained after the method for manufacturing the trench-type semiconductor structure of the present invention sequentially forms a thermal oxide layer and a chemical vapor deposition oxide layer in the trench.

[0039] Figure 8It is a schematic diagram showing the structure obtained after forming a source polysilicon layer according to the method for manufacturing a trench semiconductor structure of the present invention.

[0040] Fig. 9 It is a schematic diagram showing the structure obtained after forming a gate polysilicon layer according to the method for manufacturing a trench semiconductor structure of the present invention.

[0041] Fig.10 The graph shows the wafer warpage results for experiments in groups A to F in Table 1.

[0042] Fig.11 It is a schematic diagram showing the method for manufacturing the trench semiconductor structure of the present invention, in which a wafer is flipped so that the back side of the wafer faces upward.

[0043] Fig.12 It is a schematic diagram showing the structure obtained after forming a backside deposition layer on the backside of a wafer according to the method for manufacturing a trench-type semiconductor structure of the present invention.

[0044] Fig.13 It is a schematic diagram showing the method for manufacturing the trench semiconductor structure of the present invention, in which a wafer is flipped so that the front side of the wafer faces upward.

[0045] Fig.14 A schematic diagram showing that the stresses in the back film layer and the front film layer are opposite.

[0046] Fig.15 The schematic diagram shows that the stress of the back film layer and the front film layer offset each other so that the wafer warpage is reduced.

[0047] Description of Reference Numerals

[0048] 101 Substrate

[0049] 102 film

[0050] Steps S1 to S4

[0051] 201 substrate layer

[0052] 202 First epitaxial layer

[0053] 203 Second epitaxial layer

[0054] 204 Groove

[0055] 205 Thermal Oxide Layer

[0056] 206 Chemical Vapor Deposition Oxide Layer

[0057] 207 Source polysilicon layer

[0058] 208 gate oxide dielectric layer located on the inner wall of the double gate trench

[0059] 209 Gate oxide dielectric layer located on the surface of the source polysilicon layer

[0060] 210 Gate polysilicon layer

[0061] 211 Backside deposition layer

[0062] 301 back film layer

[0063] 302 front film layer DETAILED DESCRIPTION

[0064] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] See also Figures 4 to 15 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0066] The present invention provides a method for manufacturing a trench-type semiconductor structure. Figure 4 , shown as a flow chart of the method, comprising the following steps:

[0067] S1: providing a wafer, wherein the wafer comprises a front side and a back side which are arranged opposite to each other;

[0068] S2: forming a groove in the wafer, wherein the groove opens from the front side of the wafer and extends toward the back side of the wafer;

[0069] S3: growing a thermal oxide layer on the inner wall of the groove, and forming a chemical vapor deposition oxide layer on the surface of the thermal oxide layer by chemical vapor deposition, wherein the thickness of the thermal oxide layer is A, the total thickness of the thermal oxide layer and the chemical vapor deposition oxide layer is B, and the range of A / B is 38% to 46%;

[0070] S4: forming a gate polysilicon layer, wherein the gate polysilicon layer covers the front side of the wafer and fills the trench.

[0071] Specifically, the method for manufacturing a trench-type semiconductor structure of the present invention is applicable to a metal-oxide semiconductor field effect transistor (MOSFET) with a trench gate, a shielded gate trench field effect transistor (SGT), an insulated gate bipolar transistor (IGBT) or other deep trench semiconductor power devices. For SGT, before forming the gate polysilicon layer in step S4, a step of forming a source polysilicon layer (or shielded gate polysilicon layer) and other related layers is also included.

[0072] The following will take SGT as an example and combine Figures 5 to 13 Each step of the method for manufacturing the trench semiconductor structure of the present invention is described in detail.

[0073] First see Figure 5 , perform the step S1: provide a wafer, the wafer comprising a front side and a back side arranged opposite to each other.

[0074] As an example, the wafer includes a substrate layer 201 and a first epitaxial layer 202 and a second epitaxial layer 203 located on the substrate layer 201. The substrate layer 201 can be made of silicon, silicon carbide or other suitable semiconductor materials. In other embodiments, according to the actual semiconductor structure, the film layer composition of the wafer can also be changed. For example, the substrate layer 201 has three epitaxial layers, which is not excessively limited here.

[0075] Please see again Figure 6 , executing the step S2: forming a groove 204 in the wafer, wherein the groove 204 opens from the front side of the wafer and extends toward the back side of the wafer.

[0076] As an example, the bottom of the trench 204 stays in the first epitaxial layer 202 .

[0077] It should be noted that the specific depth, width and density of the grooves 204 can be set according to the actual requirements of the semiconductor device to be manufactured, and no excessive restrictions are imposed here.

[0078] Please see again Figure 7 , perform step S3: grow a thermal oxide layer 205 on the inner wall of the groove 204, and form a chemical vapor deposition oxide layer 206 on the surface of the thermal oxide layer 205 by chemical vapor deposition, the thickness of the thermal oxide layer 205 is A, the total thickness of the thermal oxide layer 205 and the chemical vapor deposition oxide layer 206 is B, and the range of A / B is 38% to 46%.

[0079] Specifically, in this step, the trench sidewall oxide layer is deposited in batches and by different methods to obtain a trench sidewall oxide layer formed by the superposition of the thermal oxide layer 205 and the chemical vapor deposition oxide layer 206, and by adjusting the film thickness ratio of the thermal oxide layer 205 and the chemical vapor deposition oxide layer 206, that is, the thickness ratio of the thermal oxide layer 205 is controlled to be 38% to 46%, in order to reduce the film stress, reduce the degree of wafer warping, optimize the process without affecting the electrical properties, and ensure the smooth progress of subsequent processes.

[0080] Specifically, for SGT, the trench sidewall oxide layer is used as a field oxide layer, and its total thickness can be adjusted according to the different breakdown voltage (BV) requirements of the project, as long as the thermal oxide layer thickness accounts for 38%-46%. In one embodiment, the thickness A of the thermal oxide layer 205 ranges from 3700 angstroms to 4500 angstroms. For IGBT or other deep trench semiconductor power devices, the trench sidewall oxide layer can be used as a gate oxide layer, and its total thickness can also be adjusted according to actual needs, as long as the thermal oxide layer thickness accounts for 38%-46%.

[0081] As an example, the chemical vapor deposition oxide layer 206 may be a sub-atmospheric pressure chemical vapor deposition (SACVD) oxide layer or a high-density plasma (High-Definition Plasma, HDP) chemical vapor deposition oxide layer.

[0082] As an example, after forming the chemical vapor deposition oxide layer 206, an annealing step is also included. The annealing temperature is lower than 1100°C. For example, in one embodiment, the annealing temperature is selected to be 950°C. The appropriate temperature is also conducive to reducing film layer stress and preventing excessive wafer warping.

[0083] Please see again Figure 8 and Fig. 9 , executing the step S4: forming a gate polysilicon layer 210 , wherein the gate polysilicon layer 210 covers the front side of the wafer and fills the trench 204 .

[0084] Specifically, Figure 8 As shown, a source polysilicon layer 207 is first formed, and the source polysilicon layer 207 covers the front side of the wafer and fills the trench.

[0085] Then, the portion of the source polysilicon layer 207 located above the front surface of the wafer is removed, and the portion for filling the groove is retained. Then, the thermal oxide layer 205 and the chemical vapor deposition oxide layer 206 are etched back to be lower than the front surface of the wafer and the top surface of the source polysilicon layer 207 to form a double gate groove, and then a gate oxide dielectric layer and the gate polysilicon layer 210 are formed to obtain the following: Fig. 9 The structure shown.

[0086] Specifically, the gate oxide dielectric layer is located on the inner wall of the double gate trench and the surface of the source polysilicon layer 207 after back etching, and the gate polysilicon layer 210 covers the upper surface of the wafer and fills the double gate trench, wherein: Fig. 9 The figure shows a gate oxide dielectric layer 208 located on the inner wall of the double-gate trench and a gate oxide dielectric layer 209 located on the surface of the source polysilicon layer, wherein the gate oxide dielectric layer 209 located on the surface of the source polysilicon layer serves as an isolation layer between the source polysilicon layer 207 and the gate polysilicon layer 210.

[0087] As an example, after forming the source polysilicon layer 207, the process further includes the step of unloading the wafer boat loaded with the wafer from the furnace tube, and the boat unloading rate ranges from 50 mm / min to 100 mm / min. Because a too fast boat unloading rate will accelerate the wafer cooling rate, and different film layers have different thermal expansion coefficients, stress will change and cause wafer warpage. The present invention can avoid causing additional wafer warpage by controlling the boat unloading rate to 50 mm / min to 100 mm / min during the boat unloading process after forming the source polysilicon layer.

[0088] As an example, see Table 1 and Fig.10 Table 1 shows some experimental data of the present invention for reducing film stress and weakening the degree of wafer warpage by adjusting the film thickness ratio of the thermal oxide layer 205 and the chemical vapor deposition oxide layer 206. Fig.10 The graph shows the wafer warpage results for experiments in groups A to F in Table 1 above.

[0089] Table 1 Experimental data

[0090]

[0091] Among them, the test results of the experiments of Group A, Group B, Group C, Group E and Group F all showed that the wafer warpage was too high and the results were not passed. In the experiment of Group D, the thickness of the thermal oxide layer was 4000 angstroms, which was within the range of 38% to 46% of the total thickness of the oxide layer on the sidewall of the groove, and the annealing temperature after the chemical vapor deposition oxide layer was 950°C, which was lower than 1100°C. The test results showed that the wafer warpage was qualified. In other words, by reasonably matching the film thickness ratio of the thermal oxide layer 205 and the chemical vapor deposition oxide layer 206, the film stress can be reduced and the degree of wafer warpage can be weakened. At the same time, controlling the annealing temperature after the formation of the chemical vapor deposition oxide layer to be lower than 1100°C is conducive to reducing the film stress and preventing the wafer from being too warped. Controlling the boat exit rate after the formation of the source polysilicon layer to be between 50 mm / min and 100 mm / min can avoid additional wafer warpage caused by excessive boat exit rate.

[0092] It should be pointed out that for some devices, when the film ratio and temperature cannot be adjusted due to electrical considerations, or even if the film ratio and temperature are adjusted to a certain extent, the ideal wafer warpage cannot be achieved, the back deposition layer can be formed on the back of the wafer to balance or offset the front film stress, thereby further reducing the wafer warpage. This is simple and convenient, has strong operability, does not affect the front structure, and helps to quickly solve the problem of overstocking of high warpage products and increase the iteration speed.

[0093] Specifically, in one embodiment, after forming the gate polysilicon layer 210, the following steps are further included:

[0094] (1) Please refer to Fig.11 , flipping the wafer so that the back side of the wafer faces upward.

[0095] As an example, a wafer flipping device of a scrubber machine is used to flip the wafer so that the back side of the wafer faces upward.

[0096] (2) Please refer to Fig.12 A high density plasma chemical vapor deposition method is used to form a back deposition layer 211 on the back side of the wafer to reduce the warpage of the wafer.

[0097] As an example, the backside deposition layer 211 may include a silicon oxide layer or a silicon nitride layer.

[0098] As an example, forming a backside deposition layer on the backside of the wafer by high density plasma chemical vapor deposition includes one or more deposition steps. When forming the backside deposition layer, the thickness range of a single deposition is 5.8 kiloangstroms to 9 kiloangstroms.

[0099] Specifically, the number of deposition times can be set according to the wafer warpage, for example, 1-4 times.

[0100] As an example, Table 2 shows data on the change in wafer warpage before and after backside deposition in one embodiment, wherein the backside deposition layer is formed by four depositions.

[0101] Table 2 Changes in wafer warpage before and after backside deposition

[0102] Technology Warpage (micrometer) After gate polysilicon deposition -208.49 Backside HDP deposition 4*5.8K After backside HDP deposition -69.91 Δ 138.58

[0103] It can be seen that after four depositions of a single back deposition layer with a thickness of 5.8 kiloangstroms, the wafer warpage was reduced by 138.58 microns, which is a significant improvement.

[0104] (3) Please refer to Fig.13 , flipping the wafer so that the front side of the wafer faces upward.

[0105] As an example, a wafer flipping device of a scrubber machine is also used to flip the wafer so that the front side of the wafer faces upward.

[0106] (4) Perform wafer front side processing, such as gate polysilicon layer photolithography.

[0107] As an example, the portion of the gate polysilicon layer 210 outside the trench 204 is removed, and then a dielectric layer is deposited, a contact hole is made, and a metal layer is deposited to make a metal interconnection layer (not shown).

[0108] As an example, it also includes back side thinning and back side metal process (Back Grind Back Metal, BGBM). Since the wafer warpage is small, the subsequent processes can be carried out smoothly and the wafer testing (Chip Probing, referred to as CP) yield is improved.

[0109] As an example, see Fig.14 and Fig.15 ,in, Fig.14 It is a schematic diagram showing that the stress of the back film layer 301 and the front film layer 302 are opposite. Fig.15 It is a schematic diagram showing that the stress of the back film layer 301 and the front film layer 302 offset each other so that the warpage of the wafer is reduced.

[0110] In summary, the method for making a trench-type semiconductor structure of the present invention grows a thermal oxide layer after forming a groove, and deposits an oxide layer on the surface of the thermal oxide layer by chemical vapor deposition. The thickness of the thermal oxide layer is A, and the total thickness of the thermal oxide layer and the chemical vapor deposition oxide layer is B, and the range of A / B is 38% to 46%. The present invention makes the trench sidewall oxide layer in batches and by different methods to obtain a superimposed trench sidewall oxide layer, and reduces the film stress by adjusting the film thickness ratio of the thermal oxide layer and the chemical vapor deposition oxide layer, reduces the degree of wafer warpage, and optimizes the process without affecting the electrical properties. In an optional scheme of the invention, the front film stress can be balanced by forming a back deposition layer on the back of the wafer, and the wafer warpage is further reduced. It is simple and convenient, has strong operability, does not affect the front structure, and helps to quickly solve the problem of overstocking of high-warpage products and improve the iteration speed. In another optional method of the present invention, an annealing step is also included after the chemical vapor deposition oxide layer is formed, and the annealing temperature is lower than 1100°C, which is conducive to reducing the film stress and preventing the wafer from being too warped. In the case where the trench semiconductor structure is a shielded gate trench field effect transistor, the boat exit rate can be controlled at 50 mm / min-100 mm / min during the boat exit process after the source polysilicon layer is formed, so as to avoid the wafer temperature reduction rate being accelerated due to the excessively fast boat exit rate, resulting in increased film stress and additional wafer warping. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a trench-type semiconductor structure, characterized in that it comprises the following steps: Providing a wafer, the wafer comprising a front side and a back side arranged opposite to each other; Forming a groove in the wafer, wherein the groove opens from the front side of the wafer and extends toward the back side of the wafer; Growing a thermal oxide layer on the inner wall of the groove, and forming a chemical vapor deposition oxide layer on the surface of the thermal oxide layer by chemical vapor deposition, wherein the thickness of the thermal oxide layer is A, the total thickness of the thermal oxide layer and the chemical vapor deposition oxide layer is B, and the range of A / B is 38% to 46%; A gate polysilicon layer is formed, wherein the gate polysilicon layer covers the front side of the wafer and fills the trench.

2. The method for manufacturing a trench semiconductor structure according to claim 1, wherein: The thickness A of the thermal oxide layer ranges from 3700 angstroms to 4500 angstroms.

3. The method for manufacturing a trench semiconductor structure according to claim 1, wherein: The chemical vapor deposition oxide layer includes a sub-atmospheric pressure chemical vapor deposition oxide layer or a high-density plasma chemical vapor deposition oxide layer.

4. The method for manufacturing a trench semiconductor structure according to claim 1, wherein: After forming the chemical vapor deposition oxide layer, an annealing step is also included. The annealing is thermal annealing or rapid annealing. The annealing temperature is lower than 1100°C.

5. The method for manufacturing a trench semiconductor structure according to claim 1, wherein: After forming the gate polysilicon layer, the method further comprises the following steps: Turning the wafer over so that the back side of the wafer faces upward; Using high-density plasma chemical vapor deposition to form a back deposition layer on the back of the wafer to reduce the warpage of the wafer; Turning the wafer over so that the front side of the wafer faces upward; Perform wafer front side processing.

6. The method for manufacturing a trench semiconductor structure according to claim 5, characterized in that: The backside deposition layer includes a silicon oxide layer or a silicon nitride layer.

7. The method for manufacturing a trench semiconductor structure according to claim 5, characterized in that: The back side deposition layer is formed on the back side of the wafer by high density plasma chemical vapor deposition method, which includes one or more deposition steps. When forming the back side deposition layer, the single deposition thickness ranges from 5.8 kiloangstroms to 9 kiloangstroms.

8. The method for manufacturing a trench semiconductor structure according to claim 1, wherein: The trench-type semiconductor structure includes a metal-oxide semiconductor field effect transistor, a shielded gate trench field effect transistor or an insulated gate bipolar transistor.

9. The method for manufacturing a trench semiconductor structure according to claim 1, characterized in that: The trench-type semiconductor structure includes a shielded gate trench field effect transistor, and after forming the chemical vapor deposition oxide layer in the trench, the method includes the following steps: forming a source polysilicon layer, wherein the source polysilicon layer covers the front surface of the wafer and fills the trench; Removing the portion of the source polysilicon layer located above the front side of the wafer, and retaining the portion filling the groove; Etching back the thermal oxide layer and the chemical vapor deposition oxide layer to make them lower than the front surface of the wafer and the top surface of the source polysilicon layer to form a double gate trench; A gate oxide dielectric layer and the gate polysilicon layer are formed, wherein the gate oxide dielectric layer is located on the inner wall of the double gate trench and the surface of the source polysilicon layer after back etching, and the gate polysilicon layer covers the front side of the wafer and fills the double gate trench.

10. The method for manufacturing a trench semiconductor structure according to claim 9, characterized in that: After forming the source polysilicon layer, the method further includes taking the wafer boat loaded with the wafer out of the furnace tube, with the boat taking-out rate ranging from 50 mm / min to 100 mm / min.

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