Manufacturing method of groove type semiconductor power device
By changing the wafer back sealing sequence and optimizing the annealing treatment, the problem of yield reduction in trench semiconductor power devices due to excessive wafer warping is solved, and lower warping and higher yield are achieved.
Patent Information
- Application Number
- CN202311482844.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-08
- Publication Date
- 2025-05-13
AI Technical Summary
During the production process, existing trench semiconductor power devices are prone to the problem of reducing yield due to excessive wafer warping.
By changing the wafer back sealing order, the wafer itself is optimized, the silicon oxide back sealing layer and the polysilicon back sealing layer are formed in sequence on the back of the wafer, and a silicon oxide layer and a polysilicon layer are formed in the trench, and annealing is performed to reduce thermal stress.
It effectively reduces the wafer warpage after the thermal process, improves the product yield, reduces the wafer warpage at special processes, increases the chip efficiency and success rate, reduces the cost and improves competitiveness.
Smart Images
Figure CN119997535A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to a method for manufacturing a trench-type semiconductor power device. Background Art
[0002] Deep trenches and high-density trenches are very prominent features of shield gate trench (SGT) metal-oxide-semiconductor (MOS). Deep trenches and high-density trenches can utilize more epitaxial layers and increase the breakdown voltage (BV).
[0003] Different film layers and silicon (Si) have different thermal expansion coefficients. After experiencing the hot and cold process, stress is introduced between different film layers, causing the wafer to warp. In the actual R&D process, the field oxide layer and polysilicon of SGT are filled in deeper trenches. The thermal process causes a surge in wafer warpage, resulting in machine alarms and fragmentation problems in processes such as lithography, backside thinning and backside metal (Back Grind Back Metal, BGBM).
[0004] Similar problems also exist in other semiconductor power devices that use trench technology, such as trench MOS, insulated gate bipolar transistor (IGBT), etc.
[0005] The existing solutions are usually as follows:
[0006] (1) Introducing film layers and grooves on the back of the wafer to offset the stress on the front side;
[0007] (2) Cyclic deposition of doped polysilicon (Dpoly) and undoped polysilicon (Upoly)
[0008] (3) Introducing a size-controllable polysilicon hollow closed cavity to buffer stress;
[0009] (4) Optimize the photolithography layout and make the groove distribution as crisscross as possible.
[0010] Therefore, how to improve the manufacturing method of trench-type semiconductor power devices to reduce wafer warpage and improve yield has become an important technical problem that needs to be solved urgently by those skilled in the art.
[0011] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0012] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing a trench-type semiconductor power device, so as to solve the problem that the yield of the conventional trench-type semiconductor power device is easily reduced due to excessive wafer warpage during the manufacturing process.
[0013] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a trench-type semiconductor power device, comprising the following steps:
[0014] Providing a wafer, wherein the wafer comprises a front side and a back side that are arranged opposite to each other;
[0015] Sequentially forming a silicon oxide back-sealing layer and a polysilicon back-sealing layer on the back side of the wafer;
[0016] forming a groove on the front side of the wafer;
[0017] forming a silicon oxide layer on the inner wall of the trench;
[0018] performing a first annealing process;
[0019] A polysilicon layer is formed in the trench.
[0020] Optionally, the thickness of the silicon oxide backing layer is in the range of 5 kiloangstroms to 7 kiloangstroms, and the thickness of the polysilicon backing layer is in the range of 7 kiloangstroms to 9 kiloangstroms.
[0021] Optionally, the silicon oxide backing layer includes a low temperature oxide layer, and a method for forming the low temperature oxide layer includes a plasma enhanced chemical vapor deposition method, and a deposition temperature is not higher than 200°C.
[0022] Optionally, in the step of forming a polysilicon layer in the groove, the polysilicon layer also covers the front surface of the wafer, and the manufacturing method further includes the step of chemically mechanically polishing the polysilicon layer.
[0023] Optionally, the trench-type semiconductor power device includes a metal-oxide semiconductor field effect transistor, a shielded gate trench field effect transistor or an insulated gate bipolar transistor.
[0024] Optionally, the trench-type semiconductor power device includes a shielded gate trench field effect transistor, the silicon oxide layer includes a field oxide layer, the polysilicon layer includes source polysilicon, and after forming the source polysilicon in the trench, the following steps are further included:
[0025] etching back the field oxide layer;
[0026] An isolation layer, a gate dielectric layer and gate polysilicon are formed in the trench, wherein the isolation layer is located between the source polysilicon and the gate polysilicon, and the gate dielectric layer is located between the sidewall of the trench and the gate polysilicon.
[0027] Optionally, the silicon oxide layer includes a gate oxide layer, and the polysilicon layer includes gate polysilicon.
[0028] Optionally, the annealing temperature used in the first annealing process is 950° C., and the deposition temperature used when forming the polysilicon layer in the trench is 550° C.
[0029] Optionally, after the step of forming a polysilicon layer in the trench, a second annealing process is further included to cause the polysilicon layer to undergo a crystal transformation.
[0030] Optionally, the annealing temperature range of the second annealing process is 850° C.-950° C., and the annealing time is 10 minutes-30 minutes.
[0031] As described above, the manufacturing method of the trench-type semiconductor power device of the present invention includes the following steps: providing a wafer, the wafer including a front side and a back side that are relatively arranged; sequentially forming a silicon oxide backing layer and a polysilicon backing layer on the back side of the wafer; forming a groove on the front side of the wafer; forming a silicon oxide layer on the inner wall of the groove; performing a first annealing process; forming a polysilicon layer in the groove. The present invention can optimize the stress release of the wafer itself by changing the wafer backing sequence, so that the wafer stress buffering is better and the wafer warpage after the thermal process is reduced. In addition, in the optional scheme of the present invention, the warpage caused by the thermal process can be further reduced by optimizing the silicon oxide annealing temperature and the polysilicon layer deposition temperature, and increasing the source polysilicon annealing step, which helps to improve the wafer warpage, reduce the product fragmentation rate, and reduce the wafer warpage at special processes, thereby increasing the tape-out efficiency and success rate, reducing costs, and improving competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 Shown is a process flow chart of a method for manufacturing a trench-type semiconductor power device of the present invention.
[0033] Figure 2 Shown is a schematic structural diagram of a wafer provided for the method for manufacturing a trench-type semiconductor power device of the present invention.
[0034] Figure 3 A diagram showing the film layer structure of a wafer provided for the method for manufacturing a trench-type semiconductor power device of the present invention.
[0035] Figure 4 It is a schematic diagram showing the structure obtained after sequentially forming a silicon oxide back sealing layer and a polysilicon back sealing layer on the back side of a wafer according to the manufacturing method of the trench type semiconductor power device of the present invention.
[0036] Figure 5 It is a schematic diagram showing a structure obtained after a polysilicon back sealing layer and a silicon oxide back sealing layer are sequentially formed on the back side of a wafer in a comparative embodiment.
[0037] Figure 6 It is a schematic diagram showing the structure obtained after forming a trench on the front side of a wafer according to the manufacturing method of a trench-type semiconductor power device of the present invention.
[0038] Figure 7 It is a schematic diagram showing the structure obtained after a silicon oxide layer is formed on the inner wall of a trench according to the manufacturing method of a trench type semiconductor power device of the present invention.
[0039] Figure 8 It is a schematic diagram showing the structure obtained after forming a polysilicon layer in the trench according to the manufacturing method of the trench type semiconductor power device of the present invention.
[0040] Fig. 9 It is a schematic diagram showing the structure obtained after etching back the field oxide layer and forming an isolation layer, a gate dielectric layer and gate polysilicon in the trench in the manufacturing method of the trench type semiconductor power device of the present invention.
[0041] Fig.10 Shown is the change in wafer warpage after each process step under different back-sealing sequences.
[0042] Fig.11 The figure shows the change in wafer warpage after each process step under different temperature combinations of silicon oxide annealing temperature + polysilicon deposition temperature.
[0043] Fig.12 The figure shows the change curve of the wafer warpage in the X direction drawn based on the data in Table 2.
[0044] Component number description
[0045] Steps S1 to S6
[0046] 1 Wafer
[0047] 101 substrate layer
[0048] 102 First epitaxial layer
[0049] 103 Second epitaxial layer
[0050] 2 Silicon oxide backing layer
[0051] 3 Polysilicon backing layer
[0052] 4 Grooves
[0053] 5 Silicon oxide layer
[0054] 501 Thermal Oxide Layer
[0055] 502 Chemical Vapor Deposition Oxide Layer
[0056] 6 Polysilicon layer
[0057] 7 Isolation Layer
[0058] 8 Gate dielectric layer
[0059] 9 Gate Polysilicon
[0060] A front
[0061] B Back DETAILED DESCRIPTION
[0062] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0063] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0064] The present invention provides a method for manufacturing a trench type semiconductor power device. Figure 1 , shown as a process flow chart of the method, comprising the following steps:
[0065] S1: providing a wafer, wherein the wafer comprises a front side and a back side which are arranged opposite to each other;
[0066] S2: sequentially forming a silicon oxide back sealing layer and a polysilicon back sealing layer on the back side of the wafer;
[0067] S3: forming a groove on the front side of the wafer;
[0068] S4: forming a silicon oxide layer on the inner wall of the trench;
[0069] S5: performing a first annealing process;
[0070] S6: forming a polysilicon layer in the trench.
[0071] Specifically, the method for manufacturing a trench-type semiconductor power device of the present invention is applicable to metal-oxide semiconductor field effect transistors (MOSFETs), shielded gate trench field effect transistors (SGTFETs), insulated gate bipolar transistors (IGBTs) or other deep trench-type semiconductor power devices using a trench process.
[0072] The following will take SGTFET as an example and describe in detail the various steps of the method for manufacturing the trench type semiconductor power device of the present invention in conjunction with the accompanying drawings.
[0073] First see Figure 2 , perform the step S1: provide a wafer 1, the wafer comprising a front side A and a back side B that are arranged opposite to each other.
[0074] As an example, see Figure 3 , which is a film layer structure diagram of the wafer 1 described in an embodiment, wherein the wafer 1 includes a substrate layer 101, a first epitaxial layer 102 and a second epitaxial layer 103 stacked in sequence from bottom to top, wherein the substrate layer 101 may be made of silicon, silicon carbide or other suitable semiconductor materials, and its conductivity type may be selected as P-type or N-type according to actual needs, and the conductivity type and specific doping concentration of the first epitaxial layer 102, and the conductivity type and specific doping concentration of the second epitaxial layer 103 may be set according to actual needs.
[0075] In other embodiments, the film layer composition of the wafer 1 may also be changed in other ways according to the different semiconductor structures actually manufactured, and no excessive restrictions are imposed here.
[0076] Please see again Figure 4 , executing the step S2: sequentially forming a silicon oxide backing layer 2 and a polysilicon backing layer 3 on the back side B of the wafer 1 .
[0077] As an example, the thickness of the silicon oxide backing layer 2 is in the range of 5 kiloangstroms to 7 kiloangstroms. In one embodiment, the thickness of the silicon oxide backing layer 2 is 6 kiloangstroms.
[0078] As an example, the silicon oxide backing layer 2 includes a low temperature oxide layer (Low Temperature Oxidation, LTO for short), and a method for forming the low temperature oxide layer includes a plasma enhanced chemical vapor deposition method (PECVD), and a deposition temperature is not higher than 200°C.
[0079] As an example, the thickness of the polysilicon back sealing layer 3 is in the range of 7 kiloangstroms to 9 kiloangstroms. In one embodiment, the thickness of the polysilicon back sealing layer 3 is 8 kiloangstroms.
[0080] Specifically, different back-sealing sequences result in different stress performances of the wafer after multiple thermal processes. Figure 5, which is a schematic diagram of a structure obtained after a polysilicon back sealing layer 3 and a silicon oxide back sealing layer 2 are sequentially formed on the back side B of the wafer 1 in a control embodiment. Compared with the back sealing sequence of the polysilicon back sealing layer 3 first and the silicon oxide back sealing layer 2 later, the present invention adopts the back sealing sequence of the silicon oxide back sealing layer 2 first and the polysilicon back sealing layer 3 later, which can optimize the stress release of the wafer itself, make the wafer stress buffer better, and reduce the wafer warpage after the thermal process.
[0081] Please see again Figure 6 , perform the step S3: form a groove 4 on the front side of the wafer 1 by dry etching and / or other suitable methods.
[0082] As an example, the bottom of the trench 4 stays in the first epitaxial layer 102 .
[0083] It should be pointed out that the specific depth, width and density of the grooves 4 can be set according to the actual requirements of the semiconductor device to be manufactured, and no excessive restrictions are imposed here.
[0084] Please see again Figure 7 , executing step S4: forming a silicon oxide layer 5 on the inner wall of the trench 4.
[0085] As an example, for a shielded gate trench field effect transistor, the silicon oxide layer 5 is used as a field oxide layer. The silicon oxide layer 5 as a field oxide layer can be a single layer structure or a multilayer structure deposited by different methods, for example, including a thermal oxide layer 501 and a chemical vapor deposition oxide layer 502 .
[0086] In other embodiments, for other deep trench semiconductor power devices using trench technology, such as metal-oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), etc., the silicon oxide layer 5 can also be used as a gate oxide layer.
[0087] Next, the step S5 is performed: performing a first annealing process.
[0088] Specifically, the first annealing process is mainly for the silicon oxide layer 5 to make its structure more compact.
[0089] As an example, the annealing temperature range of the first annealing process is 900° C.-1100° C. For example, in one embodiment, the annealing temperature of the first annealing process is 950° C.
[0090] As an example, the first annealing process may be conventional annealing, for example, the annealing time is 30 minutes, or may be rapid thermal annealing (RTA), for example, the annealing time is 30 seconds.
[0091] Please see again Figure 8, executing step S6: forming a polysilicon layer 6 in the trench 4 by chemical vapor deposition, physical vapor deposition or other suitable methods.
[0092] As an example, the polysilicon layer 6 also covers the front side of the wafer 1 . In some embodiments, a step of chemically mechanically polishing the polysilicon layer 6 is further included to remove a portion of the polysilicon layer 6 outside the groove 4 .
[0093] As an example, the deposition temperature range used when forming the polysilicon layer 6 in the trench 4 is 525° C.-580° C. For example, in one embodiment, the polysilicon deposition temperature is 550° C.
[0094] Specifically, the silicon oxide layer 5 and the polysilicon layer 6 are in the groove 4. The annealing temperature of the silicon oxide layer 5 and the temperature of the polysilicon layer 6 during deposition will have a greater effect on the wafer warpage. By optimizing the silicon oxide annealing temperature and the polysilicon deposition temperature, the introduction of thermal stress can be reduced, the performance of thermal stress resistance can be enhanced, and more redundancy can be provided for subsequent processes.
[0095] Specifically, different combinations of silicon oxide annealing temperature + polysilicon deposition temperature may have different effects on the growth orientation of polysilicon, so that the size of nucleated grains after the subsequent thermal process is different. Data show that for some combinations of silicon oxide annealing temperature + polysilicon deposition temperature, the wafer warpage (Bow value) deteriorates after different thermal processes. In the present invention, by using a silicon oxide annealing temperature of 900℃-1100℃ + a polysilicon deposition temperature of 525℃-580℃, the warpage caused by the thermal process can be further reduced and the wafer warpage can be improved.
[0096] In some embodiments, in order to further reduce wafer warpage, the present invention further adds a second annealing process for the polysilicon layer 6, with the aim of causing the polysilicon layer 6 to undergo crystal transformation, further reducing the introduction of thermal stress, enhancing the performance of thermal stress resistance, providing more redundancy for subsequent processes, and improving the problem of excessive wafer warpage after multiple thermal processes.
[0097] As an example, the annealing temperature range of the second annealing process is 850°C-950°C, and the annealing time is 10 minutes-30 minutes. For example, in one embodiment, after completing the chemical mechanical polishing of the polysilicon layer 6, an annealing step of annealing at 900°C for 20 minutes is added.
[0098] As an example, see Fig. 9For the shielded gate trench field effect transistor, after forming the source polysilicon (i.e., the polysilicon layer 6) in the trench 4, the following steps are also included: etching back the field oxide layer (i.e., the silicon oxide layer 5), forming an isolation layer 7, a gate dielectric layer 8 and a gate polysilicon 9 in the trench 4, the isolation layer 7 is located between the source polysilicon (i.e., the polysilicon layer 6) and the gate polysilicon 9, and the gate dielectric layer 8 is located between the side wall of the trench 4 and the gate polysilicon 9.
[0099] As an example, the method also includes performing body doping (called base doping for IGBT) on the upper surface layer of the second epitaxial layer 103 on at least one side of the groove 4, for example, performing P-type body doping (P-Body Dope, PBD for short), and forming a body lead-out region (not shown) on the upper surface layer of the resulting body region (not shown), wherein the body region is used to form a front PN junction to assist in forming a channel.
[0100] Subsequently, a metal interconnection layer may be further formed on the front side of the wafer 1, and a back side thinning and back side metallization process may be performed, which will not be described in detail here.
[0101] As an example, see Fig.10 , showing the change of wafer warpage after each process step under different back-sealing sequences. It can be seen that different back-sealing sequences make the stress performance of the wafer different after multiple processes. Among them, compared with the back-sealing sequence of polysilicon back-sealing layer first and silicon oxide back-sealing layer later, the back-sealing sequence of silicon oxide back-sealing layer first and polysilicon back-sealing layer later reduces the wafer warpage after each process step.
[0102] As an example, see Fig.11 , showing the change in wafer warpage after each process step under different temperature combinations of silicon oxide annealing temperature + polysilicon deposition temperature. It can be seen that in the back-sealing sequence of silicon oxide back-sealing layer first and polysilicon back-sealing layer later, further optimizing the temperature combination of silicon oxide annealing temperature + polysilicon deposition temperature can further improve the wafer warpage.
[0103] As an example, see Table 1 and Fig.12 , where Table 1 shows the change data of the wafer warpage in the X direction before and after adding the polysilicon annealing step under different field oxide layer annealing conditions and different source polysilicon deposition temperatures, #15, #18, #19, #20, and #21 represent different wafer numbers, Fig.12 The figure shows the change curve of the wafer warpage in the X direction based on the data in Table 1.
[0104] Table 1: The change in wafer warpage in the X direction before and after adding the polysilicon annealing step under different field oxide layer annealing conditions and different source polysilicon deposition temperatures.
[0105]
[0106] It can be seen that the annealing step of annealing at 900° C. for 20 minutes added after the source polysilicon deposition reduces the wafer warpage, and the bow value in the X direction is reduced by 30 μm to 90 μm.
[0107] In summary, the manufacturing method of the trench-type semiconductor power device of the present invention comprises the following steps: providing a wafer, the wafer comprising a front side and a back side that are relatively arranged; sequentially forming a silicon oxide back-sealing layer and a polysilicon back-sealing layer on the back side of the wafer; forming a groove on the front side of the wafer; forming a silicon oxide layer on the inner wall of the groove; performing a first annealing process; forming a polysilicon layer in the groove. The present invention can optimize the stress release of the wafer itself by changing the wafer back-sealing sequence, so that the wafer stress buffering is better and the wafer warpage after the thermal process is reduced. In addition, in the optional scheme of the present invention, the warpage caused by the thermal process can be further reduced by optimizing the silicon oxide annealing temperature and the polysilicon layer deposition temperature, and increasing the source polysilicon annealing step, which helps to improve the wafer warpage, reduce the product fragmentation rate, reduce the wafer warpage at the special process, and thus increase the efficiency and success rate of the tape-out, reduce the cost, and improve the competitiveness. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0108] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a trench-type semiconductor power device, characterized in that: The following steps are involved: Providing a wafer, wherein the wafer comprises a front side and a back side that are arranged opposite to each other; Sequentially forming a silicon oxide back-sealing layer and a polysilicon back-sealing layer on the back side of the wafer; forming a groove on the front side of the wafer; forming a silicon oxide layer on the inner wall of the trench; performing a first annealing process; A polysilicon layer is formed in the trench.
2. The method for manufacturing a trench type semiconductor power device according to claim 1, characterized in that: The thickness of the silicon oxide backing layer is in the range of 5 kiloangstroms to 7 kiloangstroms, and the thickness of the polysilicon backing layer is in the range of 7 kiloangstroms to 9 kiloangstroms.
3. The method for manufacturing a trench type semiconductor power device according to claim 1, characterized in that: The silicon oxide backing layer includes a low temperature oxide layer. The method for forming the low temperature oxide layer includes a plasma enhanced chemical vapor deposition method, and the deposition temperature is not higher than 200°C.
4. The method for manufacturing a trench type semiconductor power device according to claim 1, characterized in that: In the step of forming a polysilicon layer in the groove, the polysilicon layer also covers the front surface of the wafer, and the manufacturing method further includes the step of chemically mechanically polishing the polysilicon layer.
5. The method for manufacturing a trench type semiconductor power device according to claim 1, characterized in that: The trench-type semiconductor power device includes a metal-oxide semiconductor field effect transistor, a shielded gate trench field effect transistor or an insulated gate bipolar transistor.
6. The method for manufacturing a trench-type semiconductor power device according to claim 1, characterized in that: The trench-type semiconductor power device comprises a shielded gate trench field effect transistor, the silicon oxide layer comprises a field oxide layer, the polysilicon layer comprises source polysilicon, and after forming the source polysilicon in the trench, the following steps are further included: etching back the field oxide layer; An isolation layer, a gate dielectric layer and gate polysilicon are formed in the trench, wherein the isolation layer is located between the source polysilicon and the gate polysilicon, and the gate dielectric layer is located between the sidewall of the trench and the gate polysilicon.
7. The method for manufacturing a trench type semiconductor power device according to claim 1, characterized in that: The silicon oxide layer includes a gate oxide layer, and the polysilicon layer includes gate polysilicon.
8. The method for manufacturing a trench type semiconductor power device according to any one of claims 1 to 7, characterized in that: The annealing temperature used in the first annealing process is 950° C., and the deposition temperature used when forming the polysilicon layer in the trench is 550° C.
9. The method for manufacturing a trench type semiconductor power device according to claim 8, characterized in that: After the step of forming a polysilicon layer in the trench, a second annealing process is also included to cause the polysilicon layer to undergo a crystal transformation.
10. The method for manufacturing a trench type semiconductor power device according to claim 9, characterized in that: The annealing temperature range of the second annealing process is 850° C.-950° C., and the annealing time is 10 minutes-30 minutes.