Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate having a unit region and a terminal region, and having a first surface, a second surface opposite to the first surface and located in the terminal region, and a third surface located in the unit region, the second surface and the third surface being adjacent and located at different levels; the first groove structure is located in the unit region, penetrates through the third surface and extends towards the first surface, comprises a first semiconductor material layer and a first oxide layer which partially protrude out of the third surface, and extends towards a first direction parallel to the third surface; the second groove structure is located in the unit region, comprises a second semiconductor material layer and a second oxide layer which partially protrude out of the third surface and extends in the direction parallel to the first direction, the third surface is provided with a doped region between the first groove structure and the second groove structure, and the doped region extends in the second direction parallel to the third surface and perpendicular to the first direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a rectifier device of a trench metal oxide semiconductor (MOS) structure and a manufacturing method thereof. Background Art

[0002] Modern power circuits require rectifiers with high power, low losses and fast switching. For high voltage applications, PN junction gate rectifiers with high switching speeds are often used when high breakdown voltage and high operating temperature are required. For low voltage applications, Schottky barrier rectifiers are often used when high switching speeds and very low forward bias are required. Schottky barrier rectifiers are a majority carrier device that uses a metal oxide semiconductor (MOS) process to allow only a small reverse leakage current to flow during recovery. Unfortunately, when operating at elevated temperatures, Schottky barrier rectifiers suffer from undesirably high reverse leakage currents.

[0003] Some improvement measures are currently used to improve the blocking capability of Schottky rectifiers. One of such improvement methods is to use a junction barrier Schottky (JBS) rectifier, which combines a P / N junction gate with a sufficiently small Schottky barrier region to expand the space charge region from the PN junction gate, thereby eliminating the reduction of the Schottky barrier caused by the image charge.

[0004] Another such improvement method is to use Schottky Barrier Diode (SBD), which has a lower forward voltage and is beneficial to forward power loss. However, SBD also has a higher reverse leakage current, resulting in higher reverse power loss, which becomes a technical bottleneck for such devices.

[0005] Therefore, the rectifier devices in the prior art need to be further improved to obtain more ideal high power and low loss so as to be suitable for fast switching applications. Summary of the invention

[0006] The embodiments of the present disclosure relate to a semiconductor structure. The semiconductor structure includes: a substrate, which defines a unit area and a terminal area adjacent to the unit area from a top view, the substrate having a first surface, a second surface relative to the first surface and located in the terminal area, and a third surface relative to the first surface and located in the unit area, the second surface and the third surface being adjacent and at different levels; a first trench structure, which is located in the unit area and extends through the third surface to the first surface, wherein the first trench structure includes a first semiconductor material layer at least partially protruding from the third surface and a first oxide layer surrounding the first semiconductor material layer, and the first trench structure extends in a first direction parallel to the third surface; and a second trench structure, which is located in the unit area and extends through the third surface to the first surface, wherein the second trench structure includes a second semiconductor material layer at least partially protruding from the third surface and a second oxide layer surrounding the second semiconductor material layer, and the second trench structure extends in a first direction parallel to the first direction, wherein a first doping region is provided on the third surface of the substrate, and the first doping region is arranged between the first trench structure and the second trench structure from a top view, and the first doping region extends in a second direction parallel to the third surface and perpendicular to the first direction.

[0007] The embodiments of the present disclosure relate to a method for manufacturing a semiconductor structure. The method comprises: forming a first trench, a second trench, and a third trench in a substrate at intervals along a first direction and extending from a second surface to a first surface relative to the second surface, wherein the substrate defines a unit area and a terminal area from a top view, the first trench and the second trench are arranged in the unit area, and the third trench is arranged in the terminal area; forming a first oxide layer in the first trench, forming a second oxide layer in the second trench, and forming a third oxide layer in the third trench; forming a first semiconductor material layer in the first trench so that the first semiconductor material layer is surrounded by the first oxide layer and a first trench structure is formed, forming a second semiconductor material layer in the second trench so that the second semiconductor material layer is surrounded by the second oxide layer and a second trench structure is formed, and forming a third semiconductor material layer in the third trench so that the third semiconductor material layer is surrounded by the second oxide layer and a second trench structure is formed. The layer is surrounded by a third oxide layer and forms a third trench structure; a shielding layer is formed on the unit area, the first trench structure and the second trench structure; a first etching process is performed on the shielding layer to form a first opening and a second opening, the first opening extends along a first direction to expose at least part of the first semiconductor material layer, and the second opening extends along a second direction perpendicular to the first direction to expose at least part of the second surface and the first trench structure; after the first etching process, a second etching process is performed on the second opening to form a third surface of the substrate, and the first trench structure and the second trench structure at least partially protrude from the third surface of the unit area; and a first doped region is formed on the third surface exposed adjacent to the second opening, wherein from a top view, the first doped region is arranged between the first trench structure and the second trench structure and extends in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of several embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that various structures may not be drawn to scale. In fact, the dimensions of various structures may be arbitrarily enlarged or reduced for clarity of discussion.

[0009] Figure 1 Shown is a top view of a semiconductor structure according to some embodiments of the present invention;

[0010] Figure 2 The semiconductor structure according to some embodiments of the present invention is shown along Figure 1 A cross-sectional view of the A-A' tangent line is shown;

[0011] Figure 3 The semiconductor structure according to some embodiments of the present invention is shown along Figure 1 The cross-sectional view of the BB' cut line is shown;

[0012] Figure 4 The semiconductor structure according to some embodiments of the present invention is shown along Figure 1 The cross-sectional view of the C-C' tangent line is shown;

[0013] Figures 5 to 25 Shown are one or more stages in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0014] The same or similar components are marked with the same reference numerals in the drawings and detailed description. Several embodiments of the present disclosure will be immediately understood from the following detailed description in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are only examples and are not intended to be restrictive. In the present disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] The following is a detailed discussion of embodiments of the present disclosure. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0017] The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure disclosed herein, the extension direction of the channel is perpendicular to the extension direction of the trench structure, and the pitch of the channel can be adjusted according to the process capability, thereby increasing the channel density, thereby increasing the current density, and improving the electric field uniformity, thereby reducing the reverse leakage current.

[0018] Figure 1 Shown is a top view of a semiconductor structure 10 according to some embodiments of the present disclosure. Figure 2 FIG. 1 is a cross-sectional view of a semiconductor structure 10 along a cutting line AA′ according to some embodiments of the present invention. Figure 3 FIG. 1 is a cross-sectional view of the semiconductor structure 10 along the cutting line BB′ according to some embodiments of the present invention. Figure 4 The figure shows a cross-sectional view of a semiconductor structure 10 along a cut line CC' according to some embodiments of the present invention. Specifically, the semiconductor structure 10 is a trench MOS rectifier device structure having a vertical current conduction path. For example, the current of the semiconductor structure 10 can be conducted vertically through the semiconductor structure 10.

[0019] In some embodiments, the semiconductor structure 10 includes a substrate 11 , a first trench structure 21 , and a second trench structure 22 .

[0020] In some embodiments, the substrate 11 includes a base material 111 and an epitaxial layer 112 located on the base material 111. In some embodiments, the base material 111 includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the epitaxial layer 112 includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. The base material 111 is an N-type or P-type semiconductor material. The epitaxial layer 112 is an N-type or P-type semiconductor material. In some embodiments, the base material 111 and the epitaxial layer 112 have the same conductivity type, for example, the base material 111 and the epitaxial layer 112 are both N-type.

[0021] The substrate 111 has the same conductivity type doping as the epitaxial layer 112 . In some embodiments, the substrate 111 is a part of a silicon substrate or a silicon wafer. In some embodiments, the doping concentration of the substrate 111 is greater than the doping concentration of the epitaxial layer 112 .

[0022] In some embodiments, the substrate 11 is defined with a unit area A1 viewed from a top view and a terminal area A3 adjacent to the unit area. The unit area A1 is used to accommodate active components or passive components, and the terminal area A3 is used to connect to the circuit terminal. In some embodiments, the terminal area A3 is adjacent to one side of the unit area A1. In some embodiments, the terminal area A3 surrounds the unit area A1. In some embodiments, the substrate 11 has a first thickness T1 in the unit area A1, and has a second thickness T3 in the terminal area A3, and the second thickness T3 is greater than the first thickness T1.

[0023] In some embodiments, the substrate 11 may have a first surface 12A, a second surface 12B opposite to the first surface 12A and located in the terminal area A3, and a third surface 12C opposite to the first surface 12A and located in the cell area A1, the second surface 12B and the third surface 12C being adjacent and at different levels. In some embodiments, the second surface 12B and the first surface 12A may be located on opposite sides of the substrate 11. In some embodiments, the first surface 12A, the second surface 12B, and the third surface 12C may be horizontal planes. For convenience of description, the direction orthogonal to the first surface 12A, the second surface 12B, and the third surface 12C is defined as a vertical direction Z, and the plane formed by the first direction X and the second direction Y is orthogonal to the vertical direction Z. In some embodiments, the third surface 12C may be an active surface of the epitaxial layer 112. The bottom surface of the substrate 111 is the first surface 12A, which may be used to contact the metal layer (not shown in the drawings, which may be formed on the first surface 12A to contact the substrate 111, as a drain or cathode).

[0024] In some embodiments, the first trench structure 21 is located in the cell area A1 and extends through the third surface 12C to the first surface 12A. The first trench structure 21 includes a first semiconductor material layer 212 at least partially protruding from the third surface 12C and a first oxide layer 211 surrounding the first semiconductor material layer 212. In some embodiments, the top surface of the first trench structure 21 is coplanar with the second surface 12B. From a top view, the first trench structure 21 extends along the third surface 12C in the first direction X.

[0025] The first oxide layer 211 is used to electrically isolate the first semiconductor material layer 212 from the epitaxial layer 112. In other words, the first semiconductor material layer 212 is separated from the epitaxial layer 112 via the first oxide layer 211 in the trench. In some embodiments, the sidewall and bottom wall of the first semiconductor material layer 212 are in contact with the first oxide layer 211. The thickness of the first oxide layer 211 can be adjusted according to, for example, the size of the first semiconductor material layer 212 or the operating voltage. For example, the thickness of the first oxide layer 211 is less than the width of the first semiconductor material layer 212 in the trench. In some embodiments, the first semiconductor material layer 212 includes polysilicon material.

[0026] In some embodiments, the second trench structure 22 is located in the cell area A1 and extends through the third surface 12C to the first surface 12A. The second trench structure 22 includes a second semiconductor material layer 222 at least partially protruding from the third surface 12C and a second oxide layer 221 surrounding the second semiconductor material layer 222. In some embodiments, the top surface of the second trench structure 22 is coplanar with the second surface 12B. From a top view, the second trench structure 22 extends along the third surface 12C in the first direction X. In some embodiments, the second trench structure 22 is located between the first trench structure 21 and the terminal area A3.

[0027] The second oxide layer 221 is used to electrically isolate the second semiconductor material layer 222 from the epitaxial layer 112. In other words, the second semiconductor material layer 222 is separated from the epitaxial layer 112 via the second oxide layer 221 in the trench. In some embodiments, the second oxide layer 221 surrounds the second semiconductor material layer 222. In some embodiments, the sidewall and bottom wall of the second semiconductor material layer 222 are in contact with the second oxide layer 221. The thickness of the second oxide layer 221 can be adjusted according to, for example, the size of the second semiconductor material layer 222 or the operating voltage. For example, the thickness of the second oxide layer 221 is less than the width of the second semiconductor material layer 222 in the trench. In some embodiments, the first oxide layer 211 and the second oxide layer 221 include the same material. In some embodiments, the first semiconductor material layer 212 and the second semiconductor material layer 222 include the same material. In some embodiments, the second semiconductor material layer 222 includes polysilicon material. In some embodiments, the depth of the first trench structure 21 is substantially the same as the depth of the second trench structure 22. In some embodiments, the width W1 of the first trench structure 21 is substantially the same as the width W2 of the second trench structure 22 .

[0028] In some embodiments, the semiconductor structure 10 further includes a third trench structure 23. The third trench structure 23 is located in the terminal area A3 and extends from the second surface 12B to the first surface 12A. The third trench structure 23 is located at the outer periphery of the semiconductor structure 10. The third trench structure 23 includes a third semiconductor material layer 232 and a third oxide layer 231 surrounding the third semiconductor material layer 232, and the third trench structure 23 extends in the first direction X. In some embodiments, the top surface of the third trench structure 23 is coplanar with the second surface 12B. In some embodiments, the top surfaces of the first trench structure 21, the second trench structure 22, and the third trench structure 23 are coplanar. From a top view, the third trench structure 23 extends along the third surface 12C in the first direction X. In some embodiments, the second trench structure 22 is located between the first trench structure 21 and the third trench structure 23.

[0029] The third oxide layer 231 is used to electrically isolate the third semiconductor material layer 232 from the epitaxial layer 112. In other words, the third semiconductor material layer 232 is separated from the epitaxial layer 112 via the third oxide layer 231 in the trench. In some embodiments, the third oxide layer 231 surrounds the third semiconductor material layer 232. In some embodiments, the sidewall and bottom wall of the third semiconductor material layer 232 are in contact with the third oxide layer 231. The thickness of the third oxide layer 231 can be adjusted according to, for example, the size of the third semiconductor material layer 232 or the operating voltage. For example, the thickness of the third oxide layer 231 is less than the width of the third semiconductor material layer 232 in the trench. In some embodiments, the first oxide layer 211 and the third oxide layer 231 include the same material. In some embodiments, the first semiconductor material layer 212 and the third semiconductor material layer 232 include the same material. In some embodiments, the third semiconductor material layer 232 includes polysilicon material. In some embodiments, the depth of the first trench structure 21 is substantially the same as the depth of the third trench structure 23. In some embodiments, the width W1 of the first trench structure 21 is substantially the same as the width W3 of the third trench structure 23 .

[0030] In some embodiments, the semiconductor structure 10 further includes a plurality of trench structures located between the second trench structure 22 and the third trench structure 23, for example, including a fourth trench structure 24, a fifth trench structure 25, and a sixth trench structure 26. In some embodiments, the third trench structure 23 is farthest from the cell area A1 than the distances between the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 and the cell area A1. In some embodiments, the third trench structure 23 is located at the outer periphery of the semiconductor structure 10, and the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are located between the second trench structure 22 and the third trench structure 23. In some embodiments, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are located in the terminal area A3, extending from the second surface 12B to the first surface 12A and extending parallel to the first direction X. In some embodiments, the structures of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are substantially the same as the third trench structure 23. In some embodiments, the top surfaces of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are coplanar with the second surface 12B. In some embodiments, the top surfaces of the third trench structure 23, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are coplanar. From a top view, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 extend along the third surface 12C in the first direction X.

[0031] The first doping region 31 is disposed on the third surface 12C of the substrate 11. From a top view, the first doping region 31 is disposed between the first trench structure 21 and the second trench structure 22, and the first doping region 31 extends along the third surface 12C in a second direction Y perpendicular to the first direction X. In some embodiments, the semiconductor structure 10 includes a plurality of doping regions disposed between the first trench structure 21 and the second trench structure 22. In some embodiments, the first doping region 31 is located above the epitaxial layer 112 and adjacent to the third surface 12C. The first doping region 31 has a conductivity type different from that of the first doping region 31. In some embodiments, the first doping region 31 has a conductivity type different from that of the second type. In some embodiments, the first doping region 31 has a P type, and the epitaxial layer 112 has an N type. In some embodiments, the doping concentration of the first doping region 31 is greater than the doping concentration of the epitaxial layer 112. In some embodiments, the first doping region 31 includes a P type dopant, and the P type dopant may be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the P type dopant included in the first doping region 31 is boron.

[0032] In some embodiments, the second doping region 32 is disposed on the third surface 12C of the substrate 11. From a top view, the second doping region 32 is disposed between the first trench structure 21 and the second trench structure 22, adjacent to the first doping region 31. In some embodiments, the second doping region 32 is spaced apart from the first doping region 31. The distance D between the second doping region 32 and the first doping region 31 can be adjusted according to needs and process capabilities, and the distance D1 is greater than 0. In some embodiments, the second doping region 32 and the first doping region 31 extend in the same direction, for example, the second doping region 32 extends in the second direction Y. In some embodiments, the second doping region 32 is located above the epitaxial layer 112 and adjacent to the third surface 12C. The second doping region 32 has a different conductivity type from the epitaxial layer 112, for example, the second doping region 32 has a P type and the epitaxial layer 112 has an N type. The second doping region 32 has the same conductivity type as the first doping region 31, for example, both are P type. In some embodiments, the doping concentration of the second doping region 32 is greater than the doping concentration of the epitaxial layer 112. In some embodiments, the doping concentration of the second doping region 32 is substantially the same as the doping concentration of the first doping region 31. In some embodiments, the second doping region 32 includes a P-type dopant, and the P-type dopant may be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the P-type dopant included in the second doping region 32 is boron.

[0033] The shielding layer 35 is located in the cell area A1 and on the second surface 12B. In some embodiments, the shielding layer 35 is separated from the terminal area A3. In some embodiments, the shielding layer 35 covers a portion of the first trench structure 21 and a portion of the second trench structure 22. The upper surface of the shielding layer 35 is higher than the first doping region 31 and the second doping region 32. At least a portion of the first semiconductor material layer 212 and at least a portion of the second semiconductor material layer 222 are exposed from the shielding layer 35. At least a portion of the first oxide layer 211 and at least a portion of the second oxide layer 221 are exposed from the shielding layer 35.

[0034] From a top view, the shielding layer 35 is located between the first doping region 31 and the second doping region 32. In some embodiments, the shielding layer 35 includes a first opening 41 and a second opening 42. The first opening 41 extends along a first direction X to expose at least a portion of the first semiconductor material layer 212, and the second opening 42 extends along a second direction Y perpendicular to the first direction X to expose at least a portion of the second surface 12B and the first trench structure 21. The first opening 41 and the second opening 42 intersect. The first doping region 31 is located in the second opening 42. In some embodiments, the shielding layer 35 further includes a third opening 43 extending along a second direction Y perpendicular to the first direction X to expose at least a portion of the second surface 12B and the first trench structure 21. The third opening 43 is arranged parallel to the second opening 42 and also intersects with the first opening 41. The second doping region 32 is located in the third opening 43. From a top view, the first doping region 31 and the second doping region 32 are arranged between the first trench structure 21 and the second trench structure 22, and are arranged alternately with the shielding layer 35.

[0035] In some embodiments, the shielding layer 35 includes a fourth oxide layer 351 and a fourth semiconductor material layer 352 disposed on the fourth oxide layer 351. The fourth oxide layer 351 is disposed on the second surface 12B and covers at least a portion of the first trench structure 21 and at least a portion of the second trench structure 22. The fourth oxide layer 351 is in contact with the first oxide layer 211 and the second oxide layer 221. In some embodiments, the fourth oxide layer 351 is a gate oxide layer. In some embodiments, the thickness of the fourth oxide layer 351 is to In some embodiments, the fourth semiconductor material layer 352 includes polysilicon material.

[0036] In some embodiments, the third surface 12C of the substrate 11 is further provided with a third doping region 33. From a top view, the third doping region 33 is disposed at the periphery of the unit area A1 and extends in the first direction X. In some embodiments, the third doping region 33 is disposed between the second trench structure 22 and the third trench structure 23. In some embodiments, the third doping region 33 is disposed between the second trench structure 22 and the terminal area A3. The second trench structure 22 is located between the first doping region 31 and the third doping region 33. In some embodiments, the third doping region 33 is located above the epitaxial layer 112 and is adjacent to the third surface 12C. The third doping region 33 has a different conductivity type from the epitaxial layer 112, for example, the third doping region 33 has a P type and the epitaxial layer 112 has an N type. The third doping region 33, the second doping region 32 and the first doping region 31 have the same conductivity type, for example, all are P type. In some embodiments, the doping concentration of the third doping region 33 is greater than the doping concentration of the epitaxial layer 112. In some embodiments, the first doping region 31, the second doping region 32, and the third doping region 33 are heavily doped regions. In some embodiments, the first doping region 31, the second doping region 32, and the third doping region 33 are body doping regions. In some embodiments, the doping concentration of the first doping region 31, the doping concentration of the second doping region 32, and the doping concentration of the third doping region 33 are substantially the same. In some embodiments, the third doping region 33 includes a P-type dopant, and the P-type dopant may be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the P-type dopant included in the third doping region 33 is boron. The width W5 of the third doping region 33 may be the same as or different from the width W4 of the first doping region 31. In some embodiments, the width W5 of the third doping region 33 is substantially the same as the width W4 of the first doping region 31.

[0037] In some embodiments, the third doped region 33 is a first mesa surface between the cell region A1 and the terminal region A3. In some embodiments, the first mesa surface separates the second trench structure 22 of the cell region A1 from the third trench structure 23 of the terminal region A3. The width D2 of the first mesa surface can be controlled by the positions of the second trench structure 22 and the third trench structure 23. In some embodiments, the width D2 of the first mesa surface can be controlled by the positions of the second trench structure 22 and the fourth trench structure 24.

[0038] The semiconductor structure 10 further includes a conductive layer 38, which electrically connects the first trench structure 21 and the second trench structure 22. The conductive layer 38 is disposed above the first doped region 31 and the second doped region 32, and covers at least a portion of the shielding layer 35. The conductive layer 38 is also disposed in the first opening 41, the second opening 42, and the third opening 43, and is electrically connected to the first semiconductor material layer 212 and the second semiconductor material layer 222. In some embodiments, the conductive layer 38 extends along the sidewall of the shielding layer 35, and contacts and electrically connects to the first semiconductor material layer 212 and the second semiconductor material layer 222. In some embodiments, the conductive layer 38 contacts and electrically connects to portions of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26. In some embodiments, the conductive layer 38 includes a conductive material, such as a metal, such as but not limited to copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), titanium nitride (TiN), aluminum silicon alloy (AlSi) alloy, aluminum silicon copper (AlSiCu) alloy or other metals or alloys. In some embodiments, the portion of the conductive layer 38 surrounded by the shielding layer 35 serves as a conductive plug 383. In some embodiments, the conductive plug 383 is a columnar configuration having substantially the same width along the vertical direction Z. In some embodiments, the conductive plug 383 is a configuration that is wide at the top and narrow at the bottom, and the width of the conductive plug 383 has a tendency to decrease along the vertical direction Z as the conductive layer 38 moves toward the first surface 12A.

[0039] In some embodiments, the conductive layer 38 includes a first conductive layer 381 disposed on the shielding layer 35 and extending along the sidewall of the shielding layer 35, and contacting the first semiconductor material layer 212 and the second semiconductor material layer 222. In some embodiments, the first conductive layer 381 is a seed layer. The conductive layer 38 includes a second conductive layer 382 disposed on the first conductive layer 381 and extending along the sidewall of the first conductive layer 381, and contacting the first semiconductor material layer 212 and the second semiconductor material layer 222.

[0040] In some embodiments, the conductive layer 38 is disposed in the cell area A1 and the terminal area A3. The conductive layer 38 is disposed above the third doping area 33. The semiconductor structure 10 further includes a fifth oxide layer 37 disposed between the third trench structure 23 and the conductive layer 38. The fifth oxide layer 37 is disposed in the terminal area A3 and is located on the second surface 12B. In some embodiments, the fifth oxide layer 37 is disposed above the third trench structure 23, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26. In some embodiments, the conductive layer 38 is disposed above the first doping area 31, the second doping area 32, and the fifth oxide layer 37. In some embodiments, at least a portion of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 is exposed from the fifth oxide layer 37, and contacts and is electrically connected to the conductive layer 38. In some embodiments, the conductive layer 38 passes through the fifth oxide layer 37 and is electrically connected to the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26. In some embodiments, an edge 371 of the fifth oxide layer 37 is exposed from the conductive layer 38 .

[0041] In some embodiments, the third trench structure 23 is covered by a fifth oxide layer 37. In some embodiments, the fifth oxide layer 37 is located between the third trench structure 23 and the conductive layer 38, and electrically isolates the third trench structure 23 from the conductive layer 38. The third trench structure 23 is located at the periphery of the semiconductor structure 10 and is floated or dummy to prevent the expansion of the depletion region when the semiconductor structure 10 is reverse biased.

[0042] When the forward voltage is Figure 1 and Figure 4 As indicated by the marked arrows, the current may flow from the conductive layer 38 disposed in the second opening 42 into the first doped region 31, from the first doped region 31 into the epitaxial layer 112, and from the third surface 12C to the first surface 12A. When the forward voltage is applied, the current may also flow from the conductive layer 38 disposed in the third opening 43 into the second doped region 32, from the second doped region 32 into the epitaxial layer 112, and from the third surface 12C to the first surface 12A. In some embodiments, the active surface of the semiconductor structure 10 is the third surface 12C. The current of the semiconductor structure 10 may flow in a direction orthogonal to the active surface of the semiconductor structure 10. In some embodiments, the current of the semiconductor structure 10 flows along the vertical direction Z.

[0043] In some embodiments, the first doping region 31 and the second doping region 32 respectively form a second mesa between the first trench structure 21 and the second trench structure 22. In some embodiments, the width of the second mesa can be regulated by the positions of the first trench structure 21 and the second trench structure 22. The first trench structure 21 and the second trench structure 22 can reduce the electric field at the second mesa, thereby reducing the reverse leakage current of the semiconductor structure 10, and the extension direction of the channel is perpendicular to the extension direction of the first trench structure 21 and the second trench structure 22, that is, the channel position can be adjusted by the process (for example, making the channel narrower), so that the forward voltage is lower, and the channel density can be increased, thereby improving the current density.

[0044] Figure 5 to Figure 25 One or more stages in a method of manufacturing a semiconductor structure according to some embodiments of the present invention are shown. At least some of these drawings have been simplified to facilitate a better understanding of the aspects of the present disclosure.

[0045] Reference Figure 5 and Figure 6 , the substrate 11 may include a base material 111 and an epitaxial layer 112 located on the base material 111. The manufacturing method includes performing epitaxial growth on the base material 111 to form the epitaxial layer 112. The base material 111 has a first surface 12A of the base material 11, and the epitaxial layer 112 has a second surface 12B of the base material 11, and the first surface 12A is opposite to the second surface 12B. In some embodiments, ion implantation is performed simultaneously with the epitaxial growth, and ions with N-type electrical properties are implanted to form the N-type epitaxial layer 112.

[0046] On the epitaxial layer 112, a Figure 5 The patterned shielding layer 113 (hereinafter collectively referred to as the first shielding layer) is used to define Figure 6 The positions of the first trench 210, the second trench 220 and the third trench 230 are determined, and the first trench 210, the second trench 220 and the third trench 230 are formed by performing an etching process (such as a plasma dry etching process) on the epitaxial layer 112 through the first shielding layer 113. The etching process needle removes the epitaxial layer 112 from the second surface 12B and stops in the epitaxial layer 112. According to the position defined by the first shielding layer 113, the first trench 210, the second trench 220 and the third trench 230 are formed in the substrate 11 at intervals along the first direction X and extend from the second surface 12B to the first surface 12A relative to the second surface. The first trench 210 and the second trench 220 are formed in the unit area A1 of the substrate 11, and the third trench 230 is formed in the terminal area A3 of the substrate 11.

[0047] In some embodiments, the first groove 210, the second groove 220 and the third groove 230 may have vertical sidewalls. The first groove 210, the second groove 220 and the third groove 230 may have arc-shaped bottom surfaces. In addition, the first groove 210, the second groove 220 and the third groove 230 may be circular, elliptical, rectangular or polygonal. In some embodiments, the first groove 210, the second groove 220 and the third groove 230 have the same width. In some embodiments, the first groove 210, the second groove 220 and the third groove 230 have the same depth. In some embodiments, the fourth groove 240, the fifth groove 250 and the sixth groove 260 are formed in the substrate 11 at intervals along the first direction X and extend from the second surface 12B to the first surface 12A relative to the second surface. The fourth groove 240, the fifth groove 250 and the sixth groove 260 are located between the second groove 220 and the third groove 230.

[0048] Reference Figure 7 , the manufacturing method includes forming an inner-trench oxide layer 219 in the first trench 210, the second trench 220, and the third trench 230. In some embodiments, the inner-trench oxide layer 129 covers the second surface 12B. In some embodiments, the inner-trench oxide layer 219 can be formed by thermal oxidation technology or other deposition processes. In some embodiments, the inner-trench oxide layer 219 can be conformally or conformally deposited on the inner side surfaces (including the opposite sidewalls and the bottom extending between the sidewalls) of the first trench 210, the second trench 220, and the third trench 230. In some embodiments, the inner-trench oxide layer 219 can be filled into the first trench 210, the second trench 220, and the third trench 230 through a deposition process, so that the inner-trench oxide layer 219 forms at least one groove in the first trench 210, the second trench 220, and the third trench 230, respectively. In some embodiments, the portion of the in-trench oxide layer 129 in the first trench 210 is the first oxide layer 211, the portion in the second trench 220 is the second oxide layer 221, and the portion in the third trench 230 is the third oxide layer 231. The first oxide layer 211, the second oxide layer 221, and the third oxide layer 231 are formed simultaneously.

[0049] Reference Figure 8 The manufacturing method includes forming a first semiconductor material 215, a second semiconductor material 225, and a third semiconductor material 235 in the first trench 210, the second trench 220, and the third trench 230, respectively. In some embodiments, the first semiconductor material 215 is placed in the first trench 210 and on the top surface of the first oxide layer 211, the second semiconductor material 225 is placed in the second trench 220 and on the top surface of the second oxide layer 225, and the third semiconductor material 235 is placed in the third trench 230 and on the top surface of the third oxide layer 231.

[0050] The oxide layer 219 in the trench may surround the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235. In some embodiments, the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 may be formed by physical vapor deposition (PVD), such as sputtering or spraying. In some embodiments, the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 may be formed by electroplating or CVD. In some embodiments, the semiconductor material may cover the oxide layer 219 in the trench, and then a dry etching process is performed to remove the semiconductor material outside the first trench 210, the second trench 220, and the third trench 230 by etching or other methods to form the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235. In some embodiments, the semiconductor material includes polysilicon.

[0051] Reference Fig. 9 The manufacturing method includes forming a first semiconductor material layer 212, a second semiconductor material layer 222, and a third semiconductor material layer 232 in the first trench 210, the second trench 220, and the third trench 230, respectively, so that the first semiconductor material layer 212 is surrounded by the first oxide layer 211 and forms a first trench structure 21, the second semiconductor material layer 222 is surrounded by the second oxide layer 221 and forms a second trench structure 22, and the third semiconductor material layer 232 is surrounded by the third oxide layer 231 and forms a third trench structure 23. In some embodiments, the top surfaces of the first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232 are substantially coplanar with the second surface 12B.

[0052] In some embodiments, the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235 are etched to form the first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232, respectively. The etching process is used to remove at least a portion of the first semiconductor material 215 in the first trench 210, at least a portion of the second semiconductor material 225 in the second trench 220, and at least a portion of the third semiconductor material 235 in the third trench 230. The first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232 can be defined by a second mask layer (not shown) and formed by a dry etching process. The dry etching process removes a portion of the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235, and stops at a predetermined depth of the first semiconductor material 215, the second semiconductor material 225, and the third semiconductor material 235.

[0053] For the sake of convenience, the first semiconductor material layer 212 and the first oxide layer 211 are collectively referred to as the first trench structure 21, the second semiconductor material layer 222 and the second oxide layer 221 are collectively referred to as the second trench structure 22, and similarly, the third semiconductor material layer 232 and the third oxide layer 231 are collectively referred to as the third trench structure 23. The first trench structure 21, the second trench structure 22, and the third trench structure 23 are formed simultaneously. In some embodiments, the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are formed simultaneously with the first trench structure 21, the second trench structure 22, and the third trench structure 23.

[0054] In some embodiments, an oxide layer 370 is formed on the third trench structure 23 so that the oxide layer 370 covers the third trench structure 23. Fig.10 , the manufacturing method includes forming an oxide layer 370 on the first trench structure 21, the second trench structure 22, and the third trench structure 23. In some embodiments, the oxide layer 370 is formed on the oxide layer 219 in the trench and covers the first trench structure 21, the second trench structure 22, and the third trench structure 23. The oxide layer 370 is in contact with the first semiconductor material layer 212, the second semiconductor material layer 222, and the third semiconductor material layer 232. In some embodiments, the oxide layer 370 is also in contact with the semiconductor material layers of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26.

[0055] The oxide layer 370 and the in-groove oxide layer 219 may include the same or different materials. In some embodiments, the oxide layer 370 may be formed by ALD, CVD or other deposition processes. In some embodiments, after the oxide layer 370 is formed, a grinding process, such as a CMP process, is performed to grind the top surface of the oxide layer 370 flat.

[0056] Reference Fig.11 The manufacturing method includes removing a portion of the oxide layer 370 and a portion of the oxide layer 219 in the trench, so that the substrate 11 and the first trench structure 21 and the second trench structure 22 located in the cell area A1 are exposed. In some embodiments, the oxide layer 370 and the oxide layer 219 in the trench are partially removed by lithography and etching processes. In some embodiments, at least a portion of the semiconductor material 112 of the fourth trench structure 24, the fifth trench structure 25, and the sixth trench structure 26 are exposed from the oxide layer 370. In some embodiments, after removing a portion of the oxide layer 370 and a portion of the oxide layer 219 in the trench, the oxide layer 370 and the oxide layer 219 in the trench are only disposed in the terminal area A3, and the oxide layer 370 covers the oxide layer 219 in the trench and the third trench structure 23, and the second surface 12B of the cell area is exposed. For the convenience of description, the oxide layer 219 in the trench and the oxide layer 370 located in the terminal area A3 are collectively referred to as the fifth oxide layer 37 below.

[0057] The manufacturing method includes forming a shielding layer 35 on the cell area A1, the first trench structure 21 and the second trench structure 22. Fig.12 , the manufacturing method includes forming a fourth oxide layer 351 on the second surface 12B of the unit area and the fifth oxide layer 37, and forming a fourth semiconductor material layer 352 on the fourth oxide layer 351. The fourth oxide layer 351 and the fifth oxide layer 37 may include the same or different materials. In some embodiments, the thickness of the fourth oxide layer 351 is less than that of the fifth oxide layer 37. In some embodiments, the fourth oxide layer 351 contacts the sidewall of the fifth oxide layer 37, and the fourth semiconductor material layer 352 contacts the sidewall and top surface of the fifth oxide layer 37. In some embodiments, the fourth oxide layer 351 can be formed by thermal oxidation technology or other deposition processes. In some embodiments, the fourth semiconductor material layer 352 can be formed by PVD, such as sputtering or spraying. In some embodiments, the fourth semiconductor material layer 352 can be formed by electroplating or CVD.

[0058] The manufacturing method includes performing an etching process on the shielding layer 35 to form a first opening 41 , a second opening 42 and a third opening 43 . Fig.13 FIG. 1 is a top view of a stage in a method of manufacturing a semiconductor structure 10 according to some embodiments of the present disclosure. Fig.14 FIG. 1 is a diagram of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Fig.13 The cross-section along the tangent line AA' at the stage shown. Fig.15 FIG. 1 is a diagram of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Fig.12 The cross-section along the tangent line BB' at the shown stage. Fig.16 FIG. 1 is a diagram of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Fig.13 The cross-section along the tangent line CC' at the stage shown.

[0059] Reference Figures 13 to 16 The manufacturing method includes performing a first etching process on the shielding layer 35 to form a first opening 41 extending along a first direction X to expose at least a portion of the first semiconductor material layer 212, and forming an opening 421 and an opening 431 extending along a second direction Y perpendicular to the first direction and spaced apart from each other to expose at least a portion of the second surface 12B and the first trench structure 21. The first etching process also includes removing a portion of the fourth oxide layer 351 and a portion of the fourth semiconductor material layer 352, so that the shielding layer 35 is only disposed on the cell area A1, the first trench structure 21 and the second trench structure 22, while the second surface 12B between the second trench structure 22 and the terminal area A3 is exposed, and the fifth oxide layer 37 is also exposed.

[0060] In some embodiments, a patterned shielding layer (hereinafter collectively referred to as the third shielding layer) is formed on the fourth semiconductor material layer 352 (not shown). The first opening 41 and the openings 421 and 431 can be defined by the third shielding layer and formed by an etching process. The etching process removes the fourth oxide layer 351 and the fourth semiconductor material layer 352 and stops at the second surface 12B or the upper surface of the first trench structure 21 and the second trench structure 22. According to the position defined by the third shielding layer, the first opening 41 covers at least a portion of the first semiconductor material layer 212, and the openings 421 and 431 may cover the first trench structure 21 and a portion of the second surface 12B adjacent to the first trench structure 21. In some embodiments, the first opening 41 extends downward to the top surface of the first semiconductor material layer 212. In some embodiments, the openings 421 and 431 extend downward to the top surface of the first trench structure 21 and the second surface 12B.

[0061] Reference Figures 17 to 19 The manufacturing method includes performing a second etching process on the openings 421 and 431 after the first etching process, so that the substrate 11 forms a third surface 12C, and the first trench structure 21 and the second trench structure 22 at least partially protrude from the third surface 12C of the unit area A1, and form a second opening 42 and a third opening 43. Fig.17 FIG. 1 is a top view of a stage in a method of fabricating a semiconductor structure according to some embodiments of the present invention. Fig.18 FIG. 1 is a diagram of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Fig.17 The cross-section along the tangent line AA' at the stage shown. Fig.19 FIG. 1 is a diagram of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Fig.17 The cross-section along the tangent line CC' at the stage shown.

[0062] The manufacturing method includes partially removing the epitaxial layer 112 using the shielding layer 35 as a shield. In some embodiments, the exposed epitaxial layer 112 is etched using the shielding layer 35 and the fifth oxide layer 37 as a shield. In some embodiments, the openings 421 and 431 are redefined as the second opening 42 and the third opening 43 by a second etching process. In some embodiments, the sidewalls of the second opening 42 and the third opening 43 include the shielding layer 35 and a portion of the epitaxial layer 112. In some embodiments, Fig.12 The bottom of the middle openings 421, 431 is higher than or approximately equal to Fig.16 In some embodiments, the depths of the second opening 42 and the third opening 43 are greater than the depths of the openings 421 and 431.

[0063] After the second etching process, the substrate 11 has a first thickness T1 in the cell region A1 and a second thickness T3 in the terminal region A3, and the second thickness T3 is greater than the first thickness T1. In some embodiments, the level of the fifth oxide layer 37 is higher than the level of the shielding layer 35, and the level of the shielding layer 35 is higher than the level of the third surface 12C.

[0064] Reference Figures 20 to 22 The manufacturing method includes forming a first doping region 31 on the third surface 12C exposed by the second opening 42 and forming a second doping region 32 on the third surface 12C exposed by the third opening 43. From a top view, the first doping region 31 and the second doping region 32 are respectively disposed between the first trench structure 21 and the second trench structure 22, and extend in the second direction Y. The manufacturing method also includes forming a third doping region 33 between the unit area A1 and the terminal area A3, wherein the first doping region 31 is separated from the third doping region 33. From a top view, the second trench structure 22 is located between the first doping region 31 and the third doping region 33. Fig.19 FIG. 1 is a top view of a stage in a method of fabricating a semiconductor structure according to some embodiments of the present invention. Fig. 20 FIG. 1 is a diagram of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Fig.18 The cross-section along the tangent line AA' at the stage shown. Fig.21 FIG. 1 is a diagram of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Fig.19 The cross-section along the tangent line BB' at the shown stage.

[0065] The first doping region 31, the second doping region 32 and the third doping region 33 may be formed by diffusion or ion implantation from the third surface 12C. After the first doping region 31, the second doping region 32 and the third doping region 33 are formed, the first trench structure 21 and the second trench structure 22 at least partially protrude from the first doping region 31, the second doping region 32 and the third doping region 33.

[0066] The depth of the first doping region 31, the second doping region 32 and the third doping region 33 is less than the depth of the first trench structure 21 and the second trench structure 22. In other words, the bottom of the first doping region 31, the second doping region 32 and the third doping region 33 will be higher than the bottom of the first trench structure 21 and the second trench structure 22. In some embodiments, the coverage of the first doping region 31, the second doping region 32 and the third doping region 33 is defined in the unit area A1, and is a portion of the epitaxial layer 112 outside the shielding layer 35, the first trench structure 21 and the second trench structure 22. In some embodiments, an annealing process is performed after the ion implantation process to diffuse the doped ions. In some embodiments, the doped ions are, for example, boron ions, aluminum ions, gallium ions, indium ions, etc. In some embodiments, boron ions are implanted into the first doping region 31, the second doping region 32 and the third doping region 33.

[0067] In some embodiments, a patterned shielding layer (hereinafter collectively referred to as the third shielding layer) is formed on the shielding layer 35 and the fifth oxide layer 37 to define the positions of the first doping region 31, the second doping region 32, and the third doping region 33, and the conductivity type and depth of the first doping region 31, the second doping region 32, and the third doping region 33 are defined by adjusting the ions, energy, and dose of the diffusion or ion implantation process. Ions are implanted into the third surface 12C along the vertical direction Z. In some embodiments, the third shielding layer is formed by performing a photolithography process using a photomask having a corresponding pattern. In some embodiments, the first doping region 31, the second doping region 32, and the third doping region 33 are formed separately, and an annealing process is performed after each ion implantation process on the third surface 12C to diffuse the doped ions.

[0068] Reference Figures 23 to 25 , the manufacturing method includes forming a conductive layer 38 on the first semiconductor material layer 212, the second semiconductor material layer 222 and the third semiconductor material layer 232. The conductive layer 38 can be formed by electroplating or CVD. The material of the conductive layer 38 may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), titanium nitride (TiN), aluminum silicon alloy (AlSi) alloy, aluminum silicon copper (AlSiCu) alloy or other metals or alloys. The first trench structure 21 and the second trench structure 22 are electrically connected to the conductive layer 38. In some embodiments, the manufacturing method includes further removing a portion of the conductive layer 38 at the edge of the terminal area A3, so that the edge 371 of the fifth oxide layer 37 is exposed from the conductive layer 38.

[0069] The manufacturing method includes forming a first conductive layer 381 on the shielding layer 35, the third surface 12C and the fifth oxide layer 37. The first conductive layer 381 extends along the sidewall of the shielding layer 35 and contacts the first semiconductor material layer 212 and the second semiconductor material layer 222. In some embodiments, the first conductive layer 381 includes titanium (Ti).

[0070] The manufacturing method includes forming a second conductive layer 382 disposed on the first conductive layer 381, extending along the sidewall of the first conductive layer 381, and contacting the first semiconductor material layer 212 and the second semiconductor material layer 222. In some embodiments, the second conductive layer 382 includes titanium nitride (TiN).

[0071] The semiconductor structure 10 formed by the above steps can be Figures 1 to 4 The semiconductor structure 10 shown is substantially the same. The semiconductor structure 10 has a first doping region 31 and a second doping region 32 disposed between the first trench structure 21 and the second trench structure 22, and the first doping region 31 and the second doping region 32 are spaced apart from each other and extend in a second direction Y) parallel to the third surface 12C and perpendicular to the first direction X, thereby achieving an effect of increasing the channel density.

[0072] According to the structure and process of the present disclosure described above, under the same purpose and concept, the steps in the above process can be adjusted or replaced in sequence to achieve the same or similar semiconductor structure.

[0073] Spatially relative terms such as "under," "below," "lower," "above," "upper," "left," "right," and the like may be used herein for ease of description to describe the relationship of one component or feature to another or more components or features as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device when in use or operating in addition to the orientation depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be intermediate components.

[0074] As used herein, the terms "approximately", "substantially", "substantially" and "about" are used to describe and explain small changes. When used in conjunction with an event or situation, the term can refer to an instance where the event or situation occurs precisely as well as an instance where the event or situation is close to occurring. As used herein with respect to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1% or ±0.5% of a given value or range. Ranges may be expressed herein as one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise indicated. The term "substantially coplanar" may refer to a position difference of two surfaces positioned along the same plane within a few microns (μm), such as a position difference positioned along the same plane within 10 μm, within 5 μm, within 1 μm or within 0.5 μm. When a value or characteristic is referred to as being "substantially" the same, the term may refer to a value within ±10%, ±5%, ±1% or ±0.5% of the average value of the value. The foregoing outlines the features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure can be easily used as a basis for designing or modifying other processes and structures to facilitate the implementation of the same or similar purposes and / or to achieve the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, defining a unit area and a terminal area adjacent to the unit area as viewed from a top view, the substrate having a first surface, a second surface opposite to the first surface and located in the terminal area, and a third surface opposite to the first surface and located in the unit area, the second surface being adjacent to the third surface and being at different levels; A first trench structure is located in the cell area and extends through the third surface toward the first surface, wherein the first trench structure includes a first semiconductor material layer at least partially protruding from the third surface and a first oxide layer surrounding the first semiconductor material layer, and the first trench structure extends in a first direction parallel to the third surface; as well as a second trench structure located in the cell area and extending through the third surface toward the first surface, wherein the second trench structure includes a second semiconductor material layer at least partially protruding from the third surface and a second oxide layer surrounding the second semiconductor material layer, and the second trench structure extends in parallel with the first direction, The third surface of the substrate is provided with a first doped region. From a top view, the first doped region is arranged between the first trench structure and the second trench structure, and the first doped region extends in a second direction parallel to the third surface and perpendicular to the first direction.

2. The semiconductor structure according to claim 1, wherein the third surface of the substrate is further provided with a second doped region, and from a top view, the second doped region is arranged between the first trench structure and the second trench structure, adjacent to the first doped region, and the second doped region extends in the second direction.

3. The semiconductor structure according to claim 2, further comprising: The shielding layer is located in the unit area and on the second surface, wherein the shielding layer is located between the first doping area and the second doping area from a top view.

4. The semiconductor structure according to claim 3, wherein the shielding layer comprises a fourth oxide layer and a fourth semiconductor material layer disposed on the fourth oxide layer, and the fourth oxide layer is disposed on the second surface and covers at least a portion of the first trench structure and at least a portion of the second trench structure.

5. The semiconductor structure according to claim 3, further comprising: The conductive layer is disposed above the first doping region and the second doping region and covers at least a portion of the shielding layer. The semiconductor structure according to claim 5 , wherein the conductive layer is electrically connected to the first semiconductor material layer and the second semiconductor material layer. 7 . The semiconductor structure according to claim 5 , wherein the conductive layer extends along a side wall of the shielding layer and contacts the first semiconductor material layer.

8. The semiconductor structure according to claim 1, further comprising: The third trench structure is located in the terminal region and extends from the second surface to the first surface, wherein the third trench structure includes a third semiconductor material layer and a third oxide layer surrounding the third semiconductor material layer, and the third trench structure extends in parallel with the first direction. 9 . The semiconductor structure of claim 8 , wherein a width of the first trench structure is substantially the same as a width of the third trench structure.

10. The semiconductor structure of claim 8, wherein a depth of the first trench structure is substantially the same as a depth of the third trench structure. The semiconductor structure according to claim 8 , wherein the third trench structure is located at a periphery of the semiconductor structure.

12. The semiconductor structure of claim 11, further comprising: a fourth trench structure, located in the terminal region, between the unit region and the third trench structure, extending from the second surface to the first surface and extending in parallel with the first direction; a fifth oxide layer, disposed above the third trench structure and above the fourth trench structure; as well as A conductive layer is disposed above the first doped region, above the second doped region and above the fifth oxide layer, The conductive layer is electrically connected to the fourth trench structure through the fifth oxide layer, and the fifth oxide layer electrically isolates the third semiconductor material layer from the conductive layer. 13 . The semiconductor structure of claim 1 , wherein the substrate has a first thickness in the cell region and a second thickness in the termination region, the second thickness being greater than the first thickness. 14 . The semiconductor structure according to claim 1 , wherein a third doped region is further disposed on the third surface of the substrate, and from a top view, the third doped region is disposed at a periphery of the unit region and extends toward the first direction. The semiconductor structure according to claim 1 , wherein the first trench structure is electrically connected to the second trench structure. 16 . The semiconductor structure according to claim 8 , wherein top surfaces of the first trench structure, the second trench structure, and the third trench structure are coplanar. 17 . The semiconductor structure of claim 1 , wherein top surfaces of the first trench structure, the second trench structure, and the second surface are coplanar.

18. A method for manufacturing a semiconductor structure, characterized in that: include: A first trench, a second trench, and a third trench are formed in a substrate at intervals along a first direction and extending from a second surface to a first surface opposite to the second surface, wherein the substrate defines a cell region and a terminal region viewed from a top view, the first trench and the second trench are disposed in the cell region, and the third trench is disposed in the terminal region; forming a first oxide layer in the first trench, forming a second oxide layer in the second trench, and forming a third oxide layer in the third trench; forming a first semiconductor material layer in the first trench so that the first semiconductor material layer is surrounded by the first oxide layer and a first trench structure is formed, forming a second semiconductor material layer in the second trench so that the second semiconductor material layer is surrounded by the second oxide layer and a second trench structure is formed, and forming a third semiconductor material layer in the third trench so that the third semiconductor material layer is surrounded by the third oxide layer and a third trench structure is formed; forming a shielding layer on the cell area, the first trench structure and the second trench structure; Performing a first etching process on the shielding layer to form a first opening and a second opening, wherein the first opening extends along a first direction to expose at least a portion of the first semiconductor material layer, and the second opening extends along a second direction perpendicular to the first direction to expose at least a portion of the second surface and the first trench structure; After the first etching process, performing a second etching process on the second opening to form a third surface on the substrate, and to make the first trench structure and the second trench structure at least partially protrude from the third surface of the cell region; as well as A first doped region is formed on the third surface exposed adjacent to the second opening, wherein the first doped region is disposed between the first trench structure and the second trench structure and extends toward the second direction when viewed from a top view.

19. The manufacturing method according to claim 18, wherein forming the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer further comprises: Placing a first semiconductor material in the first trench so that a top surface of the first semiconductor material is substantially coplanar with a top surface of the first oxide layer, placing a second semiconductor material in the second trench so that a top surface of the second semiconductor material is coplanar with a top surface of the second oxide layer, and placing a third semiconductor material in the third trench so that a top surface of the third semiconductor material is substantially coplanar with a top surface of the third oxide layer; performing a third etching process to remove at least a portion of the first semiconductor material in the first trench, at least a portion of the second semiconductor material in the second trench, and at least a portion of the third semiconductor material in the third trench, After the third etching process, the top surfaces of the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are substantially coplanar with the second surface of the substrate. 20 . The manufacturing method according to claim 18 , wherein after the second etching process, the substrate has a first thickness in the cell region and a second thickness in the terminal region, and the second thickness is greater than the first thickness.

21. The manufacturing method according to claim 18, further comprising: forming a second doped region between the cell region and the terminal region, The first doping region is separated from the second doping region, and the second trench structure is located between the first doping region and the second doping region from a top view. 22 . The manufacturing method according to claim 18 , wherein the first oxide layer, the second oxide layer, and the third oxide layer are formed simultaneously.

23. The manufacturing method according to claim 21, further comprising: forming a conductive layer on the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer, The first trench structure and the second trench structure are electrically connected to the conductive layer. 24 . The manufacturing method according to claim 18 , wherein forming the first doped region comprises implanting ions into the third surface exposed adjacent to the second opening.

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