Transistor, manufacturing method thereof and electronic device

Abstract

The invention discloses a transistor, a manufacturing method thereof and an electronic device, a super junction layer comprises at least one of a P-type buffer structure and an N-type buffer structure, the P-type buffer structure is arranged between a P column and a drift layer, and the N-type buffer structure is arranged between an N column and the drift layer. Therefore, the P-type buffer structure can be equivalent to the contact surface between the longitudinal extension P column and the drift layer, and the N-type buffer structure can be equivalent to the contact surface between the longitudinal extension N column and the drift layer, thereby avoiding the generation of local hot spots between the super junction layer and the drift layer, avoiding the damage and failure of the transistor, and improving the reliability of the transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a transistor, a manufacturing method thereof and an electronic device. Background Art

[0002] Transistors such as Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) generally include: a substrate and an epitaxial layer arranged on the substrate. The epitaxial layer includes: a buffer layer, a drift layer, a superjunction layer and a P-well layer stacked in sequence. When the MOSFET is irradiated by radiation in the external environment or a high voltage is applied to the drain voltage, electric field concentration occurs between the superjunction layer and the drift layer, causing the impact ionization level at this position to increase and generate a local hot spot, resulting in a temperature increase. If the temperature at this location rises to the sublimation temperature or failure temperature of the material making the epitaxial layer, the MOSFET will be damaged and fail. Summary of the invention

[0003] The embodiments of the present invention provide a transistor, a manufacturing method thereof and an electronic device, which are used to avoid the generation of local hot spots between a super junction layer and a drift layer, thereby avoiding damage and failure of the transistor and improving the reliability of the transistor.

[0004] In a first aspect, an embodiment of the present invention provides a transistor, comprising: a first electrode layer, a buffer layer, a drift layer, and a super junction layer stacked in sequence; the super junction layer comprises a plurality of P columns and a plurality of N columns, the extension directions of the P columns and the N columns are parallel to the stacking direction, the P columns and the N columns are alternately arranged along a first direction, and the first direction is perpendicular to the stacking direction; The super junction layer further includes at least one of a P-type buffer structure and an N-type buffer structure, wherein the P-type buffer structure is disposed between the P column and the drift layer, and the N-type buffer structure is disposed between the N column and the drift layer.

[0005] In a second aspect, an embodiment of the present invention provides a method for manufacturing a transistor, comprising: sequentially forming a stacked buffer layer and a drift layer; Forming at least one of a P-type buffer structure and an N-type buffer structure on a surface of the drift layer facing away from the buffer layer; forming a superjunction layer; Among them, the super junction layer includes multiple P columns and multiple N columns, the extension directions of the P columns and the N columns are parallel to the stacking direction, the P columns and the N columns are alternately arranged along a first direction, and the first direction is perpendicular to the stacking direction; the P-type buffer structure is arranged between the P column and the drift layer, the P-type buffer structure includes at least one P-type buffer layer, and the N-type buffer structure is arranged between the N column and the drift layer.

[0006] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the above-mentioned transistor provided by an embodiment of the present invention.

[0007] The beneficial effects of the present invention are as follows: A transistor, a manufacturing method thereof, and an electronic device provided by an embodiment of the present invention, wherein the superjunction layer includes at least one of a P-type buffer structure and an N-type buffer structure, wherein the P-type buffer structure is disposed between the P column and the drift layer, and the N-type buffer structure is disposed between the N column and the drift layer. Thus, the P-type buffer structure can be equivalent to longitudinally extending the contact surface between the P column and the drift layer, and the N-type buffer structure can be equivalent to longitudinally extending the contact surface between the N column and the drift layer, so that the electric field is dispersed in the P-type buffer structure and the N-type buffer structure, thereby avoiding the generation of local hot spots between the superjunction layer and the drift layer, thereby avoiding damage and failure of the transistor and improving the reliability of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of the structure of a transistor provided in an embodiment of the present invention; Figure 2 A schematic diagram of the structure of another transistor provided in an embodiment of the present invention; Figure 3 A schematic diagram of the structure of another transistor provided in an embodiment of the present invention; Figure 4 A schematic diagram of the structure of another transistor provided in an embodiment of the present invention; Figure 5 A schematic diagram of the structure of another transistor provided in an embodiment of the present invention; Figure 6 A schematic diagram of the structure of an N-type doping portion provided in an embodiment of the present invention; Figure 7 A simulation diagram provided in an embodiment of the present invention; Figure 8 A flowchart of a method for manufacturing a transistor provided in an embodiment of the present invention; Fig. 9 The figure is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0009] Description of reference numerals: 10-first electrode layer, 20-buffer layer, 30-drift layer, 40-super junction layer, 41-P column, 42-N column, 43-P type buffer structure, 43a-first P type buffer layer, 43b-second P type buffer layer, 43c-third P type buffer layer, 43d-fourth P type buffer layer, 44-N type buffer structure, 44a-first N type buffer layer, 44b-second N type buffer layer, 44c-third N type buffer layer, 44d-the fourth N-type buffer layer, 45-N-type doped part, 50-P-well layer, 60-interlayer dielectric layer, 70-second electrode layer, 80-hole recombination structure, 81-N+ doped part, 82-N-doped part, 91-third electrode, 92-gate oxide layer, 93-P+ contact area, 94-N+ electrode contact area, 95-trench, 96-P+ shielding layer, 101-substrate, 102-P+ doped layer, m1-epitaxial layer. DETAILED DESCRIPTION

[0010] The following will be combined with the accompanying drawings to describe in detail a transistor, a method for manufacturing the transistor, and a specific implementation of an electronic device provided by an embodiment of the present invention. It should be noted that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0011] An embodiment of the present invention provides a transistor, such as Figure 1 and Figure 2 As shown, the transistor may include: a first electrode layer 10, a buffer layer 20, a drift layer 30 and a super junction layer 40 stacked in sequence; the super junction layer 40 includes a plurality of P columns 41 and a plurality of N columns 42, and the extension directions of the P columns 41 and the N columns 42 are parallel to the stacking direction, and the stacking direction may be Figure 1 and Figure 2 In the z direction shown in FIG. , the P columns 41 and the N columns 42 are alternately arranged along a first direction, and the first direction is perpendicular to the stacking direction. The first direction can be Figure 1 and Figure 2 The x direction shown in Figure 1 and Figure 2 the orientation of the paper shown; and Figure 1 and Figure 2 Only a partial number of P-pillars 41 and a partial number of N-pillars 42 are shown in the figure. The number of P-pillars 41 and N-pillars 42 can be set according to actual needs and is not specifically limited here.

[0012] The super junction layer 40 also includes at least one of a P-type buffer structure 43 and an N-type buffer structure 44. For example, the super junction layer 40 includes a P-type buffer structure 43 but does not include an N-type buffer structure 44, or the super junction layer 40 does not include a P-type buffer structure 43 but includes an N-type buffer structure 44, or the super junction layer 40 includes a P-type buffer structure 43 and an N-type buffer structure 44; the P-type buffer structure 43 is disposed between the P column 41 and the drift layer 30, and the N-type buffer structure 44 is disposed between the N column 42 and the drift layer 30.

[0013] In this way, even if the transistor is exposed to radiation in the external environment or a higher voltage is applied to the drain voltage, the P-type buffer structure 43 can be equivalent to longitudinally expanding the contact surface between the P column 41 and the drift layer 30, thereby avoiding electric field concentration between the P column 41 and the drift layer 30. The N-type buffer structure 44 can be equivalent to longitudinally expanding the contact surface between the N column 42 and the drift layer 30, thereby avoiding electric field concentration between the N column 42 and the drift layer 30. The electric field is dispersed in the P-type buffer structure 43 and the N-type buffer structure 44, thereby avoiding the generation of local hot spots between the super junction layer 40 and the drift layer 30, reducing the temperature at the interface between the super junction layer 40 and the drift layer 30, and further avoiding sublimation or failure of the material at the interface between the super junction layer 40 and the drift layer 30, thereby avoiding damage and failure of the transistor and improving the reliability of the transistor.

[0014] Optionally, the doping concentration of the P-type buffer structure 43 can be less than the doping concentration of the P column 41 and greater than the doping concentration of the drift layer 30, so as to reduce the doping concentration difference at the interface between the super junction layer 40 and the drift layer 30. Since the greater the doping concentration difference, the greater the peak temperature may be, the reduction in the doping concentration difference can reduce the peak temperature at the interface, thereby avoiding the generation of local hot spots.

[0015] Furthermore, the P-type buffer structure 43 includes at least one P-type buffer layer. For example, the P-type buffer layer may be provided with one, such as Figure 1 As shown in FIG. , the P-type buffer layer can be referred to as the first P-type buffer layer 43 a. Thus, the contact surface between the P column 41 and the drift layer 30 can be extended by one P-type buffer layer. Alternatively, a plurality of P-type buffer layers can be provided, such as Figure 3 The four P-type buffer layers shown in the figure are respectively a first P-type buffer layer 43a, a second P-type buffer layer 43b, a third P-type buffer layer 43c and a fourth P-type buffer layer 43d along the direction from the drift layer 30 to the super junction layer 40, that is, Figure 3In the z direction, the doping concentration of each P-type buffer layer gradually increases, which can further reduce the doping concentration difference at the interface between the super junction layer 40 and the drift layer 30, further reduce the peak temperature at the interface, and further eliminate local hot spots. Of course, when there are multiple P-type buffer layers, along the direction from the super junction layer 40 to the drift layer 30, the doping concentration of each P-type buffer layer can also be reduced in a step-by-step manner, as long as it can show a decreasing trend.

[0016] Alternatively, the doping concentration of the P-type buffer structure 43 can also be set to be greater than the doping concentration of the P column 41, or less than the doping concentration of the drift layer 30. In this way, the contact surface between the P column 41 and the drift layer 30 can also be longitudinally expanded. However, compared with the setting method of the doping concentration introduced above, the degree of reduction when lowering the peak temperature at the interface will be smaller, but the peak temperature at the interface can still be reduced to a certain extent.

[0017] Optionally, the doping concentration of the N-type buffer structure 44 is less than the doping concentration of the N-column 42 and greater than the doping concentration of the drift layer 30, which can reduce the doping concentration difference at the interface between the super junction layer 40 and the drift layer 30. Since the greater the doping concentration difference, the greater the peak temperature may be, the reduction in the doping concentration difference can reduce the peak temperature at the interface, thereby avoiding the generation of local hot spots.

[0018] Furthermore, the N-type buffer structure 44 includes at least one N-type buffer layer. For example, the N-type buffer layer may be provided with one, such as Figure 2 As shown in FIG. 4 , the N-type buffer layer may be referred to as the first N-type buffer layer 44 a. Thus, the contact surface between the N column 42 and the drift layer 30 may be extended by one N-type buffer layer. Alternatively, a plurality of N-type buffer layers may be provided, such as Figure 3 The four N-type buffer layers shown in the figure are respectively a first N-type buffer layer 44a, a second N-type buffer layer 44b, a third N-type buffer layer 44c and a fourth N-type buffer layer 44d along the direction from the drift layer 30 to the super junction layer 40, that is, Figure 3 In the z direction, the doping concentration of each N-type buffer layer gradually increases, which can further reduce the doping concentration difference at the interface between the super junction layer 40 and the drift layer 30, further reduce the peak temperature at the interface, and further eliminate local hot spots. Of course, when there are multiple N-type buffer layers, the doping concentration of each N-type buffer layer can also be reduced in a step-by-step manner along the direction from the super junction layer 40 to the drift layer 30, as long as it can show a decreasing trend.

[0019] Alternatively, the doping concentration of the N-type buffer structure 44 can also be set to be greater than the doping concentration of the N column 42, or less than the doping concentration of the drift layer 30. In this way, the contact surface between the N column 42 and the drift layer 30 can also be longitudinally expanded. However, compared with the setting method of the doping concentration introduced above, the degree of reduction in the peak temperature at the interface will be smaller, but the peak temperature at the interface can still be reduced to a certain extent.

[0020] Furthermore, when a plurality of P-type buffer layers and a plurality of N-type buffer layers are provided, the number of P-type buffer layers and the number of N-type buffer layers are the same and they are provided in one-to-one correspondence, and the doping concentration of the ith P-type buffer layer and the doping concentration of the ith N-type buffer layer satisfy a charge balance relationship. In this way, the P-type buffer layer and the N-type buffer layer can participate in the reverse withstand voltage of the transistor, thereby improving the withstand voltage performance of the transistor, especially when the thickness of the buffer layer 20 is large, the withstand voltage performance of the transistor is improved more significantly.

[0021] For example, Figure 3 As shown in Figure 3 Four P-type buffer layers and four N-type buffer layers are shown in FIG. 1 . To avoid making the drawings too complicated, Figure 3 Only the super junction layer 40 and the drift layer 30 are shown, the first P-type buffer layer 43a corresponds to the first N-type buffer layer 44a, and the first P-type buffer layer 43a and the first N-type buffer layer 44a satisfy a charge balance relationship; the second P-type buffer layer 43b corresponds to the second N-type buffer layer 44b, and the second P-type buffer layer 43b and the second N-type buffer layer 44b satisfy a charge balance relationship; the third P-type buffer layer 43c corresponds to the third N-type buffer layer 44c, and the third P-type buffer layer 43c and the third N-type buffer layer 44c satisfy a charge balance relationship; the fourth P-type buffer layer 43d corresponds to the fourth N-type buffer layer 44d, and the fourth P-type buffer layer 43d and the fourth N-type buffer layer 44d satisfy a charge balance relationship.

[0022] Moreover, the charge balance relationship can be expressed by Formula 1, which is: Pi×2W1=Ni×W2, Pi represents the doping concentration of the i-th P-type buffer layer, Ni represents the doping concentration of the i-th N-type buffer layer, and W1 represents the P column along Figure 3 The width in the x direction, W2 represents the width of N columns along Figure 3 that is, the first P-type buffer layer 43a and the first N-type buffer layer 44a, the second P-type buffer layer 43b and the second N-type buffer layer 44b, the third P-type buffer layer 43c and the third N-type buffer layer 44c, and the fourth P-type buffer layer 43d and the fourth N-type buffer layer 44d all satisfy Formula 1.

[0023] Of course, Formula 1 can also be: Pi×2W1≈Ni×W2, that is, the left side of the equation is not necessarily completely equal to the right side of the equation, and some gaps are allowed, but they are considered to be approximately equal, which also satisfies the charge balance relationship.

[0024] The thickness of each P-type buffer layer can be set to be the same or different, and can be set according to actual needs, which is not specifically limited here. The thickness of any P-type buffer layer can be set to be greater than 0 and not less than 10μm, and can be further set to 1μm-4μm, such as but not limited to: 1μm, 2μm, 3μm, 4μm and other values, which are not limited here. Similarly, the thickness of each N-type buffer layer can be set to be equal or different, and the thickness of any N-type buffer layer is the same as the thickness of the corresponding P-type buffer layer, which is not only convenient for manufacturing, but also conducive to achieving charge balance, thereby improving the voltage resistance performance of the transistor.

[0025] Optionally, the transistor may further include: an epitaxial layer m1, an interlayer dielectric layer 60, a second electrode layer 70, a gate oxide layer 92 and a third electrode 91, the epitaxial layer m1 includes a buffer layer 20, a drift layer 30, a super junction layer 40 and a P-well layer 50; wherein the manufacturing material of the epitaxial layer m1 may include: silicon carbide, silicon, gallium nitride and other semiconductor materials, which are not limited here.

[0026] The interlayer dielectric layer 60 and the second electrode layer 70 are both arranged on the side of the epitaxial layer m1 away from the first electrode layer 10. Figure 4 and Figure 5 shown.

[0027] The gate oxide layer 92 and the third electrode 91 are both disposed on the side of the epitaxial layer m1 away from the first electrode layer 10. Figure 4 As shown, the third electrode 91 is located between the gate oxide layer 92 and the interlayer dielectric layer 60, and the structure of the third electrode 91 is planar; or, a groove 95 is provided on the side of the epitaxial layer m1 away from the first electrode layer 10, as shown in FIG. Figure 5As shown, the third electrode 91 and the gate oxide layer 92 are both disposed in the trench 95, and the gate oxide layer 92 isolates the P-well layer 50 and the third electrode 91, and the super junction layer 40 and the third electrode 91, respectively, that is, the gate oxide layer 92 can isolate the epitaxial layer m1 and the third electrode 91, and the structure of the third electrode 91 is a channel type. At this time, the epitaxial layer m1 can also include a P+ shielding layer 96, and the P+ shielding layer 96 is disposed at the bottom of the trench 95 to protect the gate oxide layer 92 at the bottom of the trench and improve the reliability of the gate oxide layer 92. Among them, if the transistor is a metal-oxide semiconductor field effect transistor, the third electrode 91 can be a gate. In this case, a drain (or source) is provided in the first electrode layer 10, a source (or drain) is provided in the second electrode layer 70, and a substrate 101 can be provided between the first electrode layer 10 and the buffer layer 20; if the transistor is an insulated gate bipolar transistor, the third electrode 91 is a base. In this case, a collector (or emitter) is provided in the first electrode layer 10, an emitter (or collector) is provided in the second electrode layer 70, and a P+ doped layer 102 (or N+ doped layer) can be provided between the first electrode layer 10 and the buffer layer 20, and the P+ doped layer 102 (or N+ doped layer) can be part of the epitaxial layer m1.

[0028] The P-well layer 50 is located on the side of the superjunction layer 40 away from the drift layer 30. The P-well layer 50 is generally provided with a P+ contact region 93 and an N+ electrode contact region 94. Compared with the P+ contact region 93, the N+ electrode contact region 94 is closer to the third electrode 91. Figure 4 and Figure 5 As shown, the depths of the P+ contact region 93 and the N+ electrode contact region 94 are both less than the depth d1 of the P-well layer 50 .

[0029] At this time, if Figure 4 and Figure 5 As shown, a hole recombination structure 80 may also be provided in the P-well layer 50, and the orthographic projection of the P column 41 onto the P-well layer 50 overlaps with the hole recombination structure 80; it should be understood that the orthographic projection of the P column 41 onto the P-well layer 50 overlaps with the hole recombination structure 80, which can be understood as the hole recombination structure 80 being provided at the top of the P column 41 and corresponding to it. Since the impact ionization will cause the holes to diffuse vertically upward along the P column 41, the holes are likely to gather near the gate oxide layer 92, which will increase the internal electric field of the gate oxide layer 92 and easily cause the gate oxide layer 92 to fail. By providing the hole recombination structure 80, the recombination of the holes at this location with the redundant electrons in the hole recombination structure 80 can be enhanced, and at the same time, the extraction effect of the hole current vertically diffused upward along the P column 41 in the transistor to the second electrode layer 70 is accelerated, and the increase in the internal electric field of the gate oxide layer 92 is avoided, thereby improving the reliability of the transistor.

[0030] Among them, at least part of the hole recombination structure 80 is disposed in the P+ contact region 93, and along Figure 4In the x direction, the width of the hole recombination structure 80 does not exceed the width of the P+ contact area 93, so the hole recombination structure 80 will not contact the N+ electrode contact area 94, thus avoiding affecting the hole recombination structure 80's function of extracting holes.

[0031] Furthermore, the depth d2 of the cavity composite structure 80 may be set to: The depth d2 of the hole composite structure 80 is less than the depth d1 of the P-well layer 50, which is not shown in the figure. For example, the depth d2 of the hole composite structure 80 is less than the depth of the P+ contact area 93, or the depth d2 of the hole composite structure 80 is greater than the depth of the P+ contact area 93 and less than the depth d1 of the P-well layer 50. In this case, the hole composite structure 80 is not in direct contact with the P column 41, but this can still speed up the extraction of holes to a certain extent; Alternatively, the depth d2 of the hole recombination structure 80 is equal to the depth d1 of the P-well layer 50, as shown in FIG. Figure 4 As shown, at this time, the hole composite structure 80 is in direct contact with the P column 41, which can effectively speed up the extraction of holes; Alternatively, the depth d2 of the hole recombination structure 80 is greater than the depth d1 of the P-well layer 50 (not shown in the figure). In this case, the hole recombination structure 80 will penetrate the P-well layer 50 and penetrate into the interior of the P column 41, which can accelerate the extraction of holes faster and earlier.

[0032] Based on this, as the depth d2 of the hole composite structure 80 increases, the extraction effect on the holes will also increase accordingly, so the depth d2 of the hole composite structure 80 can be set according to actual needs and is not specifically limited here.

[0033] For example, Figure 4 As shown, the hole recombination structure 80 may include an N+ doped portion 81, and the depth d2 of the hole recombination structure 80 is the depth of the N+ doped portion 81. There are excess electrons in the N+ doped portion 81, and the holes can recombine with the excess electrons in the N+ doped portion 81, thereby achieving the effect of extracting holes.

[0034] Or, if Figure 5 As shown, the hole recombination structure 80 may include: an N+ doping portion 81 and an N- doping portion 82. The N- doping portion 82 is disposed on a side of the N+ doping portion 81 away from the P column 41. Figure 5In the z direction shown in the figure, an N+ doping portion 81 and an N- doping portion 82 are sequentially provided on the top of the P column 41 to form a heterojunction of N+ and N-, and a vertically upward built-in drift electric field. When the hole current generated by heavy ion irradiation reaches the hole recombination structure 80, a part of the holes recombine with the electrons in the N+ doping portion 81, and the remaining holes drift toward the second electrode layer 70 under the action of the built-in drift electric field, thereby enhancing the hole extraction effect in the P column 41 and avoiding affecting the gate oxide layer 92, thereby further improving the reliability of the transistor.

[0035] It should be understood that whether the structure of the third electrode 91 is a planar type or a channel type has no direct relationship with the specific implementation structure of the hole recombination structure 80. Figure 4 The hole recombination structure 80 is shown by taking the planar third electrode 91 as an example. Figure 5 In the figure, the hole recombination structure 80 is illustrated by taking the channel-type third electrode 91 as an example. Figure 1 and Figure 2 In the embodiment, whether the structure of the third electrode 91 is a planar type or a channel type has no direct relationship with the structure of the super junction layer 40. Figure 1 In the figure, the super junction layer 40 is shown by taking the planar third electrode 91 as an example. Figure 2 In the figure, only the super junction layer 40 is shown by taking the third electrode 91 of the channel type as an example.

[0036] Optionally, the transistor may further include an N-type doping portion 45, which is disposed in a partial region between the P column 41 and the P-well layer 50. Figure 4 and Figure 6 As shown, Figure 6 For along Figure 4 The black thick arrow in the figure is a top view of the surface (i.e., the top surface) of the P column 41. An N-type doping portion 45 is provided between each P column 41 and the P-well layer 50, and the projection of the N-type doping portion 45 on the top surface of the P column 41 only occupies a partial area of ​​the top surface of the P column 41. In this way, the N-type doping portion 45 only separates the P column 41 from the P-well layer 50 in a partial area. The N-type doping portion 45 and the P column 41 can form a PN junction, which can accelerate the extraction effect of the hole current vertically diffused upward along the P column 41 in the transistor to the second electrode layer 70, avoid affecting the gate oxide layer 92, and further improve the reliability of the transistor. In addition, the N-type doping portion 45 does not completely separate the P column 41 from the P-well layer 50, so the effect of the super junction layer 40 can still be guaranteed to be effective, thereby improving the voltage resistance performance of the transistor.

[0037] The thickness and size of the N-type doping portion 45 can be designed according to actual needs, and an N-type doping portion 45 can be provided between the P column 41 and the P-well layer 50. Figure 6As shown in (b) of FIG. 1 , a plurality of N-type doping portions 45 may be provided between the P column 41 and the P-well layer 50 , as shown in FIG. Figure 6 As shown in (a) in the figure, the arrangement of the plurality of N-type doped portions 45 can be designed according to actual needs, and are not specifically limited here.

[0038] Furthermore, it can be configured as follows: an N-type doping portion 45 is provided between each P column 41 and the P-well layer 50, or an N-type doping portion 45 is provided between some P columns 41 and the P-well layer 50. The specific design can be based on actual conditions to meet the needs of different scenarios and improve design flexibility.

[0039] Taking a transistor including four P-type buffer layers and four N-type buffer layers as an example, the transistor is simulated. During the simulation, the source-drain voltage Vds applied is 1500V, the thickness of the four P-type buffer layers is 1μm, and the doping concentrations of the four P-type buffer layers along the direction from the P column 41 to the drift layer 30 are: 5.2e16 / cm 3 , 4.4e16 / cm 3 、3.6e16 / cm 3 , 2.8e16 / cm 3 The thickness of the four N-type buffer layers is 1 μm. Along the direction from the N column 42 to the drift layer 30, the doping concentrations of the four N-type buffer layers are: 2.6e16 / cm 3 , 2.2e16 / cm 3 , 1.8e16 / cm 3 , 1.4e16 / cm 3 , the doping concentration of P column 41 is 6e16 / cm 3 , the doping concentration of N column 42 is 3e16 / cm 3 , the doping concentration of the drift layer 30 is 5e15 / cm 3 The simulation results are as follows: Figure 7 As shown, Figure 7 Curve 1 in the figure represents the peak temperature of the interface between the super junction layer 40 and the drift layer 30 when the P-type buffer layer and the N-type buffer layer are not set, and curve 2 represents the peak temperature of the interface between the super junction layer 40 and the drift layer 30 when the P-type buffer layer and the N-type buffer layer are set. By comparing curve 1 and curve 2, it can be found that the peak temperature is reduced when the P-type buffer layer and the N-type buffer layer are set, which indicates that the P-type buffer layer and the N-type buffer layer reduce the local temperature at the interface between the super junction layer 40 and the drift layer 30, thereby avoiding damage and failure of the transistor and improving the reliability of the transistor.

[0040] It should be understood that Figure 4 and Figure 5 As shown in the example, Figure 4 and Figure 5The structure of a transistor is shown. When multiple transistors are provided, Figure 4 or Figure 5 Just repeat the structure shown in .

[0041] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a transistor, and the manufacturing method can manufacture the above-mentioned transistor provided by the embodiment of the present invention, such as Figure 8 As shown, the production method may include: S801, sequentially forming a stacked buffer layer and a drift layer; S802, forming at least one of a P-type buffer structure and an N-type buffer structure on a surface of the drift layer facing away from the buffer layer; S803, forming a super junction layer; Among them, the super junction layer includes multiple P columns and multiple N columns, the extension directions of the P columns and the N columns are parallel to the stacking direction, the P columns and the N columns are arranged alternately along a first direction, and the first direction is perpendicular to the stacking direction; the P-type buffer structure is arranged between the P column and the drift layer, and the N-type buffer structure is arranged between the N column and the drift layer.

[0042] In this way, the P-type buffer structure can be equivalent to longitudinally expanding the contact surface between the P column and the drift layer, and the N-type buffer structure can be equivalent to longitudinally expanding the contact surface between the N column and the drift layer, so that the electric field is dispersed in the P-type buffer structure and the N-type buffer structure, avoiding the generation of local hot spots between the super junction layer and the drift layer, thereby avoiding damage and failure of the transistor and improving the reliability of the transistor.

[0043] Optionally, taking the formation of a P-type buffer structure and an N-type buffer structure as an example, the implementation process of the above S802 may include: Step 1: using epitaxial growth technology to form an epitaxial layer; Step 2: Using ion implantation technology to perform N-type doping on the epitaxial layer, so that the epitaxial layer is converted into an N-type doped layer; Step 3, continue to use ion implantation technology to perform P-type doping on some positions in the N-type doped layer, so that some positions form P-type doped regions, and the remaining positions are N-type doped regions. At this time, the P-type doped regions serve as P-type buffer layers, and the N-type doped regions serve as N-type buffer layers; Afterwards, step 1 to step 3 are continuously repeated to obtain a plurality of P-type buffer layers and a plurality of N-type buffer layers, thereby obtaining a P-type buffer structure and an N-type buffer structure.

[0044] In this way, through multiple epitaxy and ion implantation techniques, a P-type buffer structure and an N-type buffer structure can be obtained, which can reduce the ion implantation energy, reduce costs, reduce damage to other film layers, and improve the manufacturing yield of transistors.

[0045] Based on the same inventive concept, an embodiment of the present invention provides an electronic device, such as Fig. 9 As shown, the electronic device may include the above-mentioned transistor provided in the embodiment of the present invention. Among them, the electronic device may be any type of device including the transistor, such as but not limited to a chip, etc. The electronic device can be applied to high-voltage inverters of high-speed railways, power grids (such as distribution networks, microgrids, etc.), high-voltage photovoltaics and other scenarios to meet the withstand voltage requirements. Of course, in addition to transistors, electronic devices may also include other structures, such as but not limited to other passive devices or active devices such as capacitors, resistors, inductors, etc., which can be specifically set according to actual needs and are not limited here.

[0046] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A transistor, characterized in that: include: A first electrode layer, a buffer layer, a drift layer and a super junction layer are stacked in sequence; the super junction layer comprises a plurality of P columns and a plurality of N columns, the extension directions of the P columns and the N columns are parallel to the stacking direction, the P columns and the N columns are alternately arranged along a first direction, and the first direction is perpendicular to the stacking direction; The super junction layer further includes at least one of a P-type buffer structure and an N-type buffer structure, wherein the P-type buffer structure is disposed between the P column and the drift layer, and the N-type buffer structure is disposed between the N column and the drift layer.

2. The transistor according to claim 1, characterized in that The doping concentration of the P-type buffer structure is less than the doping concentration of the P column and greater than the doping concentration of the drift layer.

3. The transistor according to claim 2, characterized in that The P-type buffer structure includes at least one P-type buffer layer; When a plurality of P-type buffer layers are provided, the doping concentration of each P-type buffer layer gradually increases along a direction from the drift layer to the super junction layer.

4. The transistor according to claim 1, wherein The doping concentration of the N-type buffer structure is less than the doping concentration of the N column and greater than the doping concentration of the drift layer.

5. The transistor according to claim 4, characterized in that The N-type buffer structure includes at least one N-type buffer layer; When a plurality of N-type buffer layers are provided, the doping concentration of each N-type buffer layer gradually increases along a direction from the drift layer to the super junction layer.

6. The transistor according to claim 1, wherein The super junction layer includes a P-type buffer structure and an N-type buffer structure. The P-type buffer structure includes a plurality of P-type buffer layers, and the N-type buffer structure includes a plurality of N-type buffer layers. The number of layers of the P-type buffer layer is the same as that of the N-type buffer layer.

7. The transistor according to claim 1, wherein The transistor further includes: a P-well layer located on a side of the superjunction layer away from the drift layer, a hole recombination structure is provided in the P-well layer, and an orthographic projection of the P column to the P-well layer overlaps with the hole recombination structure.

8. The transistor according to claim 7, characterized in that The depth of the hole recombination structure is not less than the depth of the P-well layer.

9. The transistor according to claim 7, characterized in that The hole recombination structure includes an N+ doped portion.

10. The transistor according to claim 9, characterized in that The hole recombination structure further includes an N-doped portion disposed on a side of the N+ doped portion away from the P column.

11. The transistor according to any one of claims 1 to 10, characterized in that: The transistor further includes: a P-well layer and an N-type doping portion, wherein the P-well layer is disposed on a side of the superjunction layer away from the drift layer, and the N-type doping portion is disposed in a partial region between the P column and the P-well layer.

12. A method for manufacturing a transistor, characterized in that: include: sequentially forming a stacked buffer layer and a drift layer; forming at least one of a P-type buffer structure and an N-type buffer structure on a surface of the drift layer facing away from the buffer layer; forming a superjunction layer; Among them, the super junction layer includes multiple P columns and multiple N columns, the extension directions of the P columns and the N columns are parallel to the stacking direction, the P columns and the N columns are alternately arranged along a first direction, and the first direction is perpendicular to the stacking direction; the P-type buffer structure is arranged between the P column and the drift layer, and the N-type buffer structure is arranged between the N column and the drift layer.

13. An electronic device, characterized in that: Comprising a transistor as claimed in any one of claims 1 to 11.

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