Preparation method of semiconductor structure, semiconductor structure, device and equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. The preparation method comprises the following steps: forming a first pole structure on a first region of a substrate, and forming a first transistor in the flip stacked transistors on a second region of the substrate; reversing the wafer and removing the substrate; a second pole structure is formed on the first region, a second transistor in the flip-chip stacked transistor is formed on the second region, and the ion doping type of the second pole structure is different from that of the first pole structure; wherein under the condition that the first pole structure or the second pole structure is the base structure, an emitter structure is formed in the third region of the base structure through ion doping, and the ion doping type of the emitter structure is different from that of the base structure. By preparing the punch-through bipolar junction transistor compatible with the flip-chip transistor process, the process steps are saved, and the flexibility of the circuit design of the semiconductor device is enhanced.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further improve the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size. Under the preparation process of flip-chip stacked transistors, a method for preparing bipolar junction transistors is urgently needed. Summary of the invention

[0003] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus, which not only saves process steps but also enhances the flexibility of circuit design in semiconductor devices by preparing a through-bipolar junction transistor compatible with a flip-chip stacked transistor process.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising: forming a first pole structure on a first region of a substrate, and forming a first transistor in a flip-chip stacked transistor on a second region of the substrate, the first region and the second region being different regions of the substrate in a first direction; flipping the first pole structure and the first transistor, and removing the substrate; forming a second pole structure on the first region, and forming a second transistor in the flip-chip stacked transistor on the second region, the ion doping type of the second pole structure being different from the ion doping type of the first pole structure; wherein the first pole structure is a base structure and the second pole structure is a collector structure, or the first pole structure is a collector structure and the second pole structure is a base structure; forming an emitter structure by ion doping in a third region of the base structure, the ion doping type of the emitter structure being different from the ion doping type of the base structure.

[0005] In one possible implementation, a first pole structure is formed on a first region of a substrate, and a first transistor in a flip-chip stacked transistor is formed on a second region of the substrate, including: forming a first mask on the second region; forming a first pole on the first region by ion doping; removing the first mask; and forming a first pole contact metal on the first pole while forming the first transistor based on the second region, the first pole and the first pole contact metal constituting a first pole structure.

[0006] In one possible implementation, a second electrode structure is formed on a first region, and a second transistor in a flip-chip stacked transistor is formed on a second region, including: forming a second mask on the second region; forming a second electrode on the first region by ion doping, wherein the ion doping type of the second electrode is different from the ion doping type of the first electrode; removing the second mask; and forming a second electrode contact metal on the second electrode when forming the second transistor based on the second region, wherein the second electrode and the second electrode contact metal constitute a second electrode structure.

[0007] In one possible embodiment, in the case where the first electrode is the collector, in the case where the first transistor in the flip-chip stacked transistor is formed based on the second region, a first electrode contact metal is formed on the first electrode, including: forming a third mask on the first region, and etching the substrate in the second region to form an active structure, the active structure including a first active structure away from the substrate and a second active structure close to the substrate; forming a first semiconductor structure based on the first active structure; removing the third mask; forming a first source-drain structure in the second region by ion implantation, and forming a collector contact structure on the collector of the first region, the first source-drain structure being formed after ion implantation of the first semiconductor structure, and the ion concentration of the collector contact structure being higher than the ion concentration of the collector structure; while sequentially forming the first gate structure and the first source-drain metal in the first transistor on the second region, forming the collector contact metal on the collector contact structure of the first region.

[0008] In a possible embodiment, while the first gate structure and the first source-drain metal in the first transistor are sequentially formed on the second region, the collector contact metal is formed on the collector contact structure of the first region, including: forming a first dielectric layer on the first source-drain structure and the collector contact structure; forming a first gate structure based on the first active structure; etching the first dielectric layer to form the first source-drain metal on the first source-drain structure, and forming the collector contact metal on the collector contact structure.

[0009] In one possible embodiment, in the case where the second electrode is the base, in the case where a second transistor is formed based on the second region, a second electrode contact metal is formed on the second electrode, including: forming a second source-drain structure based on the second active structure on the second region; forming a fourth mask on the first region and the second region, the fourth mask on the first region exposing the region where the emitter is located; forming an emitter in the first region by ion implantation; removing the fourth mask; and while sequentially forming a second gate structure and a second source-drain metal in the second transistor on the second region, forming a base contact metal on the base of the first region and an emitter contact metal on the emitter.

[0010] In a possible implementation, while a second gate structure and a second source-drain metal in a second transistor are sequentially formed on the second region, a base contact metal is formed on the base of the first region and an emitter contact metal is formed on the emitter, including: forming a second dielectric layer on the second source-drain structure, the base and the emitter; forming a second gate structure based on the second active structure; etching the second dielectric layer to form a second source-drain metal on the second source-drain structure, and forming a base contact metal on the base and an emitter contact metal on the emitter.

[0011] In a possible implementation, when the first electrode structure is a base structure, the first electrode is formed on the first region by ion doping, including: forming a collector on the first region by ion doping; forming a base on the collector by ion doping, and the ion doping type of the base is different from the ion doping type of the collector.

[0012] In one possible embodiment, in the case where the first electrode is the base, in the case where the first transistor in the flip-chip stacked transistor is formed based on the second region, a first electrode contact metal is formed on the first electrode, including: forming a fifth mask on the first region, and etching the substrate in the second region to form an active structure, the active structure including a first active structure away from the substrate and a second active structure close to the substrate; based on the first active structure, forming a first source-drain structure, the ion doping type in the first source-drain structure is the same as the ion doping type of the base structure; forming a fifth mask on the second region, and etching the fifth mask on the first region to expose the region where the emitter is located; forming an emitter structure in the first region by ion implantation; removing the fifth mask; while sequentially forming the first gate structure and the first source-drain metal in the first transistor on the first region, forming a base contact metal on the base of the first region and an emitter contact metal on the emitter.

[0013] In one possible embodiment, in the case where the second electrode is the collector, in the case where a second transistor is formed based on the second region, a second electrode contact metal is formed on the second electrode, including: forming a sixth mask on the first region, and forming a second semiconductor structure based on the second active structure on the second region; removing the sixth mask; forming a second source-drain structure in the second region by ion implantation, and forming a collector contact structure on the collector of the first region, the second source-drain structure being formed after ion implantation of the second semiconductor structure, and the ion concentration of the collector contact structure being higher than the ion concentration of the collector; while sequentially forming a second gate structure and a second source-drain metal in the second transistor on the second region, forming a collector contact metal on the collector contact structure of the first region.

[0014] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is manufactured using the preparation method of the first aspect and any one of its embodiments, and includes: flip-flop transistors and bipolar junction transistors located in different regions, and the flip-flop transistors and the bipolar junction transistors are formed simultaneously; wherein the flip-flop transistor includes a first transistor and a second transistor arranged back to back, and the bipolar junction transistor includes a collector structure, a base structure and an emitter structure, and the collector structure is arranged back to back with the base structure and the emitter structure.

[0015] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a semiconductor structure as described in the second aspect above.

[0016] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0017] The technical solution provided by this application may have the following beneficial effects:

[0018] In the embodiment of the present application, a first electrode structure is formed on a first region of a substrate, and a first transistor in a flip-stack transistor is formed on a second region of the substrate; the substrate is flipped and removed; a second electrode structure having an ion doping type different from that of the first electrode structure is formed on the first region, and a second transistor in the flip-stack transistor is formed on the second region. The present application saves process steps and enhances the flexibility of semiconductor device circuit design by preparing a through bipolar junction transistor compatible with the flip-stack transistor process.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0021] Figure 1 It is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0022] Figure 2 This is a first schematic top view of a semiconductor structure in an embodiment of the present application;

[0023] Figures 3 to 14 A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0024] Fig.15 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application;

[0025] Fig.16 A second schematic top view of the semiconductor structure in an embodiment of the present application;

[0026] Fig.17 This is a schematic diagram of a second structure of a semiconductor structure in an embodiment of the present application;

[0027] Fig.18 This is a schematic diagram of a third structure of a semiconductor structure in an embodiment of the present application;

[0028] Fig.19 This is a schematic diagram of the fourth structure of the semiconductor structure in the embodiment of the present application.

[0029] The above pictures:

[0030] 10. Flip-chip stack transistor; 11. First transistor (front transistor); 111. First fin structure; 112. First source-drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 115. First source-drain metal; 12. Second transistor (back transistor); 121. First fin structure; 122. Second source-drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 125. Second source-drain metal; 20. BJT; 21. Substrate; 22. First photoresist layer; 23. Collector region; 24. Second photoresist layer; 25. Fin structure; 26. Isolation 27. first pseudo-gate structure; 28. first sidewall; 29. ​​first semiconductor structure; 30. collector contact region; 31. first dielectric layer; 32. collector contact metal; 33. first insulating layer; 34. first oxide layer; 35. second oxide layer; 36. second insulating layer; 37. carrier wafer; 38. base region; 39. third photoresist layer; 40. second pseudo-gate structure; 41. second sidewall; 42. fourth photoresist layer; 43. emitter region; 44. second dielectric layer; 45. base contact metal; 46. emitter contact metal; 47. third insulating layer; 48. third oxide layer. DETAILED DESCRIPTION

[0031] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0032] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0033] In one embodiment, there are two schemes for the manufacturing process of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0034] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using substrate bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0035] The second solution is based on substrate bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the substrate on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to substrate bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonding substrate; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0036] However, some solutions for preparing flip-chip stack transistors do not involve a solution for manufacturing a bipolar junction transistor (BJT) under the flip-chip stack transistor process.

[0037] Therefore, an embodiment of the present application provides a method for preparing a semiconductor structure, which saves process steps and enhances the flexibility of semiconductor device circuit design by preparing a through-bipolar junction transistor that is compatible with a flip-chip stack transistor process.

[0038] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0039] In some embodiments, the semiconductor structure may include a flip-stacked transistor and a bipolar junction transistor located in different regions, and the flip-stacked transistor and the bipolar junction transistor are formed simultaneously; wherein the flip-stacked transistor includes a first transistor and a second transistor arranged back to back, and the bipolar junction transistor includes a collector structure, a base structure and an emitter structure, and the collector structure is arranged back to back with the base structure and the emitter structure.

[0040] In an embodiment of the present application, the first transistor and the second transistor in the flip-chip stacked transistor are transistors of the same type, and the type of the transistor may include but is not limited to: fin field effect transistor (FinFET), gate-all-around field effect transistor (GAAFET), planar transistor, vertical field effect transistor (VFET), etc.

[0041] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application. Figure 1 As shown, the method for preparing a semiconductor structure includes the following steps.

[0042] Step S101: forming a first electrode structure on a first region of a substrate, and forming a first transistor in a flip-chip stack transistor on a second region of the substrate.

[0043] In some embodiments, the first region and the second region are different regions of the substrate in the first direction.

[0044] In some embodiments, the implementation process of step S101 may be: forming a first mask on the second region; forming a first electrode on the first region by ion doping; removing the first mask; and forming a first electrode contact metal on the first electrode while forming a first transistor based on the second region, and the first electrode and the first electrode contact metal constitute a first electrode structure.

[0045] In some embodiments, the collector structure in the punch-through BJT may be located on the front side, and the base structure and the emitter structure may be located on the back side, or the base structure and the emitter structure are located on the front side, and the collector structure is located on the back side. In this application, the scheme in which the collector structure is located on the front side, and the base structure and the emitter structure are located on the back side is referred to as the first scheme, and the scheme in which the base structure and the emitter structure are located on the front side, and the collector structure is located on the back side is referred to as the second scheme.

[0046] In some embodiments, when the first electrode structure on the front side is a collector structure (corresponding to the first solution), a substrate is first provided, the substrate includes a first region and a second region, the first region is used to prepare a BJT, and the second region is used to prepare a flip-chip stacked transistor; then a first mask is formed on the second region of the substrate; and a collector is formed on the first region of the substrate by ion doping. The collector may also be referred to as a collector region.

[0047] In some embodiments, the substrate may be any semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, or a silicon carbide (SiC) substrate.

[0048] In some embodiments, the ion doping type may be N-type ions or P-type ions. The P-type ions may be any one of the following: boron (B), gallium (Ga), aluminum (Al). The N-type ions may be any one of the following: phosphorus (P), arsenic (As), antimony (Sb).

[0049] It can be understood that the BJT device region (i.e., the first region) and the flip-chip stack transistor device region (i.e., the second region) are defined by photolithography, a first mask is formed on the second region, and then the collector region is formed on the first region by ion doping. Since the first mask is provided as a protective layer on the second region during ion doping, the substrate on the second region is not ion doped.

[0050] In some embodiments, the collector region may be formed by low-doped deep well implantation, so that the ion doping concentration of the collector region is low and the thickness of the collector region is high. For example, the ion doping type of the collector region may be P-type ions.

[0051] In some embodiments, when the first electrode structure is a base structure (corresponding to the second solution), a substrate is first provided, the substrate includes a first region and a second region, the first region is used to prepare a BJT, and the second region is used to prepare a flip-chip stacked transistor; a first mask is formed on the second region of the substrate; a collector is formed on the first region of the substrate by ion doping; a base is formed on the collector by ion doping, and the ion doping type of the base is different from the ion doping type of the collector. The collector may also be referred to as a collector region, and the base may also be referred to as a base region.

[0052] It can be understood that the collector region is first formed on the first region, and then the base region of the BJT is defined by photolithography, and ion doping is performed to form the base region, wherein the thickness of the base region is smaller than the thickness of the collector region.

[0053] In some embodiments, when the ion doping type of the collector region is P-type ions, the ion doping type of the base region is N-type ions.

[0054] In some embodiments, the base region may be formed by shallow well implantation, so that the thickness of the base region formed is relatively low.

[0055] It can be understood that the collector region or base region of the BJT is formed using the first mask as a protective layer, and then the first mask can be removed to simultaneously form the front transistor (ie, the first transistor) of the flip-chip stacked transistor and the front structure of the BJT.

[0056] In some embodiments, when a first transistor in a flip-chip stack transistor is formed based on the second region, a first electrode contact metal is formed on the first electrode structure.

[0057] In some embodiments, when the first electrode on the front side is the collector (corresponding to the first solution), when the first transistor in the flip-chip stacked transistor is formed based on the second region, the implementation process of forming the first electrode contact metal on the first electrode structure can be: forming a third mask on the first region, and etching the substrate in the second region to form an active structure, the active structure includes a first active structure away from the substrate and a second active structure close to the substrate; forming a first semiconductor structure based on the first active structure; removing the third mask; forming a first source-drain structure in the second region by ion implantation, and forming a collector contact structure in the first region, the first source-drain structure is formed after the first semiconductor structure is implanted, and the ion concentration of the collector contact structure is higher than the ion concentration of the collector; while sequentially forming the first gate structure and the first source-drain metal in the first transistor on the second region, forming the collector contact metal on the collector contact structure in the first region. The collector contact structure may also be referred to as a collector contact region.

[0058] It can be understood that a third mask is first formed on the first region, and then the substrate in the second region is etched to form a number of active structures standing upright on the substrate, and a first semiconductor structure is formed based on the first active structure in the active structure. Then the third mask is removed, and the first semiconductor structure in the second region is formed into a first source-drain structure by ion implantation, and a part of the collector region in the first region is formed into a collector contact region. Afterwards, the front transistor in the flip-chip stacked transistor and the collector contact metal on the front in the BJT can be formed respectively. By way of example, the etching process can be at least one of dry etching, wet etching, reactive ion etching, and the like.

[0059] When the flip-stack transistor is a fin field effect transistor, the active structure is a fin structure. When the flip-stack transistor is a full-surround gate transistor, the active structure is a nanosheet. When the flip-stack transistor is a planar transistor, the active structure is a block planar structure.

[0060] In some embodiments, after forming the active structure, an insulating material may be deposited on the substrate to form an isolation structure encapsulating the second active structure.

[0061] It can be understood that after the active structure is formed, an insulating material may be deposited on the surface of the substrate and the active structure and thinned, so that the formed isolation structure wraps the second active structure and exposes the first active structure.

[0062] In one example, the isolation structure may be formed by shallow trench isolation (STI). For example, the insulating material forming the isolation structure may be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO). The thinning process may be a process such as chemical-mechanical planarization (CMP).

[0063] In some embodiments, before forming the first semiconductor structure based on the first active structure, a semiconductor material may be deposited in the gate region of the first transistor to form a first dummy gate structure surrounding the first active structure; and a first sidewall spacer may be formed on both sides of the first dummy gate structure.

[0064] For example, the semiconductor material may be polycrystalline silicon (poly Si), amorphous silicon, or the like.

[0065] It is understandable that after the isolation structure is formed, the gate region can be opened by photolithography, and semiconductor materials such as polysilicon can be deposited in the gate region as a pseudo-gate structure (i.e., a first pseudo-gate structure) of the front transistor. Then, a dielectric material is deposited on both sides of the first pseudo-gate structure to form a first sidewall. Among them, the first spacer is used to isolate the first source and drain structure from the first gate structure. The structure of the first spacer can be set according to actual needs, and the embodiment of the present application is not limited to this. For example, the first spacer may have a single-layer structure, and the whole is made of the same material, such as porous carbon silicon oxyhydride (SiCOH).

[0066] In some embodiments, after forming the first spacer, a first semiconductor structure may be formed on the first dummy gate structure and the first active structure on both sides of the first spacer, that is, a first source-drain structure without ion implantation is formed.

[0067] In one example, the first active structure of the first transistor in the source and drain region is etched to form source and drain grooves, and then strained materials such as silicon germanium or silicon carbide are formed by selective epitaxial growth to fill the source and drain grooves to form the first semiconductor structure.

[0068] After forming the first semiconductor structure, the third mask can be removed, and the collector contact region of the BJT can be defined by photolithography, and then ion implantation is performed on both regions to form a collector contact region on the first region and a first source-drain structure on the second region. The thickness of the collector contact region is less than the thickness of the collector region, and the ion concentration of the collector contact structure is higher than the ion concentration of the collector region.

[0069] It should be noted that the type of ions implanted here is the same as the type of ions doped in the collector region in the above step S101. For example, when the type of ions doped in the collector region is P type, the type of ions implanted here is also P type.

[0070] It can be understood that after removing the third mask, the first source-drain structure can be formed by ion implanting the strained material of the first semiconductor structure in the second region, and the collector contact area is defined by photolithography and then high-concentration ion implantation is performed in the area to form a collector contact structure.

[0071] After forming the first source-drain structure and the collector contact structure, the first gate structure and the first source-drain metal in the first transistor may be sequentially formed on the second region while forming the collector contact metal on the collector contact structure in the first region.

[0072] In some embodiments, while the first gate structure and the first source-drain metal in the first transistor are sequentially formed on the second region, the collector contact metal is formed on the collector contact structure in the first region by: forming a first dielectric layer on the first source-drain structure and the collector contact structure; forming a first gate structure based on the first active structure; etching the first dielectric layer to form the first source-drain metal on the first source-drain structure, and forming the collector contact metal on the collector contact structure.

[0073] It can be understood that after the collector contact structure and the first source-drain structure are formed simultaneously, an insulating material (such as SiO2) can be deposited on the collector contact structure and the first source-drain structure, and a flattening process can be performed to form a first interlayer dielectric layer (also referred to as a first dielectric layer), and the first interlayer dielectric layer can cover the collector contact structure and the first source-drain structure. After that, the first dummy gate structure in the second region can be removed to form a first gate structure. The first dielectric layer can then be etched to expose the collector contact structure in the first region and the first source-drain structure in the second region, and a metal material can be deposited on the exposed collector contact structure and the first source-drain structure to form a collector contact metal in the first region and a first source-drain metal in the second region. Among them, the collector contact metal occupies a small area on the collector contact structure.

[0074] It should be noted that, since there is no active structure and dummy gate structure in the first region, there is no first gate structure in the first region.

[0075] In some embodiments, the first dummy gate structure formed above is removed by an etching process to obtain a first gate groove, an insulating material is deposited at the first gate groove to form a first gate dielectric layer, and a metal material is deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute a first gate structure.

[0076] For example, the first gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. For example, the first gate electrode layer can be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide).

[0077] In addition, in some embodiments, after forming the first gate structure, an insulating material may be deposited on the first gate structure in the second region and the collector contact structure in the first region to form a first insulating layer, and then a first oxide layer may be formed on the first insulating layer to protect the collector contact structure in the first region and the first gate structure in the second region. When the first source-drain metal and the collector contact metal are formed by photolithography, if the photolithography drilling is offset, it will also be punched on the insulating layer, preventing the gate metal from directly contacting the source-drain metal, thereby reducing the requirements for photolithography.

[0078] In some embodiments, after forming the collector contact metal in the first region and forming the first source and drain metal in the second region, a first metal interconnect layer can be formed through back-end processes (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.). In this way, the front structure of the BJT in the first region and the front transistor of the flip-chip stacked transistor in the second region are prepared.

[0079] The above is the preparation process of forming the collector structure on the front side in the first solution. The following is the preparation process of forming the base structure and the emitter structure on the front side in the second solution.

[0080] In some embodiments, when the first electrode on the front side is the base (corresponding to the second solution), when the first transistor in the flip-chip stacked transistor is formed based on the second region, the implementation process of forming the first electrode contact metal on the first electrode structure can be: forming a fifth mask on the first region, and etching the substrate in the second region to form an active structure, the active structure includes a first active structure away from the substrate and a second active structure close to the substrate; forming a first source-drain structure based on the first active structure, the ion doping type in the first source-drain structure is the same as the ion doping type of the base structure; forming a fifth mask on the second region, and etching the fifth mask on the first region to expose the region where the emitter is located; forming an emitter in the first region by ion implantation; removing the fifth mask; while sequentially forming the first gate structure and the first source-drain metal in the first transistor on the first region, forming a base contact metal on the base of the first region and an emitter contact metal on the emitter. The emitter may also be referred to as an emitter region.

[0081] It can be understood that first, a fifth mask is formed on the first region, and then the substrate in the second region is etched to form a number of active structures standing upright on the substrate, and based on the first active structure in the active structure, a first source-drain structure having the same ion doping type as the ion doping type of the base region is formed. After that, the emitter region can be defined by photolithography in the first region, and then the emitter region can be formed by ion doping in the third region of the base region, and finally, the front transistor in the flip-chip stacked transistor and the front base contact metal and emitter contact metal in the BJT are formed respectively. Among them, the third region is a part of the base region.

[0082] In some embodiments, after forming the active structure, an insulating material may be deposited on the substrate to form an isolation structure encapsulating the second active structure.

[0083] In some embodiments, before forming the first source-drain structure based on the first active structure, a semiconductor material may be deposited in the gate region of the first transistor to form a first dummy gate structure surrounding the first active structure; and a first sidewall may be formed on both sides of the first dummy gate structure.

[0084] It can be understood that in the second solution, after forming a base region with an ion doping type different from that of the collector region in the above step S101, a first source-drain structure with the same ion doping type as that of the base region can be formed here. For example, when the ion doping type of the collector region is P-type and the ion doping type of the base region is N-type, a first source-drain structure with an ion doping type of N-type can be formed here.

[0085] After forming the first source-drain structure, a fifth mask may be formed on the second region, and the emitter region in the first region may be defined by photolithography. Therefore, the fifth mask in the first region may be etched to expose the region where the emitter region is located, and then the emitter region is formed in the region exposed in the first region by ion implantation. After forming the emitter region, the fifth mask may be removed. The ion implantation (also referred to as doping) concentration of the emitter region is higher than the ion doping concentration of the collector region, and the ion doping type of the emitter region is the same as the ion doping type of the collector region and different from the ion doping type of the base region. For example, when the ion doping type of the collector region is P-type and the ion doping type of the base region is N-type, the ion doping type of the emitter region is P-type.

[0086] In some embodiments, the emitter region may be formed by highly doped shallow well implantation, so that the ion doping concentration of the emitter region is high and the thickness of the emitter region is low.

[0087] After forming the base and the emitter, the first gate structure and the first source-drain metal in the first transistor can be sequentially formed on the second region, while a base contact metal is formed on the base of the first region and an emitter contact metal is formed on the emitter.

[0088] In some embodiments, while the first gate structure and the first source-drain metal in the first transistor are sequentially formed on the second region, the implementation process of forming a base contact metal on the base of the first region and an emitter contact metal on the emitter can be: forming a first dielectric layer on the first source-drain structure, the base and the collector; forming a first gate structure based on the first active structure; etching the first dielectric layer to form a first source-drain metal on the first source-drain, and forming a base contact metal on the base and an emitter contact metal on the emitter.

[0089] It can be understood that after forming the base and the emitter, an insulating material (such as SiO2) can be deposited on the base, the emitter and the first source-drain structure, and a flattening process can be performed to form a first interlayer dielectric layer (also referred to as a first dielectric layer), and the first interlayer dielectric layer can cover the base, the emitter and the first source-drain structure. After that, the first pseudo-gate structure in the second region can be removed to form a first gate structure. Then, the first dielectric layer can be etched to expose the base, the emitter in the first region and the first source-drain structure in the second region, and a metal material can be deposited on the exposed base, the emitter and the first source-drain structure to form a base contact metal in the first region, an emitter contact metal and a first source-drain metal in the second region.

[0090] In some embodiments, after forming the base contact metal and the emitter contact metal in the first region and forming the first source and drain metal in the second region, a first metal interconnect layer can be formed through a back-end process (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.). In this way, the front structure of the BJT in the first region and the front transistor of the flip-chip stacked transistor in the second region are prepared.

[0091] Step S102: flipping the first electrode structure and the first transistor, and removing the substrate.

[0092] It can be understood that after the front structure of the BJT in the first region and the front transistor of the flip-chip stacked transistor in the second region are formed, the front structure of the BJT and the front transistor can be flipped over, and the back structure can be prepared on the front structure of the BJT, and the back transistor can be prepared on the front transistor.

[0093] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the first metal interconnect layer to form a second insulating layer, and the second insulating layer may be bonded to a carrier wafer, and then flipped over and the substrate removed.

[0094] In some embodiments, after removing the substrate, the isolation structure on the second region may be thinned to expose the second active structure, so that a back-side transistor can be subsequently prepared based on the exposed second active structure.

[0095] Step S103: forming a second electrode structure on the first region, and forming a second transistor in the flip-chip stack transistor on the second region.

[0096] In some embodiments, the ion doping type of the second electrode structure is different from the ion doping type of the first electrode structure.

[0097] In some embodiments, the implementation process of step S103 may be: forming a second mask on the second region; forming a second electrode on the first region by ion doping, the ion doping type of the second electrode being different from the ion doping type of the first electrode; removing the second mask; and forming a second electrode contact metal on the second electrode when forming a second transistor based on the second region, the second electrode and the second electrode contact metal constitute a second electrode structure.

[0098] In some embodiments, when the second electrode structure on the back side is a base structure (corresponding to the first solution), a second mask may be formed on the second region, a base region of the BJT may be defined by photolithography, and a base may be formed by ion doping, wherein the ion doping type of the base is different from the ion doping type of the collector.

[0099] In some embodiments, when the second electrode on the back side is a collector (corresponding to the second solution), since the collector has been formed in the first step of the second solution in the aforementioned step S101, no operation is required here.

[0100] It can be understood that in the first solution, the base region of the BJT is formed using the second mask as a protective layer, and then the second mask can be removed to simultaneously form the back transistor of the flip-chip stacked transistor and the back structure of the BJT.

[0101] In some embodiments, when the second transistor in the flip-chip stack transistor is formed based on the second region, a second electrode contact metal is formed on the second electrode structure.

[0102] In some embodiments, when the second electrode on the back side is the base (corresponding to the first solution), when the second transistor in the flip-chip stacked transistor is formed based on the second region, the implementation process of forming the second electrode contact metal on the second electrode structure can be: forming a fourth mask on the first region, and forming a second source-drain structure based on the second active structure on the second region; forming a fourth mask on the second region, the fourth mask on the first region exposes the region where the emitter is located; forming an emitter in the first region by ion implantation; removing the fourth mask; and forming the second gate structure and the second source-drain metal in the second transistor in sequence on the second region, while forming a base contact metal on the base of the first region and an emitter contact metal on the emitter.

[0103] It can be understood that the fourth mask is first formed on the first region, and then based on the second active structure in the active structure of the second region, a second source-drain structure having the same ion doping type as the ion doping type of the base region is formed. After that, the emitter region can be defined by photolithography in the first region, and then the emitter region is formed by ion doping in the third region of the base region, and finally the back transistor (i.e., the second transistor) in the flip-chip stacked transistor and the base contact metal and the emitter contact metal on the back of the BJT are formed respectively.

[0104] In some embodiments, before forming the second source-drain structure based on the second active structure on the second region, a mask may be formed on the first region, and then a semiconductor material may be deposited in the gate region of the second transistor in the second region to form a second dummy gate structure surrounding the second active structure; and a second sidewall may be formed on both sides of the second dummy gate structure. After forming the second sidewall, a second source-drain structure may be formed on the second active structure on both sides of the second dummy gate structure and the second sidewall. The mask may then be removed.

[0105] After forming the second source-drain structure, a fourth mask may be formed on the second region, and the emitter region in the second region may be defined by photolithography, so that the fourth mask in the first region may be etched to expose the emitter region, and then an emitter region may be formed in the region exposed in the first region by ion implantation. After forming the emitter region, the fourth mask may be removed.

[0106] After forming the base and the emitter, a second gate structure and a second source-drain metal in the second transistor can be sequentially formed on the second region, while a base contact metal is formed on the base of the first region and an emitter contact metal is formed on the emitter.

[0107] In some embodiments, while sequentially forming the second gate structure and the second source-drain metal in the second transistor on the second region, the implementation process of forming the base contact metal on the base of the first region and the emitter contact metal on the emitter can be: forming a second dielectric layer on the second source-drain structure, the base and the collector; forming a second gate structure based on the second active structure; etching the second dielectric layer to form a second source-drain metal on the second source-drain structure, and forming the base contact metal on the base and the emitter contact metal on the emitter.

[0108] It can be understood that after forming the base and the emitter, an insulating material (such as SiO2) can be deposited on the base, the emitter, and the second source-drain structure, and a flattening process can be performed to form a second interlayer dielectric layer (also referred to as a second dielectric layer), and the second interlayer dielectric layer can cover the base, the emitter, and the second source-drain structure. After that, the second pseudo-gate structure in the second region can be removed to form a second gate structure. Then, the second dielectric layer can be etched to expose the base, the emitter, and the second source-drain structure in the first region, and a metal material can be deposited on the exposed base, the emitter, and the second source-drain structure to form a base contact metal in the first region, an emitter contact metal, and a second source-drain metal in the second region.

[0109] In some embodiments, after forming the base contact metal and the emitter contact metal in the first region and forming the second source and drain metal in the second region, a second metal interconnect layer can be formed through a back-end process (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.). In this way, the back structure of the BJT in the first region and the back transistor of the flip-chip stacked transistor in the second region are prepared.

[0110] In addition, in some embodiments, after forming the second gate structure and before forming the second source and drain, an insulating material may be deposited on the second gate structure in the second region and the base and emitter in the first region to form a third insulating layer, and then a second oxide layer may be formed on the third insulating layer to protect the base and emitter in the first region and the second gate structure in the second region. When the second source and drain metal and the base contact metal and the emitter contact metal are formed by photolithography, if the photolithography drilling is offset, it will also be punched on the insulating layer to prevent the gate metal from directly contacting the source and drain metal, thereby reducing the requirements for photolithography.

[0111] In some embodiments, after forming the base contact metal and the emitter contact metal in the first region and forming the second source and drain metal in the second region, a second metal interconnect layer can be formed through a back-end process (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.). In this way, the back structure of the BJT in the first region and the back transistor of the flip-chip stacked transistor in the second region are prepared.

[0112] The above is the preparation process of forming the base structure and the emitter structure on the back side in the first solution. The following is the preparation process of forming the collector structure on the back side in the second solution.

[0113] In some embodiments, when the second electrode on the back side is the collector (corresponding to the second scheme), when the second transistor in the flip-chip stacked transistor is formed based on the second region, the implementation process of forming the second electrode contact metal on the second electrode structure can be: forming a sixth mask on the first region, and forming a second semiconductor structure based on the second active structure on the second region; removing the sixth mask; forming a second source-drain structure in the second region by ion implantation, and forming a collector contact structure on the collector of the first region, the second source-drain structure is formed after ion implantation of the second semiconductor structure, and the ion concentration of the collector contact structure is higher than the ion concentration of the collector; while sequentially forming the second gate structure and the second source-drain metal in the second transistor on the second region, forming the collector contact metal on the collector contact structure of the first region.

[0114] In some embodiments, before forming the second semiconductor structure based on the second active structure, semiconductor material may be deposited in the gate region of the second transistor to form a second dummy gate structure surrounding the second active structure; and second sidewalls may be formed on both sides of the second dummy gate structure.

[0115] In some embodiments, after forming the second spacer, a second semiconductor structure may be formed on the second dummy gate structure and the second active structure on both sides of the second spacer, that is, a second source-drain structure without ion implantation is formed.

[0116] After forming the second semiconductor structure, the sixth mask can be removed, and the collector contact region of the BJT can be defined by photolithography, and then ion implantation is performed on both regions to form a collector contact region on the first region and a second source-drain structure on the second region.

[0117] It can be understood that after removing the sixth mask, the second source-drain structure can be formed by ion implanting the strained material of the second semiconductor structure in the second region, and the collector contact area is defined by photolithography and then high-concentration ion implantation is performed in the area to form a collector contact structure.

[0118] After forming the second source-drain structure and the collector contact structure, the second gate structure and the second source-drain metal in the second transistor can be sequentially formed on the second region while forming the collector contact metal on the collector contact structure in the first region.

[0119] In some embodiments, while sequentially forming the second gate structure and the second source-drain metal in the second transistor on the second region, the collector contact metal is formed on the collector contact structure in the first region by: forming a second dielectric layer on the second source-drain structure and the collector contact structure; forming a second gate structure based on the second active structure; etching the second dielectric layer to form a second source-drain metal on the second source-drain structure, and forming a collector contact metal on the collector contact structure.

[0120] It can be understood that after the collector contact structure and the second source-drain structure are formed simultaneously, an insulating material (such as SiO2) can be deposited on the collector contact structure and the second source-drain structure, and a flattening process can be performed to form a second interlayer dielectric layer (also referred to as a second dielectric layer), and the second interlayer dielectric layer can cover the collector contact structure and the second source-drain structure. After that, the second dummy gate structure in the second region can be removed to form a second gate structure. Then, the second dielectric layer can be etched to expose the collector contact structure in the first region and the second source-drain structure in the second region, and a metal material can be deposited on the exposed collector contact structure and the second source-drain structure to form a collector contact metal in the first region and a second source-drain metal in the second region.

[0121] In addition, in some embodiments, after forming the second gate structure, an insulating material may be deposited on the second gate structure in the second region and the collector contact structure in the first region to form a third insulating layer, and then a second oxide layer may be formed on the third insulating layer to protect the collector contact structure in the first region and the second gate structure in the second region. When the second source-drain metal and the collector contact metal are formed by photolithography, if the photolithography drilling is offset, it will also be punched on the insulating layer, preventing the gate metal from directly contacting the source-drain metal, thereby reducing the requirements for photolithography.

[0122] In some embodiments, after forming the collector contact metal in the first region and forming the second source and drain metal in the second region, a second metal interconnect layer can be formed through a back-end process (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.). In this way, the back side structure of the BJT in the first region and the back side transistor of the flip-chip stacked transistor in the second region are prepared.

[0123] In the embodiment of the present application, a first electrode structure is formed on a first region of a substrate, and a first transistor in a flip-stack transistor is formed in a second region; the substrate is flipped and removed; a second electrode structure having an ion doping type different from that of the first electrode structure is formed on the first region, and a second transistor in a flip-stack transistor is formed in the second region. The present application saves process steps and enhances the flexibility of semiconductor device circuit design by preparing a through bipolar junction transistor compatible with the flip-stack transistor process.

[0124] Furthermore, the embodiments of the present application can improve the performance of the BJT in the following ways. For example, the area and doping concentration of the collector high doping region can be increased to increase the effective collection area width, reduce the series resistance and increase the maximum current density, but reduce the breakdown voltage. Alternatively, the collector region doping concentration around the base region is reduced to reduce the collector junction parasitic capacitance and increase the Early voltage (VA). Alternatively, the base region thickness is reduced to reduce the base region transit time and increase the frequency of the device, but in order to prevent punch-through, the base region doping concentration needs to be increased, which will reduce VA and current gain, so a trade-off can be made in terms of frequency, VA and current gain.

[0125] The following describes a method for preparing a semiconductor structure provided in an embodiment of the present application by taking a fin-shaped structure as an example in which the active structure in the semiconductor structure is an example. Figure 2 This is a first schematic top view of a semiconductor structure in an embodiment of the present application. Figure 2 (a) is a top view of the BJT. Figure 2 (b) is a top view schematic diagram of the flip-chip stacked transistor. For ease of understanding, the top view in (a) only shows the base region, BJT front structure, BJT back structure, collector region, and BJT region, and the top view in (b) only shows the fin structure, gate structure, and source-drain structure. Among them, the AA' direction is the section direction of the BJT along the BJT front structure; the BB' direction is the section direction of the BJT along the lateral BJT; the A1-A1' direction is the section direction of the stacked transistor along the source-drain structure; the B1-B1' direction is the section direction of the flip-chip stacked transistor along the fin structure.

[0126] The first preparation process is first introduced below. Figures 3 to 14 is a schematic diagram of a semiconductor structure in a first preparation process according to an embodiment of the present application, Figures 3 to 14(a) is a schematic diagram of the structure of a BJT in a semiconductor structure during the first preparation process. Figures 3 to 14 (b) is a schematic diagram of the structure of a flip-chip stack transistor in a semiconductor structure during the first preparation process. Fig.15 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application. Fig.15 (a) is a schematic diagram of the first structure of BJT in a semiconductor structure. Fig.15 (b) is a schematic diagram of the first structure of the flip-chip stack transistor in the semiconductor structure.

[0127] In one example, a first process for preparing a semiconductor structure may include the following steps:

[0128] Step 1: Form a first photoresist layer 22 on the second region of the substrate 21, and use the first photoresist layer 22 as a mask to perform ion doping to obtain Figure 3 The structure shown.

[0129] It can be understood that the first region of the substrate 21 is used to prepare the BJT, and the second region is used to prepare the flip-chip stacked transistor. First, the second region of the substrate 21 can be covered with photoresist to form a first photoresist layer 22, and then the substrate 21 is ion doped using the first photoresist layer 22 as a mask. Since the first region is not covered with photoresist, a collector region 23 can be formed in the planar BJT region by low-doping deep well doping. For example, the ion type doped in the collector region 23 can be a P-type ion.

[0130] Step 2: remove the first photoresist layer 22, and form a second photoresist layer 24 on the collector region, then etch the substrate 21 in the second region using a standard process to form a fin structure 25, and then deposit an insulating material on the substrate 21 to form an isolation structure 26; deposit a semiconductor material on the isolation structure 26 to form a first dummy gate structure 27; and form a first sidewall 28 on both sides of the first dummy gate structure 27 and the first fin structure to obtain a Figure 4 The structure shown.

[0131] It can be understood that the fin structure 25 includes a first fin structure 111 close to the substrate and a second fin structure 121 far from the substrate, and the isolation structure 26 wraps the second fin structure 121 and exposes the first fin structure 111 .

[0132] Step 3: forming a first semiconductor structure 29 on the second region to obtain Figure 5 The structure shown.

[0133] It can be understood that the first fin structure in the source and drain region is etched to a preset height to form a first source and drain groove in the source and drain region, and then a strained material such as silicon germanium or silicon carbide is selectively epitaxially grown in the first source and drain groove to form a first semiconductor structure 29.

[0134] Step 4: remove the second photoresist layer 24, and form a collector contact region 30 in the first region through a heavy doping process, and form a first source-drain structure 112 in the first region, so as to obtain Figure 6 The structure shown.

[0135] It is understandable that after removing the second photoresist layer, the collector contact region of the BJT is defined by photolithography, and then ion doping is performed. For example, the type of ion doping can be P-type ions. Since the first region and the second region are doped at the same time, the collector contact region 30 and the first source-drain structure 112 in the first region are doped with the same ion type.

[0136] It should be noted that the ion type doped in the collector contact region 30 is the same as the ion type doped in the collector region 23 formed in the first step, but the ion concentration is different. The ion concentration doped in the collector contact region is higher than that in the collector region.

[0137] Step 5: Prepare the front transistor of the flip-chip stacked transistor in the second region and prepare the first dielectric layer 31 and collector contact metal 32 in the collector region of the BJT in the first region according to the standard process, and obtain Figure 7 The structure shown.

[0138] It can be understood that an interlayer dielectric is deposited on the first source-drain structure 112 and the collector contact region 30 formed in the previous step to form a first interlayer dielectric layer 113 in the second region and a first dielectric layer 31 in the first region, and then the first dummy gate structure 27 in the second region is removed to form a first gate structure 114, the first interlayer dielectric layer is etched and a metal material is deposited on the exposed first source-drain structure 112 to form a first source-drain metal 115, a portion of the first dielectric layer 31 is photolithographically formed in the first region, and a metal material is deposited at the position where the first dielectric layer 31 is etched to form a collector contact metal 32.

[0139] In addition, after forming the first gate structure, the first gate structure 114 may be selectively etched to a preset height, and an insulating material may be deposited on the etched first gate structure 114 to form a first insulating layer 33 , and then a first oxide layer 34 may be formed on the first insulating layer 33 .

[0140] It should be noted that, since there is no first dummy gate structure in the first region, there is no first gate structure in the first region in this step.

[0141] Step 6: Perform the back-end process and deposit SiO2 to form a second oxide layer 35, and deposit SiCN on the second oxide layer 35 to form a second insulating layer 36, so as to obtain Figure 8 The structure shown.

[0142] Figure 8 The first metal interconnection layer formed by the back-end process is not shown.

[0143] Step 7: Bond the carrier wafer 37 to the second insulating layer 36 above the second insulating layer 36, and then flip the wafer to obtain Fig. 9 The structure shown.

[0144] Step 8: Remove the substrate 21 and thin the isolation structure 26 in the second region to expose the second fin structure, and obtain Fig.10 The structure shown.

[0145] Step 9: Define the base region of the BJT on the second region by photolithography and perform ion doping to form a base region 38, as shown in FIG. Fig.11 The structure shown.

[0146] It can be understood that the doping concentration of the base region is higher than that of the collector region, and the ion type doped in the base region is opposite to the ion type doped in the collector region.

[0147] Step 10: Form a third photoresist layer 39 on the base region 38 of the first region, and then deposit a semiconductor material on the thinned isolation structure 26 to form a second dummy gate structure 40; and form a second sidewall 41 on both sides of the second dummy gate structure 40 and the second fin structure to obtain a Fig.12 The structure shown.

[0148] Step 11: Form a second source-drain structure 122 on the second region to obtain Fig.13 The structure shown.

[0149] It can be understood that the first fin structure in the source-drain region is etched to a preset height to form a first source-drain groove in the source-drain region, and then a strained material such as silicon germanium or silicon carbide is selectively epitaxially grown in the first source-drain groove, and a second source-drain structure 122 is formed on the strained material through a heavy doping process. The ion type doped in the second source-drain structure 122 is opposite to the ion type doped in the first source-drain structure 112.

[0150] Step 12: Remove the third photoresist layer 39, then form a fourth photoresist layer 42 on both the first region and the second region, define the emission region in the first region by photolithography, remove the fourth photoresist layer on the emission region, and then form the emission region 43 by ion implantation, so as to obtain Fig.14 The structure shown.

[0151] It can be understood that the emitter region is a small area on the base region, and the ion type doped in the emitter region is opposite to the ion type doped in the base region, and the ion concentration is different, wherein the ion concentration doped in the emitter region is higher than the ion concentration doped in the base region.

[0152] Step 13: Remove the fourth photoresist layer 42, and then prepare the back transistor of the flip-chip stacked transistor in the second region and prepare the second dielectric layer 44, base contact metal 45, and emitter contact metal 46 of the BJT in the first region according to the standard process, and obtain Fig.15 The structure shown.

[0153] It can be understood that after removing the fifth photoresist layer, an interlayer dielectric is deposited on the second source-drain structure 122, the base region 38, and the emitter region 43 to form a second interlayer dielectric layer 123 in the first region and a second dielectric layer 44 in the first region, and then the second dummy gate structure 40 in the second region is removed to form a second gate structure 124, and the second interlayer dielectric layer is etched and a metal material is deposited on the exposed second source-drain structure 122 to form a second source-drain metal 125. A portion of the first dielectric layer is photoetched in the base region and the emitter region in the first region, and a metal material is deposited at the position where the first dielectric layer is etched to form a base contact metal 45 and an emitter contact metal 46 in the base region, respectively.

[0154] In addition, after forming the second gate structure, the second gate structure 124 may be selectively etched to a preset height, and an insulating material may be deposited on the etched second gate structure 124 to form a third insulating layer 47 , and then a third oxide layer 48 may be formed on the third insulating layer 47 .

[0155] In addition, after forming the third oxide layer, a back-end process can be performed to form a second metal interconnection layer. Fig.15 The second metal interconnect layer is not shown.

[0156] It should be noted that, since there is no second dummy gate structure in the first region, there is no second gate structure in the first region in this step.

[0157] against Fig.15(a), the emitter region 43 forms a PN junction with the base region 38, and the base region 38 also forms a PN junction with the collector region 23. Moreover, the collector region includes the base region, and there are two types of highly doped regions of the same conductivity in the base region, namely, the region in the base region connected to the base contact metal and the region in the emitter region connected to the emitter contact metal. The emitter contact metal in the back structure is connected to a highly doped region surrounded by the base region, whose ion doping type is different from that of the base region. The base contact metal may be directly connected to the base region, or it may be connected to a highly doped region surrounded by the base region, whose ion doping type is the same as that of the base region.

[0158] Fig.16 This is a second schematic top view of the semiconductor structure in the embodiment of the present application. Fig.16 (a) is a top view of the BJT. Fig.16 (b) is a top view schematic diagram of the flip-chip stacked transistor. Fig.17 This is a schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application. Fig.17 (a) is a schematic diagram of the second structure of BJT in the semiconductor structure. Fig.17 (b) is a schematic diagram of a second structure of a flip-chip stacked transistor in a semiconductor structure. Referring to the first preparation method, the preparation can be performed on a multi-fin device.

[0159] Fig.18 This is a schematic diagram of the third structure of the semiconductor structure in the embodiment of the present application. Fig.18 (a) is a schematic diagram of the third structure of BJT in the semiconductor structure. Fig.18 (b) is a schematic diagram of the third structure of the flip-chip stacked transistor in the semiconductor structure. Referring to the first preparation method, the third preparation method is different from the first preparation method in that the N-type device and the N-type collector region are first made on the front side, and then the P-type device and the P-type base region and the N-type emitter region are made on the back side. It should be noted that the ion type doped when the collector region is formed in the first step is the N-type ion.

[0160] Fig.19 This is a schematic diagram of the fourth structure of the semiconductor structure in the embodiment of the present application. Fig.19 (a) is a schematic diagram of the fourth structure of BJT in the semiconductor structure. Fig.16(b) is a schematic diagram of the fourth structure of the flip-chip stacked transistor in the semiconductor structure. When preparing the BJT, the base region and the emitter region are prepared on the front side, and the collector region is prepared on the back side. Referring to the first preparation method, the difference from the first preparation method is that in the fourth preparation method, after the collector region is formed in the first step, the BJT base region is defined on the collector region by photolithography, and ion doping is performed to form the base region, and then in the third step, the first source-drain structure after ion doping is formed in the second region at one time, and according to step eleven, the emitter region is defined by photolithography, and the emitter region is formed by ion implantation, and then the base contact metal and the emitter contact metal are formed respectively. The wafer is then flipped over to form a second source-drain structure that is not ion-doped in the second region, and a collector contact region and a second source-drain structure are formed in the first region and the second region by ion implantation, and finally a collector contact metal is formed in the first region, and a back transistor is formed in the second region.

[0161] The embodiment of the present application can further propose a solution for preparing a through-BJT that is compatible with the process of the self-aligned flip-chip stacked transistor, which not only saves process steps but also enhances the flexibility of the FFET device circuit design.

[0162] It should be noted that the above is an introduction to the structure of the semiconductor structure provided by the present application by taking the fin field effect transistor as an example. The preparation method in the embodiment of the present application can also be applied to the stacking of transistors in various forms such as full-surround gate transistors, planar transistors, vertical field effect transistors, fork-shaped transistors, etc., which are not shown in the embodiment of the present application.

[0163] Furthermore, the flip-chip stacked transistor provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the above semiconductor structure.

[0164] The embodiment of the present application provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can refer to the above semiconductor structure, which will not be described in detail here.

[0165] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be referred to the above semiconductor structure, which will not be repeated here.

[0166] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0167] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Forming a first electrode structure on a first region of a substrate, and forming a first transistor in a flip-chip stack transistor on a second region of the substrate, wherein the first region and the second region are different regions of the substrate in a first direction; Flipping the first electrode structure and the first transistor, and removing the substrate; forming a second electrode structure on the first region, and forming a second transistor in the flip-chip stacked transistor on the second region, wherein the ion doping type of the second electrode structure is different from the ion doping type of the first electrode structure; Among them, the first electrode structure is a base structure, and the second electrode is a collector structure, or the first electrode structure is the collector structure, and the second electrode structure is the base structure; an emitter structure is formed by ion doping in the third region of the base structure, and the ion doping type of the emitter structure is different from the ion doping type of the base structure.

2. The method according to claim 1, characterized in that The method of forming a first electrode structure on a first region of a substrate and forming a first transistor in a flip-chip stacked transistor on a second region of the substrate comprises: forming a first mask on the second region; forming a first electrode on the first region by ion doping; removing the first mask; When the first transistor is formed based on the second region, a first electrode contact metal is formed on the first electrode, and the first electrode and the first electrode contact metal constitute the first electrode structure.

3. The method according to claim 1, characterized in that The forming of a second electrode structure on the first region and the forming of a second transistor in the flip-chip stacked transistor on the second region comprises: forming a second mask on the second region; forming a second electrode on the first region by ion doping, wherein the ion doping type of the second electrode is different from the ion doping type of the first electrode; removing the second mask; When the second transistor is formed based on the second region, a second electrode contact metal is formed on the second electrode, and the second electrode and the second electrode contact metal constitute the second electrode structure.

4. The method according to claim 2, characterized in that: In a case where the first electrode is a collector, in a case where the first transistor is formed based on the second region, forming a first electrode contact metal on the first electrode comprises: forming a third mask on the first region, and etching the substrate in the second region to form an active structure, wherein the active structure includes a first active structure away from the substrate and a second active structure close to the substrate; Based on the first active structure, forming a first semiconductor structure; removing the third mask; forming a first source-drain structure in the second region by ion implantation, and forming a collector contact structure on the collector in the first region, wherein the first source-drain structure is formed after ion implantation of the first semiconductor structure, and the ion concentration of the collector contact structure is higher than the ion concentration of the collector; While the first gate structure and the first source-drain metal in the first transistor are sequentially formed on the second region, a collector contact metal is formed on the collector contact structure in the first region.

5. The method according to claim 4, characterized in that The forming of the first gate structure and the first source-drain metal in the first transistor in sequence on the second region and the forming of the collector contact metal on the collector contact structure of the first region comprises: forming a first dielectric layer on the first source-drain structure and the collector contact structure; Based on the first active structure, forming the first gate structure; The first dielectric layer is etched to form the first source-drain metal on the first source-drain structure, and the collector contact metal is formed on the collector contact structure.

6. The method according to claim 3, characterized in that In a case where the second electrode is a base electrode, in a case where the second transistor is formed based on the second region, forming a second electrode contact metal on the second electrode comprises: forming a fourth mask on the first region, and forming a second source-drain structure based on the second active structure on the second region; forming the fourth mask on the second region, and etching the fourth mask on the first region to expose the region where the emitter is located; forming the emitter in the first region by ion implantation; removing the fourth mask; While the second gate structure and the second source-drain metal of the second transistor are sequentially formed on the second region, a base contact metal is formed on the base of the first region, and an emitter contact metal is formed on the emitter.

7. The method according to claim 6, characterized in that The step of sequentially forming a second gate structure and a second source-drain metal in the second transistor on the second region while forming a base contact metal on the base of the first region and an emitter contact metal on the emitter comprises: forming a second dielectric layer on the second source-drain structure, the base and the emitter; Based on the second active structure, forming the second gate structure; The second dielectric layer is etched to form the second source-drain metal on the second source-drain structure, and the base contact metal is formed on the base, and the emitter contact metal is formed on the emitter.

8. The method according to claim 2, characterized in that: In the case where the first electrode structure is a base electrode structure, forming the first electrode on the first region by ion doping includes: forming a collector on the first region by ion doping; A base is formed on the collector by ion doping, and the ion doping type of the base is different from the ion doping type of the collector.

9. The method according to claim 2, characterized in that: In a case where the first electrode is a base electrode, in a case where the first transistor is formed based on the second region, forming a first electrode contact metal on the first electrode comprises: forming a fifth mask on the first region, and etching the substrate in the second region to form an active structure, wherein the active structure includes a first active structure away from the substrate and a second active structure close to the substrate; Based on the first active structure, a first source-drain structure is formed, wherein the ion doping type in the first source-drain structure is the same as the ion doping type of the base structure; forming the fifth mask on the second region, and etching the fifth mask on the first region to expose the region where the emitter is located; forming the emitter in the first region by ion implantation; removing the fifth mask; While the first gate structure and the first source-drain metal in the first transistor are sequentially formed on the second region, a base contact metal is formed on the base of the first region and an emitter contact metal is formed on the emitter.

10. The method according to claim 3, characterized in that: When the second electrode is a collector, when the second transistor is formed based on the second region, forming a second electrode contact metal on the second electrode includes: forming a sixth mask on the first region, and forming a second semiconductor structure based on the second active structure on the second region; removing the sixth mask; forming a second source-drain structure in the second region by ion implantation, and forming a collector contact structure on the collector in the first region, wherein the second source-drain structure is formed after ion implantation of the second semiconductor structure, and the ion concentration of the collector contact structure is higher than the ion concentration of the collector; While the second gate structure and the second source-drain metal of the second transistor are sequentially formed on the second region, a collector contact metal is formed on the collector contact structure of the first region.

11. A semiconductor structure, prepared by the preparation method according to any one of claims 1 to 10, characterized in that: include: A flip-stack transistor and a bipolar junction transistor located in different regions, wherein the flip-stack transistor and the bipolar junction transistor are formed simultaneously; The flip-chip stacked transistor includes a first transistor and a second transistor that are arranged in opposite directions, and the bipolar junction transistor includes a collector structure, a base structure and an emitter structure, wherein the collector structure is arranged in opposite directions to the base structure and the emitter structure.

12. A semiconductor device, characterized in that: include: The semiconductor structure of claim 11.

13. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 12, wherein the semiconductor device is arranged on the circuit board.

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