Formation method of strained silicon layer and semiconductor structure

Abstract

The invention provides a method for forming a strained silicon layer and a semiconductor structure, which comprises the steps of covering a semiconductor layer and a gate stack structure to form an etching stop layer, and the semiconductor layer comprises a first device region and a second device region which are separated from each other; forming an auxiliary side wall surrounding the side wall of the gate stack structure on the etching stop layer; forming a patterned hard mask layer; taking the patterned hard mask layer as an etching mask, and performing selective etching on the second device region through a wet etching process to form a sigma trench; and growing a strained silicon layer in the sigma groove. According to the invention, on the premise of not sacrificing the consistency of the critical dimensions of the sigma trench, the etching load effect caused by dry etching in the forming process of the sigma trench is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing; in particular, to a method for forming a strained silicon layer. Background Art

[0002] In the field of semiconductor integrated circuit manufacturing technology, with the development of semiconductor technology, the characteristic dimensions of various semiconductor devices are constantly decreasing, and the requirements for the performance of semiconductor devices are getting higher and higher. However, with the increasing integration of CMOS technology and the shrinking of key dimensions, the stress-lifting method used in the traditional CMOS process has been difficult to meet the needs of high-performance devices, especially from the technology node below 40nm, a larger driving current is required to improve the response speed of the circuit. In order to improve the driving current of NMOS and / or PMOS, a wafer with a (110) crystal plane is generally used, and different stresses are applied to the channel to improve the performance of NMOS and PMOS field effect transistors respectively. However, due to the different process steps for NMOS and PMOS, different degrees of etching loads on the top surface of the gate stack structure between NMOS and PMOS will be caused, resulting in a height difference. Additional processes need to be introduced later to solve the above problems, otherwise it will affect the execution of the replacement gate process.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0004] In view of the shortcomings of the prior art mentioned above, the object of the present invention is to provide a method for forming a strained silicon layer and a semiconductor structure, so as to solve the problem that in the existing process for forming a sigma trench, a strained silicon layer is introduced separately or individually in the NMOS and PMOS regions, so that the top surfaces of the gate stack structures in the NMOS and PMOS regions are subjected to different degrees of etching damage, resulting in a height difference between the gate stack structures and the isolation side walls of the two regions, affecting the subsequent replacement gate process.

[0005] To achieve the above object and other related objects, the present invention provides a method for forming a strained silicon layer, comprising the following steps:

[0006] A substrate is provided, on which a semiconductor layer is formed, the semiconductor layer includes a first device region and a second device region separated, a gate stack structure is formed on the first device region and the second device region respectively, the gate stack structure includes a dummy gate and a gate hard mask layer;

[0007] forming a first isolation spacer on the sidewall of the gate stack structure;

[0008] An etch stop layer is formed covering the semiconductor layer, the first isolation sidewall and the top surface of the gate stack structure;

[0009] forming an auxiliary spacer surrounding the sidewall of the gate stack structure on the etch stop layer to define the boundary of the sigma trench to be formed;

[0010] Forming a patterned hard mask layer, wherein the patterned hard mask layer covers the first device region, and removing the etch stop layer covering the second device region and the top surface of the gate stack structure thereof;

[0011] Using the patterned hard mask layer as an etching mask, selectively etching the second device region by a wet etching process to form a sigma trench;

[0012] A strained silicon layer is grown in the sigma trench.

[0013] Optionally, the step of forming the patterned hard mask layer includes: forming a hard mask layer covering the semiconductor layer and the gate stack structure, the material of the hard mask layer includes a polysilicon material layer; based on the photoresist pattern, dry etching the polysilicon material layer, and the dry etching step proceeds to the etch stop layer and stops at the second device region and the top surface of the gate stack structure thereon.

[0014] Optionally, the dry etching of the polysilicon material layer is performed using an etching gas including at least one selected from the following fluorocarbon gases and O2: CF4, CHF3, CH2F2, CH3F.

[0015] Optionally, the step of forming the etch stop layer comprises: using a chemical vapor deposition process to conformally deposit the etch stop layer on the gate stack structure and the semiconductor layer; wherein the thickness of the etch stop layer is to The material of the etching stop layer is silicon oxide or silicon oxynitride.

[0016] Optionally, after the step of forming the strained silicon layer, the step includes: synchronously removing the remaining etch stop layer and the patterned hard mask layer through a wet etching process; wherein the material of the etch stop layer is silicon oxide, and the wet etching process is performed using diluted hydrofluoric acid.

[0017] Optionally, the semiconductor layer is selected to be a single crystal silicon layer with a (110) crystal plane, and the step of forming the sigma trench includes: using the auxiliary sidewall exposed in the second device area to define the boundary of the sigma trench, using a TMAH solution to perform the selective etching step, and forming a sigma trench extending into below the gate stack structure in one step.

[0018] Optionally, after the wet etching step, the method further comprises: wet cleaning the surface of the sigma groove using ammonia water and DSP solution.

[0019] Optionally, the step of forming the sigma groove includes: during wet etching, using a TMAH solution with a concentration between 2wt% and 25wt% to wet-etch the semiconductor layer in the second device area at a temperature of 20° C. to 80° C. for a duration of between 120 seconds and 300 seconds.

[0020] Optionally, one of the first device region and the second device region is an NMOS region, and the other is a PMOS region, wherein when the strained silicon layer is formed as an embedded source and drain region located in the PMOS region, the material of the strained silicon layer is selected to be a doped SiGe epitaxial layer; or, when the strained silicon layer is formed as an embedded source and drain region located in the NMOS region, the material of the strained silicon layer is selected to be a doped SiC epitaxial layer.

[0021] The present invention also provides a method for forming a semiconductor structure, including the method for forming a strained silicon layer as described above; performing a replacement gate process including the following steps: removing a gate hard mask layer and a dummy gate to form a metal gate electrode; wherein the semiconductor structure includes a PMOS region and an NMOS region, and at least one of the PMOS region and the NMOS region includes a strained silicon layer embedded in a source and drain region.

[0022] As described above, the present invention provides a method for forming a strained silicon layer and a semiconductor structure, which has the following beneficial effects:

[0023] The method for forming a strained silicon layer of the present invention, before forming an auxiliary sidewall for defining the boundary of a sigma groove, forms an etch stop layer covering the gate stack structure and the semiconductor layer, so that the dry etching for forming the patterned hard mask layer stops in the etch stop layer, and the sigma groove can be formed only by wet etching based on the patterned hard mask layer, without conventionally adopting a combination of more than one dry etching process and a wet etching process, and avoids the etching load effect caused by dry etching in the formation process of the sigma groove without sacrificing the consistency of the key dimensions of the sigma groove, thereby substantially eliminating the height difference between the gate stack structures in the PMOS and NMOS regions.

[0024] By applying the method for forming a strained silicon layer of the present invention, the height difference between the top surfaces of the gate stack structures in the PMOS and NMOS regions can be basically eliminated, and the influence of different etching loads on subsequent processes can be avoided, especially the planarization treatment before the replacement gate process, thereby improving the process stability without increasing the process cost and process complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A to Figure 1D Schematic diagram showing the structures obtained at different stages of the method for forming an embedded silicon germanium device according to a comparative example of the present invention.

[0026] Figure 2 Shown is a flow chart of a method for forming an embedded silicon germanium device according to an embodiment of the present invention.

[0027] Figure 3A to Figure 3H Schematic diagrams showing structures obtained at different stages of a method for forming a gate stack structure according to an embodiment of the present invention.

[0028] Component number description

[0029] 1.10 semiconductor layer

[0030] 2.20 Isolation Structure

[0031] 11, 110 N-type well region

[0032] 12, 120 P-type well region

[0033] 3. 30a, 30b gate stack structure

[0034] 4.40 Source and drain regions

[0035] 310 high dielectric constant gate dielectric layer

[0036] 320 work function adjustment layer

[0037] 33, 330 dummy gate

[0038] 34, 340 gate hard mask layer

[0039] 5 Isolation side wall

[0040] 50First isolation side wall

[0041] 350 Etch stop layer

[0042] 360 auxiliary side wall

[0043] 6Patterned Hard Mask Layer

[0044] 60 polysilicon layers

[0045] 600 polysilicon material layer

[0046] 221 Initial Groove

[0047] 22, 220 Sigma Groove

[0048] Steps S1 to S4, S100 to S700 DETAILED DESCRIPTION

[0049] Hereinafter, the embodiments of the present invention are described by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. For the purpose of clarity, parts and steps familiar to those skilled in the art are omitted to avoid unnecessary confusion of the elements of the present invention.

[0050] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0051] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0052] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0053] The comparative example of the present invention provides a method for forming a strained silicon layer, which may include:

[0054] Step S1, providing a substrate, on which a semiconductor layer is formed, the semiconductor layer comprising a first device region and a second device region separated from each other, a gate stack structure being formed on the first device region and the second device region respectively, the gate stack structure comprising a dummy gate and a gate hard mask layer;

[0055] Step S2, forming an isolation spacer on the sidewall of the gate stack structure;

[0056] Step S3, covering the first device region with a patterned mask layer, and etching the second device region using the isolation sidewall and the gate stack structure as masks to form a sigma trench extending into a bottom of the gate stack structure;

[0057] Step S4, growing a strained silicon layer in the sigma trench.

[0058] Figure 1A and Figure 1D Shown is a schematic diagram of the structure obtained before and after etching the high dielectric constant gate dielectric layer during the manufacturing process of the gate stack structure of the comparative example.

[0059] In step S1, the semiconductor layer includes a separated PMOS region and an NMOS region, such as Figure 1A As shown, an isolation structure 2 is extended inward from the surface of the semiconductor layer, and an N-type well region 11 and a P-type well region 12 are separated by the isolation structure. A gate stack structure 3 is formed on the N-type well region 11 and the P-type well region 12, and the gate stack structure 3 includes a dummy gate 33 and a gate hard mask layer 34.

[0060] In step S2 , an isolation spacer 5 is formed on the sidewall of the gate stack structure.

[0061] like Figure 1B As shown, in step S3, the patterned mask layer includes a patterned hard mask layer, and the patterned hard mask layer acts as a barrier layer to prevent the NMOS region from being exposed to the etchant during the etching process of the sigma groove; wherein the hard mask layer can be a silicon nitride hard mask layer. In the above step of forming the patterned hard mask layer, the silicon nitride hard mask layer covering the N-type well region is removed by an anisotropic etching process, and the silicon nitride hard mask layer covering the top surface of the gate stack structure is removed synchronously, so that there are different degrees of etching loss between the hard mask layers covering the top surfaces of the gate stack structures of the NMOS and PMOS.

[0062] like Figure 1C and Figure 1D As shown, in step S3, the step of forming the sigma trench 22 includes: performing several dry etching processes based on the patterned hard mask layer 6 to form initial trenches 221 located on both sides of the gate stack structure; then, selectively etching the initial trenches 221 by a wet etching process. Figure 1C As shown, dry etching of the N-type well region 11 based on the patterned hard mask layer 6 will simultaneously sacrifice a portion of the isolation sidewall and consume the gate hard mask layer above the dummy gate. Figure 1D As shown, after the dry etching process is performed, there are different height differences between the gate stack structures located above the N-type well region and the P-type well region, and correspondingly there are height differences between the isolation sidewalls 5 on the sidewalls of the gate stack structures of NMOS and PMOS.

[0063] In step S4, a strained silicon layer is grown in the sigma trench by a selective epitaxial process. In order to improve the carrier mobility in the channel region, a strained silicon layer is embedded in the source and drain regions of the NMOS and PMOS, respectively, or a strained silicon layer is embedded in the source and drain regions of the PMOS alone; wherein the strained silicon layer introduced in the N-type well region may be a strained SiGe layer, and the strained silicon layer introduced in the P-type well region may be a strained SiC layer.

[0064] In addition, after the step of forming the strained silicon layer in step S4, the silicon nitride hard mask layer remaining in the PMOS region can be removed by phosphoric acid, but the above method has shortcomings: when the feature size is below 28nm, the polysilicon gate used as a dummy gate needs to be removed by a replacement gate process to form a metal gate electrode and an optional work function metal layer. Due to the different formation processes of the NMOS and PMOS regions, there is a height difference between the first isolation sidewall of the gate stack structure sidewall of the NMOS and PMOS and the second isolation sidewall outside thereof, which not only increases the process difficulty of the subsequent replacement gate process, but also may introduce a risk of damage between the isolation sidewall and the gate electrode, affecting the reliability of the device.

[0065] Compared with the above-mentioned method for manufacturing the strained silicon layer, the present invention introduces an etch stop layer before the step of defining the sigma groove boundary to protect the top surface of the gate stack structure from etching loss caused by the process sequence of the strained silicon layer. The etch stop layer is removed by an etchant without adding an additional removal step, thereby avoiding the different etching loads of the gate stack structure affecting subsequent processes, and improving its process stability without increasing the process cost and process complexity.

[0066] Hereinafter, the method for forming the strained silicon layer of the present invention will be described in detail with reference to the accompanying drawings.

[0067] See also Figure 2 , this embodiment provides a method for forming a strained silicon layer.

[0068] First, step S100 is performed to provide a substrate, on which a semiconductor layer is formed, the semiconductor layer includes a first device region and a second device region separated, a gate stack structure is formed on the first device region and the second device region respectively, and the gate stack structure includes a dummy gate and a gate hard mask layer.

[0069] Specifically, the substrate may be a semiconductor material or an insulating material, and the material of the semiconductor layer 10 may be selected, for example, one of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide, and indium phosphide. Various doping regions are also formed in the semiconductor layer 10 to form necessary parts or structures of semiconductor devices, the isolation structure is, for example, a shallow trench isolation structure (STI), and the doping region is, for example, a lightly doped source and drain region (LDD). The above structure is determined according to the actual semiconductor device manufacturing process, and is well known to those skilled in the art, and will not be repeated here.

[0070] One of the first device region and the second device region is an NMOS region, and the other is a PMOS region. Hereinafter, the method for forming a strained silicon layer of the present invention will be specifically described by taking the first device region as an NMOS region and the second device region as a PMOS region as an example.

[0071] like Figure 3A As shown, the semiconductor layer 10 includes an N-type well region 110 and a P-type well region 120 separated by an isolation structure, a PMOS gate stack structure 30a is formed on the N-type well region 110, and an NMOS gate stack structure 30b is formed on the P-type well region 120. In this embodiment, the steps of forming the gate stack structures 30a and 30b include sequentially forming a high dielectric constant (k) gate dielectric layer 310, a work function adjustment layer 320, a dummy gate 330, and a retained gate hard mask layer 340; wherein the material of the dummy gate 330 includes one of polycrystalline silicon, amorphous silicon, and microcrystalline silicon, and the gate hard mask layer 340 is a single layer composed of one of silicon oxide, silicon nitride, and silicon oxynitride, or a stack of multiple layers.

[0072] In some examples, the step of forming the high-k gate dielectric layer 310 includes: depositing the high dielectric constant material layer by a high-density plasma chemical vapor deposition (HDPCVD) process, an atomic layer deposition (ALD) or a similar process, wherein the material of the high dielectric constant material layer can be selected from materials suitable for making a high dielectric constant gate dielectric layer, including but not limited to metal oxides of the subgroup or lanthanide series, such as HfO2, CeO2, Y2O3, La2O; nitride oxides, such as SiON, AlON, TiON.

[0073] Next, step S200 is performed to form a first isolation spacer on the sidewall of the gate stack structure.

[0074] Specifically, a first isolation spacer is formed simultaneously on the sidewalls of the gate stack structure in the first device region and the second device region.

[0075] Continue to see Figure 3AAt step S200, the step of forming the first isolation spacer 50 includes: forming a first spacer material layer covering the gate stack structure and the semiconductor layer, wherein the material of the first spacer material layer includes SiO x 、SiN x 、SiN x O y One of the following: removing the first spacer material layer covering the gate stack structure and the semiconductor layer by an anisotropic etching process, such as Figure 3A As shown, the top surface of the obtained first isolation spacer is flush with the top surface of the gate stack structure.

[0076] In step S200 of this embodiment, after the step of forming the first isolation spacer 50 , ion implantation is performed on the N-type well region 110 and the P-type well region 120 respectively to pre-form source and drain regions 40 on both sides of the gate stack structure.

[0077] Next, step S300 is performed to form an etch stop layer covering the semiconductor layer, the first isolation sidewall and the top surface of the gate stack structure.

[0078] Specifically, at step S300, if Figure 3B As shown, the etch stop layer 350 is formed to cover the gate stack structure and the semiconductor layer.

[0079] In some examples, the etch stop layer 350 can be formed by chemical vapor deposition, and the material of the etch stop layer 350 includes one of silicon oxide, silicon nitride, and silicon oxynitride. In a specific example, the material of the etch stop layer 350 can be selected from silicon oxide, and the silicon oxide etch stop layer is deposited by, for example, PETEOS, or PECVD, or a deep aspect ratio sub-atmospheric pressure process chemical vapor deposition method. The thickness of the silicon oxide etch stop layer is to

[0080] Next, step S400 is performed to form an auxiliary spacer on the etch stop layer at the sidewall of the gate stack structure to define the boundary of the sigma trench to be formed.

[0081] For some examples, see FIG. 3C to FIG. 3D The specific steps of forming the auxiliary sidewall 360 are as follows: forming a second sidewall material layer 3600; then, removing a portion of the second sidewall material layer by an anisotropic etching process, and retaining the second sidewall material layer covering the sidewall of the gate stack structure to form an auxiliary sidewall 360 for defining the boundary of the sigma trench; wherein the second sidewall material includes silicon nitride.

[0082] In step S400 of this embodiment, the material of the auxiliary spacer 360 includes silicon nitride, and the second spacer material layer 3600 can be formed by, for example, a reactive sputtering process, a thermal chemical vapor deposition (CVD) process, or a plasma enhanced chemical vapor deposition (PECVD) process.

[0083] Next, step S500 is performed to form a patterned hard mask layer, wherein the patterned hard mask layer covers the first device region, and the etching stop layer covering the second device region and the top surface of the gate stack structure thereof is removed.

[0084] Specifically, after step S300, a patterned hard mask layer is formed by an anisotropic etching process based on the photoresist pattern, and the patterned mask layer acts as a barrier layer to shield the first device region thereunder from the influence of the wet etching process in the subsequent etching process.

[0085] Some examples include FIG. 3E to FIG. 3F , the step of forming the patterned mask layer includes: forming a hard mask layer covering the semiconductor layer 10 and the gate stack structures 30a and 30b, wherein the material of the hard mask layer includes a polysilicon material layer 600; based on the photoresist pattern, dry etching the polysilicon material layer until the polysilicon material covering the second device area is removed to form a polysilicon layer 60 covering the first device area, and the etchant used in the process of etching the polysilicon material has an etching selectivity ratio of the polysilicon material layer 600 to the etch stop layer 350 that is greater than a preset ratio, typically the preset ratio is equal to or greater than 6:1, and more typically the preset ratio is equal to or greater than 10:1, so that the dry etching step proceeds to the etch stop layer and stops at the second device area and the top surface of the gate stack structure thereon, to prevent the underlying material of the etch stop layer from being over-etched. The "photoresist pattern" mentioned here can be formed by a series of operations such as forming a photoresist layer by spin coating on a hard mask layer, soft baking, exposure, development and hard baking. The above operations are technical means well known to those skilled in the art and will not be elaborated on.

[0086] In a preferred example, an etching gas comprising at least one fluorocarbon gas selected from CF4, CHF3, CH2F2, and CH3F and O2 is used for dry etching, and a window defined in a patterned hard mask layer is used as a mask, and the etching step is synchronously stopped at the second device region and the top surface of the gate stack structure thereon. The anisotropic etching process is performed using the above-mentioned etching gas ratio to increase the etching selectivity of polysilicon to silicon oxide to more than 10:1. The "dry etching" mentioned herein may be an anisotropic dry etching scheme, such as the dry etching performed using reactive ion etching (RIE) or plasma etching processes, and during such dry etching, a gas mixture comprising an etching gas and a carrier gas is introduced into the process chamber, or reactive free radicals and ion species generated by a remote plasma generator from the etching gas and the carrier gas.

[0087] Then, step S600 is performed, in which the patterned hard mask layer is used as an etching mask, and the second device region is selectively etched by a wet etching process to form a sigma trench.

[0088] like Figure 3G As shown, the patterned hard mask layer is used as an etching mask, and the N-type well region 110 is selectively etched by a wet etching process, so as to form a sigma trench extending into the bottom of the gate stack structure in one step. In the above-mentioned wet etching process, the auxiliary sidewall exposed in the second device region defines the boundary of the sigma trench, so that the strained silicon material subsequently filled in the sigma trench is adjacent to the channel as an embedded source and drain region, but has a desired spacing between the embedded source and drain regions at a lower depth, thereby avoiding the current leakage problem caused by the closure of the source / drain region at a lower depth.

[0089] In this embodiment, the semiconductor layer has a single crystal silicon layer with a (110) crystal plane, and an alkaline etching solution can be selected to perform the wet etching process. The wet etching process has anisotropy. The alkaline etching solution includes, for example, a tetramethylammonium hydroxide (TMAH) solution. Since a single crystal silicon layer with a (110) crystal plane is selected to make PMOS, the semiconductor layer is selectively etched using the TMAH solution. <100> right <111> The etching selectivity can reach 40:1 to 70:1, so that the wet etching process finally stops at <111> The resulting sigma groove has Figure 3H The shape shown.

[0090] In a specific example, a TMAH solution is used to selectively etch the N-type well region 110. During the wet etching process, a TMAH solution with a concentration between 2wt% and 25wt% is used to wet etch the semiconductor layer of the second device region at a temperature of 20°C to 80°C for a duration of 120 seconds to 300 seconds; wherein the process time of the wet etching for forming the sigma groove can be correspondingly shortened according to the increase in the concentration of the TMAH solution. Since the sigma groove formation process has a huge impact on the electrical properties of the device, the requirements for the critical dimension (CD) of the sigma groove are very precise to avoid electrical deviation caused by deformation of the sigma groove morphology. Compared with the sigma groove formation process composed of a combination of more than one dry etching process and one wet etching process, the above-mentioned scheme uses a wet etching process to form the sigma groove in one step. By appropriately increasing the process time, without sacrificing the consistency of the critical dimensions of the sigma groove, the etching load effect of the gate stack structure caused by dry etching in the formation process of the sigma groove can be avoided.

[0091] Furthermore, at step S600, after the wet etching step, the surface of the sigma groove is wet cleaned with ammonia water and a diluted sulfuric peroxide mixed solution (dilute sulfuric peroxide plus; DSP) in sequence.

[0092] Compared with the comparative example, after the step of forming a patterned hard mask layer, the present solution uses the patterned hard mask layer as an etching mask to form a sigma groove in one step through a wet etching process, thereby effectively avoiding etching loss on the isolation sidewalls and the top surface of the gate stack structure.

[0093] Then, step S700 is performed to grow a strained silicon layer in the sigma trench.

[0094] Specifically, at step S700, a strained silicon layer is grown in the sigma trench by a selective epitaxial process, wherein the selective epitaxial process includes but is not limited to low pressure chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD) or molecular beam epitaxy (MBE).

[0095] One of the first device region and the second device region is an NMOS region, and the other is a PMOS region; wherein a strained SiGe layer is grown in the sigma trench of the PMOS region, and a strained SiC layer is grown in the sigma trench of the NMOS region.

[0096] When the strained silicon layer is formed as an embedded source-drain region located in the PMOS region, the material of the strained silicon layer is selected to be a doped strained SiGe layer; or, when the strained silicon layer is formed as an embedded source-drain region located in the NMOS region, the material of the strained silicon layer is selected to be a doped strained SiC layer. In this embodiment, the step of forming the strained SiGe layer includes: after the step of wet cleaning, growing a SiGe epitaxial layer by an epitaxial process, and in-situ doping the SiGe epitaxial layer; the step of forming the strained SiC layer includes: after the step of wet cleaning, pre-depositing a silicon oxide barrier layer, defining a window in the silicon oxide barrier layer to expose the NMOS region, growing a SiC epitaxial layer on the exposed surface of the sigma trench, and in-situ doping the SiC epitaxial layer.

[0097] Furthermore, after the step of forming the strained silicon layer, the patterned hard mask layer, the auxiliary sidewalls and the etch stop layer covering them are removed synchronously by a wet etching process. In some examples, the etch stop layer is made of silicon oxynitride, and hot phosphoric acid, such as a phosphoric acid solution below 160° C., is used to remove the remaining etch stop layer and the auxiliary sidewalls; or, the etch stop layer is made of silicon oxide, and diluted hydrofluoric acid is used to remove the remaining etch stop layer and the auxiliary sidewalls, without adding an additional removal process.

[0098] Based on the above scheme, the etch stop layer is used to stop the dry etching step of the patterned hard mask layer in time, and in the subsequent sigma trench etching process, the second device area is selectively etched only by a wet etching process, without the need to introduce a dry etching process, and no etching load effect will be caused on the gate stack structure above the device area, thereby ensuring that after the etch stop layer is completely removed, there is no obvious height difference between the gate stack structures of the PMOS area and the NMOS area.

[0099] The present embodiment also provides a method for forming a semiconductor structure, comprising the following steps: the aforementioned method for forming a strained silicon layer; forming a second isolation sidewall on the outer side of the first isolation sidewall; performing a replacement gate process comprising the following steps: removing a gate hard mask layer and a dummy gate to form a metal gate electrode; wherein the semiconductor structure includes forming a PMOS region and an NMOS region, and at least one of the PMOS region and the NMOS region includes a strained silicon layer embedded in a source and drain region.

[0100] Specifically, after removing the remaining etch stop layer and the auxiliary sidewall step, the overall heights of the gate stack structures 30a and 30b of NMOS and PMOS are basically the same, and by sequentially performing a deposition process of a third sidewall material and an anisotropic etching process, a second isolation sidewall is synchronously formed outside the first isolation sidewall of the PMOS region and the NMOS region.

[0101] In some cases, when the material of the gate hard mask layer is silicon nitride and the material of the etch stop layer is silicon oxide, the etching rate of silicon oxide to silicon nitride is adjusted by changing the ratio of the etching gas, such as the carbon-fluorine ratio in the etching gas, thereby effectively reducing the damage to the top of the gate hard mask layer caused by the subsequent second isolation side wall etching process.

[0102] Furthermore, after the step of forming the second isolation sidewall, the deposition of the contact hole etch stop layer and the interlayer dielectric film, planarization treatment, and replacement gate process and other processes are performed in sequence; wherein, the planarization step is performed using a chemical mechanical polishing process (CMP); the replacement gate process includes the following steps, removing the gate hard mask layer and the dummy gate to form an opening, and forming an optional work function adjustment layer and a metal gate electrode in the opening. The above processes are well known to technicians in this field and will not be repeated here.

[0103] Based on the above technical solution, after the embedded source and drain regions are formed, there is almost no height difference between the gate stack structures of the PMOS region and the NMOS region, and the chemical mechanical polishing process performed before the replacement gate process can be reduced from multiple steps to one.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for forming a strained silicon layer, characterized in that: The following steps are involved: A substrate is provided, on which a semiconductor layer is formed, the semiconductor layer includes a first device region and a second device region separated, a gate stack structure is formed on the first device region and the second device region respectively, the gate stack structure includes a dummy gate and a gate hard mask layer; forming a first isolation spacer on the sidewall of the gate stack structure; An etch stop layer is formed covering the semiconductor layer, the first isolation sidewall and the top surface of the gate stack structure; forming an auxiliary spacer surrounding the sidewall of the gate stack structure on the etch stop layer to define the boundary of the sigma trench to be formed; Forming a patterned hard mask layer, wherein the patterned hard mask layer covers the first device region, and removing the etch stop layer covering the second device region and the top surface of the gate stack structure thereof; Using the patterned hard mask layer as an etching mask, selectively etching the second device region by a wet etching process to form a sigma trench; A strained silicon layer is grown in the sigma trench.

2. The method for forming a strained silicon layer according to claim 1, characterized in that: The step of forming the patterned hard mask layer includes: forming a hard mask layer covering the semiconductor layer and the gate stack structure, wherein the material of the hard mask layer includes a polysilicon material layer; based on the photoresist pattern, dry etching the polysilicon material layer, wherein the dry etching step proceeds to the etch stop layer and stops at the second device region and the top surface of the gate stack structure thereon.

3. The method for forming a strained silicon layer according to claim 2, wherein: The dry etching of the polysilicon material layer is performed using an etching gas including at least one selected from the following fluorocarbon gases and O2: CF4, CHF3, CH2F2, CH3F.

4. The method for forming a strained silicon layer according to claim 1, characterized in that: The step of forming the etch stop layer comprises: using a chemical vapor deposition process to conformally deposit the etch stop layer on the gate stack structure and the semiconductor layer; wherein the thickness of the etch stop layer is to The material of the etching stop layer is silicon oxide or silicon oxynitride.

5. The method for forming a strained silicon layer according to claim 4, characterized in that: After the step of forming the strained silicon layer, the method includes: synchronously removing the remaining etch stop layer and the patterned hard mask layer through a wet etching process; wherein the etch stop layer is made of silicon oxide, and the wet etching process is performed using diluted hydrofluoric acid.

6. The method for forming a strained silicon layer according to claim 1, characterized in that: The semiconductor layer is selected to be a single crystal silicon layer with a (110) crystal plane, and the step of forming the sigma trench includes: using the auxiliary sidewall exposed in the second device area to define the boundary of the sigma trench, using a TMAH solution to perform the selective etching step, and forming a sigma trench extending into below the gate stack structure in one step.

7. The method for forming a strained silicon layer according to claim 6, characterized in that: After the wet etching step, the method includes: using ammonia water and DSP solution to wet clean the surface of the sigma groove.

8. The method for forming a strained silicon layer according to claim 6, characterized in that: The step of forming the sigma groove includes: during wet etching, using a TMAH solution with a concentration between 2wt% and 25wt% to wet etch the semiconductor layer in the second device area at a temperature of 20° C. to 80° C. for a duration between 120 seconds and 300 seconds.

9. The method for forming a strained silicon layer according to claim 1, wherein: One of the first device region and the second device region is an NMOS region, and the other is a PMOS region, wherein when the strained silicon layer is formed as an embedded source and drain region located in the PMOS region, the material of the strained silicon layer is selected to be a doped SiGe epitaxial layer; or, when the strained silicon layer is formed as an embedded source and drain region located in the NMOS region, the material of the strained silicon layer is selected to be a doped SiC epitaxial layer.

10. A method for forming a semiconductor structure, characterized in that: It comprises a method for forming a strained silicon layer according to any one of claims 1 to 9; forming a second isolation sidewall on the outer side of the first isolation sidewall; performing a replacement gate process comprising the following steps: removing a gate hard mask layer and a dummy gate to form a metal gate electrode; wherein the semiconductor structure comprises a PMOS region and an NMOS region, and at least one of the PMOS region and the NMOS region comprises a strained silicon layer embedded in a source and drain region.

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