Alternating bare chip wafer

Abstract

The invention provides an alternating type bare chip wafer. The alternating type bare chip wafer comprises a substrate; a plurality of first bare chip columns, wherein each first bare chip column comprises a plurality of first bare chips arranged in one column on the substrate; a plurality of first bare chip columns, a plurality of second bare chip columns, where each second bare chip column includes a plurality of second bare chips arranged in one column on the substrate, and the first bare chip columns and the second bare chip columns are alternately arranged, where the structures of the first and second bare chips are different. According to the invention, different bare chips can be manufactured on the same wafer.

Description

Technical Field

[0001] The present invention relates generally to the field of semiconductors, and more particularly to an alternating bare chip wafer. Background Art

[0002] A wafer is a round sheet, usually made of semiconductor materials such as silicon (Si), and is the basic material for manufacturing chips. On the surface of the wafer, a large number of integrated circuit patterns are produced through a series of complex semiconductor manufacturing processes such as photolithography, etching, and doping. Each independent integrated circuit pattern area is a bare chip.

[0003] At present, due to considerations such as process compatibility, only the same bare chips are made on the same wafer. For example, photolithography is one of the key steps in chip manufacturing. During the photolithography process, a mask is needed to project the circuit pattern onto the wafer. Making a mask is a complex and expensive process, and each chip design requires a special mask. If different bare chips are made on the same wafer, the mask needs to be replaced frequently, which not only increases production costs but also reduces production efficiency. Moreover, after each mask change, the photolithography equipment needs to be recalibrated to ensure the accuracy of the pattern. This process is prone to introduce errors and affect chip quality. In addition, chip manufacturing involves many complex process steps, such as etching, doping, deposition, etc. The parameters of these process steps are optimized according to specific chip designs. If different bare chips are made on the same wafer at the same time, it is difficult to adjust the process parameters for each chip design, which will greatly increase the complexity of process control. For example, during the doping process, different chips may require different doping concentrations and depths, and it is difficult to meet these different requirements on the same wafer at the same time. Summary of the invention

[0004] Based on the prior art, the task of the present invention is to provide an alternating bare chip wafer, through which different bare chips can be manufactured on the same wafer.

[0005] According to the present invention, the aforementioned task is solved by an alternating bare chip wafer, the wafer comprising:

[0006] substrate;

[0007] a plurality of first die columns, wherein each first die column comprises a plurality of first die arranged in a column on the substrate; and

[0008] A plurality of second die columns, wherein each second die column comprises a plurality of second die arranged in a column on the substrate, and the first die column and the second die column are arranged alternately, wherein the structures of the first and second die are different.

[0009] In one embodiment of the present invention, the first and second bare chips are micro light emitting diode chips, and the wiring stack structures of the driving circuits of the first and second bare chips are different.

[0010] In another embodiment of the present invention, a first chip has a first wiring stack and a second chip has a second wiring stack, wherein the first wiring stack and the second wiring stack are complementary to each other.

[0011] In another embodiment of the present invention, it is provided that:

[0012] The first wiring stack includes a first insulating layer and a first metal layer; and

[0013] The second wiring stack includes a second insulating layer and a second metal layer, wherein the first insulating layer and the second metal layer are in the same layer, and the first metal layer and the second metal layer are in the same layer.

[0014] In another embodiment of the present invention, the first and / or second bare chip has:

[0015] a cathode contact portion located on an upper side of the bare chip and configured to electrically connect a cathode of the bare chip;

[0016] an anode contact portion located at the upper and lower sides of the bare chip and configured to electrically connect the anode of the bare chip; and

[0017] The test contact portion is located on the left or right side or both sides of the bare chip and is configured to electrically connect the test port of the bare chip.

[0018] In another embodiment of the present invention, the first and / or second bare chip has:

[0019] A distinguishing mark is disposed on the surface of the bare chip to distinguish the first and second bare chips.

[0020] In another embodiment of the present invention, the distinguishing mark includes one or more of the following:

[0021] Notches, pits, and grooves.

[0022] In another embodiment of the present invention, the notch is a triangular, square, rectangular, trapezoidal, semicircular, polygonal, or irregular notch at the edge of the bare chip.

[0023] In another embodiment of the present invention, the distinguishing marks of the first bare chip and the second bare chip have different shapes, and the distinguishing marks have a reflective layer, which is configured to reflect light falling thereon to form reflected light, and the reflected light can be identified by a machine as the first or second bare chip.

[0024] In another embodiment of the present invention, one of the first and second bare chips is provided with the distinguishing mark, and the reflective layer is a metal layer.

[0025] In another embodiment of the present invention, it is provided that:

[0026] The spacing between a first bare chip column and an adjacent second bare chip column is 50 to 500 μm.; and / or

[0027] The spacing between adjacent first bare chips is 50 to 500 μm; and / or

[0028] The interval between adjacent second bare chips is 50 to 500 μm.

[0029] In another embodiment of the present invention, the first die has a first size and the second die has a second size, wherein the first size is equal to the second size.

[0030] In another embodiment of the present invention, the first bare chip has a first size and the second bare chip has a second size, wherein the first size is larger than the second size, and the second size is determined so that a first wafer area occupied by an edge bare chip of the bare chip wafer is smaller than a second wafer area occupied by an edge bare chip of the bare chip wafer when only the first bare chip is arranged.

[0031] In another embodiment of the present invention, it is provided that:

[0032] The second size is determined so that one or both of the two bare chip columns arranged at the outermost edge of the bare chip wafer are second bare chip columns; or

[0033] The first and second die are arranged such that one or both of the two die columns arranged at the outermost edge of the die wafer are the second die column.

[0034] In another embodiment of the present invention, the size includes: length and width.

[0035] In another embodiment of the present invention, the first die and the second die have:

[0036] Same or different light emitting areas; and / or

[0037] Same or different drive circuits.

[0038] In another embodiment of the present invention, the light emitting diode chip comprises:

[0039] A driving circuit, a metal layer is provided on the surface of the driving circuit, a plurality of IC copper pillars are provided on the driving circuit, the IC copper pillars are electrically connected to the metal layer, the micro-LED array area is bonded to the driving circuit through a bottom conductive bonding layer, wherein the driving circuit further has a wiring stack under the metal layer, which is configured to lead out a first electrode;

[0040] Light-emitting mesas, each light-emitting mesas corresponding to an IC copper column, and the light-emitting mesas include a first epitaxial layer, a light-emitting layer and a second epitaxial layer deposited in sequence;

[0041] at least one first electrode electrically connected to the IC copper pillar;

[0042] A passivation isolation layer covering the surface of the light-emitting mesa but exposing at least a portion of the second epitaxial layer;

[0043] a transparent conductive layer, which is disposed on a surface of the passivation insulating layer and is in electrical contact with the first epitaxial layer; and

[0044] The second electrode is disposed on the surface of the transparent conductive layer.

[0045] In one embodiment of the present invention, the second electrode is a ring-shaped reflective electrode, which is arranged around the light-emitting mesa.

[0046] In another embodiment of the present invention, the polarity of the second electrode is opposite to that of the first electrode.

[0047] In another embodiment of the present invention, the material of the second epitaxial layer is a material layer of the second conductive type containing at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of the first conductive type containing at least two or more elements of Ga, N, As, Al, In, and P, wherein the first conductive type is different from the second conductive type.

[0048] In another embodiment of the present invention, the light emitting layer comprises a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, an InGaAs / AlGaAs multi-quantum well layer, or an AlGaInP multi-quantum well layer.

[0049] In another embodiment of the present invention, an electron blocking layer is disposed on a first side of the light-emitting layer, wherein the first side refers to a side along which electrons migrate out of the light-emitting layer.

[0050] In another embodiment of the present invention, the material of the passivation layer is Si 3 N 4 Membrane, SiO2 Film or Al 2 O 3 membrane.

[0051] In another embodiment of the present invention, the material of the substrate is selected from the group consisting of silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), gallium nitride (GaN), glass, aluminum nitride (AlN), sapphire (α-Al2O3), and germanium (Ge).

[0052] In another embodiment of the present invention, it is provided that:

[0053] The material of the first and / or second insulating layer is selected from the group consisting of silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or any combination thereof; and / or

[0054] The material of the first and / or second metal layer is selected from the group consisting of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), gold (Au), nickel (Ni), platinum (Pt), tantalum (Ta), and molybdenum (Mo).

[0055] The present invention has at least the following technical effects:

[0056] (1) The present invention achieves the purpose of arranging different bare chips on the same wafer by alternately arranging first bare chips and second bare chips with different structures, thereby providing an alternative solution for the bare chip manufacturing method.

[0057] (2) When the first and second bare chips are micro-LED chips, since the light-emitting structures of the micro-LED chips are the same, there is no process compatibility problem in this part; the two chips differ only in the difference in the underlying driving circuits, and even if the wiring structures of the driving circuits are different, they are mainly composed of insulating layers and metal layers. From the process characteristics of metal and insulating layers, it can be seen that both metal and insulating layers can be deposited on the same layer, or the insulating layer can be deposited first and then the metal can be deposited by etching, or vice versa. Therefore, the coexistence of insulating layers and metal layers can be easily achieved on the same layer, and their etching can be achieved through the same mask without changing the mask. In addition, by alternately arranging two types of micro-LEDs with different underlying driving circuits, it is also possible to achieve wiring complementarity and better utilize the wiring area.

[0058] (3) When the first and second bare chips are micro-LED chips, since the light-emitting area of ​​the micro-LED mainly depends on the number of micro-LEDs, the light-emitting area can be easily adjusted without affecting process compatibility. By reasonably determining the size of the first and second bare chips, the area of ​​the wafer occupied by the edge bare chips at the edge of the wafer can be reduced, thereby increasing the usable area of ​​the wafer. The edge bare chips cannot be used as normal chips due to their incomplete structures and are generally discarded. For example, by setting the size of one or both of the first and second bare chips, a second bare chip of smaller size can be arranged at one or both edges, or more rows of chips can be arranged compared to arranging a single chip, thereby increasing the wafer utilization area. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

[0060] Figure 1 A schematic diagram showing a first embodiment of an alternating bare chip wafer according to the present invention is shown;

[0061] Figure 2 A schematic diagram showing the surface and appearance of a first bare chip and a second bare chip of an alternating bare chip wafer according to the present invention is shown;

[0062] Figure 3A and 3B A schematic diagram of solder foot contact portions of a first bare chip and a second bare chip according to the present invention is shown;

[0063] Figure 4A 4B shows a schematic diagram of a second embodiment of an alternating bare chip wafer according to the present invention; and

[0064] Figure 5 A schematic diagram of a micro light emitting diode chip of a light source machine according to the present invention is shown. DETAILED DESCRIPTION

[0065] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be implemented without one or more specific details or with other alternative and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the inventive points of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are described to provide a comprehensive understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details.

[0066] It should be noted that the components in the figures may be shown exaggeratedly for the sake of illustration and are not necessarily true to scale. In the figures, identical or functionally identical components are provided with the same reference numerals.

[0067] In the present invention, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." merely indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0068] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0069] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of a plurality of elements.

[0070] In the present invention, the term “connected” may refer to both being directly connected or being indirectly connected via an intermediate element.

[0071] In the present application, the term "configuration" refers to the setting of the shape, structure, material and / or function of the target object to achieve the desired technical effect, wherein "configuration" includes a variety of alternative technical means for achieving the technical effect, which become obvious under the teaching of the present application.

[0072] In this specification, references to "one embodiment" or "the embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0073] It should be noted that the embodiments of the present invention describe the process steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0074] In the present invention, the term "bare chips are arranged in columns on a wafer substrate" covers both arrangement in rows and in columns on a wafer substrate. Moreover, when the bare chips on the wafer are arranged in rotational symmetry, when the wafer is rotated by a certain angle, the columns of bare chips may become rows, and vice versa.

[0075] In the present invention, the term "bare chip" is also called bare crystal, chip die or unpackaged chip, which refers to an integrated circuit chip that has not been packaged after wafer manufacturing and chip processing steps (such as deposition, etching, grinding, etc.) in the semiconductor manufacturing process. It should also be pointed out that the term "micro light emitting diode chip" can refer to both unpackaged micro light emitting diode bare chips and packaged micro light emitting diode finished chips.

[0076] Figure 1 FIG. 1 is a schematic diagram showing a first embodiment of an alternating bare chip wafer 100 according to the present invention.

[0077] like Figure 1 As shown, the alternating bare chip wafer 100 according to the present invention includes the following components: a substrate 103, and first bare chip columns 101 and second bare chip columns 102 arranged alternately, wherein the first bare chip column 101 includes a plurality of first bare chips 101A, and the second bare chip column 102 includes a plurality of second bare chips 102A. The first bare chip 101A and the second bare chip 102A have different structures from each other. Here, the first bare chip 101A and the second bare chip 102A are both micro light emitting diode chips, which have the same light emitting surface, but have different driving circuits, which is manifested in that they have different ports, i.e., different contacts. For a more detailed description of the first bare chip 101A and the second bare chip 102A, refer to Figure 2 Each component is described in detail below, wherein the corresponding components are marked with "·".

[0078] Substrate

[0079] The alternating bare chip wafer 100 according to the present invention includes a substrate 103 .

[0080] The substrate 103 is configured to carry the first bare chip 101A and the second bare chip 102A. In some embodiments, the substrate 103 can be acted by the driving circuit or its bottom portion, while in other embodiments, the substrate 103 is a separate component. The substrate can be a transparent substrate, such as a glass substrate, or an opaque substrate. Examples of glass substrates include: quartz glass, silicate glass, soda-lime glass, and fluoride glass. Examples of other substrates include: Si, Ge, GaN, GaAs, GaP, InP, SiC, ZnO, metal, Al 2 O 3 , Al N and sapphire substrates, etc. In some embodiments, the substrate is about 700 microns thick.

[0081] ·First Bare Chip Column

[0082] The alternating bare chip wafer 100 according to the present invention further includes a first bare chip column 101 .

[0083] Each first bare chip column 101 includes a plurality of first bare chips 101A arranged in a column on a substrate. The first bare chip column 101 and the second bare chip column 102 are arranged alternately with each other, that is, the column adjacent to the first bare chip column 101 is the second bare chip column 102, and the column adjacent to the second bare chip column 102 is the first bare chip column 101. Here, the first bare chip column 101 has a first structure, and the second bare chip 102 has a second structure, and the first structure is different from the second structure. For example, in the case where the first and second bare chips 101A and 102A are both micro light-emitting diode chips, the first bare chip column 101 and the second bare chip column 102 have different drive circuits, but they have the same light-emitting surface or light-emitting layer structure. Such structural differences and similarities realize process compatibility. The structural differences of the drive circuit are, for example, reflected in the difference of the port or the contact portion. The first bare chip 101 may have a first size, such as length and width. The length of the first bare chip 101 is, for example, 0.5 to 5 cm, and the width is, for example, 0.3 to 3 cm. Other sizes are also conceivable.

[0084] like Figure 1 As shown, the alternating bare chip wafer 100 is circular, and the first bare chip 101A and the second bare chip 101B are rectangular bare chips, and are formed in a column on a substrate 103. Each column contains the same chips, that is, each column is either a first bare chip column 101, which includes a plurality of first bare chips 101A; or a second bare chip column 102, which includes a plurality of second bare chips 102A.

[0085] · Second bare chip row

[0086] The alternating bare die wafer 100 according to the present invention further includes a second bare die column 102 .

[0087] Each second bare chip column 102 includes a plurality of second bare chips 102A arranged in a column on the substrate. The second bare chip column 102 and the first bare chip column 101 are arranged alternately with each other, that is, the column adjacent to the first bare chip column 101 is the second bare chip column 102, and the column adjacent to the second bare chip column 102 is the first bare chip column 101. Here, the second bare chip column 102 has a second structure, and the second structure is different from the first structure of the first bare chip column 101. The present invention achieves the purpose of arranging different bare chips on the same wafer 100 by alternately arranging the first bare chips 101A and the second bare chips 102A with different structures, and provides an alternative solution for the bare chip manufacturing method.

[0088] In the case where the first and second bare chips 101A and 102A are both micro-light emitting diode chips, the first bare chip column 101 and the second bare chip column 102 have different driving circuits, but they have the same light-emitting surface or light-emitting layer structure. Such structural differences and similarities achieve process compatibility. The structural differences of the driving circuit are, for example, reflected in the difference in ports or contacts. The second bare chip 102 can have a second size, such as length and width. The length of the second bare chip 102 is, for example, 0.5 to 5 cm, and the width is, for example, 0.3 to 3 cm. Other sizes are also conceivable. Here, the size of the second bare chip 102 is different from the size of the first bare chip 101, such as different lengths or widths. For example, the width of the second bare chip 102 is less than the width of the first bare chip 101, thereby reducing the wafer area occupied by the edge bare chip 104. The principle is described below.

[0089] There are one or more edge bare chips 104 at the edge of the alternating bare chip wafer 100. The edge bare chip 104 cannot be used as a normal chip due to its incomplete structure and is generally scrapped. For example, by setting the size of one or both of the first and second bare chips, smaller bare chips can be arranged at one or both edges, or more rows of chips can be arranged compared to arranging a single chip, thereby increasing the wafer utilization area. For example, the length of the second bare chip 102 is smaller than the length (lateral dimension) of the first bare chip 101, and the smaller second bare chip 102 is arranged at one or both edges, which can reduce the maximum length of the edge bare chip on the wafer 100, thereby reducing the wafer area occupied by the edge bare chip and increasing the effective utilization area of ​​the wafer. For an embodiment of the size arrangement, see Figure 4A and 4B.

[0090] Figure 2 A schematic diagram of a first bare chip 101A and a second bare chip 102A of an alternating bare chip wafer according to the present invention is shown.

[0091] like Figure 2 As shown, the first die 101A comes from a first die column 101 , and the second die 102A comes from a second die column 102 , wherein the first die column 101 and the second die column 102 are alternately arranged on a substrate 103 .

[0092] In this embodiment, the first bare chip 101A and the second bare chip 102A are both shown as micro light emitting diode chips. However, it should be noted that in other embodiments, other chips are also conceivable. The ports or contacts of the first bare chip 101A and the second bare chip 102A are described below. For further details about the micro light emitting diode chips, please refer to Figure 4 and its description.

[0093] The first bare chip 101A includes a light emitting surface 204A, an anode contact 201A, a cathode contact 202A, and a distinguishing mark 205A. The second bare chip 102A includes a light emitting surface 204B, an anode contact 201B, a cathode contact 202B, a test contact 205 and a distinguishing mark 205B.

[0094] The light emitting surface 204A and the light emitting surface 204B are both composed of micro-light emitting diode arrays, and their sizes depend on the number of micro-light emitting diodes (assuming that the unit size of the micro-light emitting diodes is a fixed size). The light emitting surface 204A and the light emitting surface 204B are configured to emit light. Here, the light emitting surface 204A is slightly smaller than the light emitting surface 204B, but in other embodiments, the light emitting surface 204A can be greater than or equal to the light emitting surface 204B. In order to manufacture light emitting surfaces of different sizes or shapes, the range of etching and deposition can be controlled in the same process step to achieve light emitting surfaces of different sizes.

[0095] The cathode contact 202A is located on the upper side of the first bare chip 101A and is configured to electrically connect the cathode of the bare chip. Similarly, the cathode contact 202B is located on the upper side of the second bare chip 102A and is configured to electrically connect the cathode of the bare chip. Here, the cathode contact 202A and the cathode contact 202A are both common cathode structures, that is, all the micro-light emitting diode cathodes of each micro-light emitting diode array of the bare chip are connected together. Therefore, due to the common cathode structure, the number of contacts of the cathode contact 202A is less than the number of contacts of the anode contact 201A. In this embodiment, the cathode contact 202A and the anode contact 201A are both arranged on the upper side of the first bare chip 101A. In other embodiments, the cathode contact 202A and the anode contact 201A can also be arranged together on the lower side of the first bare chip 101A. Similarly, due to the common cathode structure, the number of contacts of the cathode contact 202B is also less than the number of contacts of the anode contact 201B. In this embodiment, the cathode contact portion 202B and the anode contact portion 201B are both arranged on the upper side of the second bare chip 102A. In other embodiments, the cathode contact portion 202B and the anode contact portion 201B can also be arranged together on the lower side of the second bare chip 102A. For further details about the cathode contact portion, please refer to Figure 3A and 3B In order to manufacture cathode contacts of different positions or shapes, the positions and / or ranges of etching and deposition can be controlled in the same process step to realize cathode contacts of different positions or shapes.

[0096] A metal layer 206A is also arranged on the upper surface of the first bare chip 101A, and the metal layer 206A is configured to achieve electrical contact with a common cathode. Similarly, a metal layer 206B is also arranged on the upper surface of the second bare chip 102A, and the metal layer 206B is configured to achieve electrical contact with a common cathode. In order to manufacture metal layers of different sizes or shapes, the range of etching and deposition can be controlled in the same process step to achieve metal layers of different sizes or shapes.

[0097] The anode contact 201A is located on the upper and lower sides of the first bare chip 101A and is configured to electrically connect the anode of the first bare chip 101A. Similarly, the anode contact 201B is located on the upper and lower sides of the second bare chip 102A and is configured to electrically connect the anode of the second bare chip 102A. The anode contact and the cathode contact can be connected to the corresponding terminals of the external control source or power supply to control or power the bare chip. The anode contact 201A and the anode contact 201B respectively have a plurality of contacts. Here, the anode contact 201A and the cathode contact 202A are both arranged on the upper side of the first bare chip 101A, and the contacts of the two can be arranged separately or staggered. Here, for the convenience of wiring, the contacts of the anode contact 201A and the cathode contact 202A are staggered together on the upper side of the first bare chip 101A. Similarly, the anode contact 201B and the cathode contact 202B are both arranged on the upper side of the second bare chip 102A, and the contacts of the two can be arranged separately or staggered. Here, due to the convenience of wiring, the contacts of the anode contact 201B and the cathode contact 202B are arranged together in an interlaced manner on the upper side of the second bare chip 102A. In the case of a passive matrix driving mode, each contact of the anode contact 201A is respectively connected to the anodes of the micro-light emitting diodes with the same number in different micro-light emitting diode arrays of the first bare chip 101A, thereby combining the different cathode contacts of each array to achieve individual control of each micro-light emitting diode. Similarly, each contact of the anode contact 201B is respectively connected to the anodes of the micro-light emitting diodes with the same number in different micro-light emitting diode arrays of the second bare chip 102A, thereby combining the different cathode contacts of each array to achieve individual control of each micro-light emitting diode. In order to manufacture anode contacts of different positions or shapes, the position and / or range of etching and deposition can be controlled in the same process step to achieve anode contacts of different positions or shapes. For further details about the anode contact, please refer to Figure 3A and 3B and its description.

[0098] The test contact portion 203 is located on one or both sides of the second bare chip 102A and is configured to electrically connect the test port of the bare chip. In this embodiment, the first bare chip 101A is not equipped with a test contact portion 203. Similar to the cathode and anode contact portions, the test contact portion 203 also has a plurality of contacts. For further details about the test contact portion 203, please refer to Figure 3A and 3B In order to avoid manufacturing test contacts or manufacturing test contacts with different positions or shapes, the target area may not be processed in the same process step or the position and / or range of etching and deposition may be controlled to avoid manufacturing test contacts or manufacturing anode contacts with different positions or shapes. For further details on test contacts, see Figure 3A and 3B and its description.

[0099] In addition, the first bare chip 101A and the second bare chip 102A also have distinguishing marks 205A and 205B, respectively. The distinguishing marks are configured to distinguish the first bare chip 101A and the second bare chip 102A from each other to achieve bare chip sorting. The distinguishing marks of different types of bare chips can have different shapes, and / or different colors and / or different reflected light. For example, the distinguishing marks can have different shapes, such as notches, pits, grooves, etc., or triangles, squares, rectangles, trapezoids, semicircles, polygons, or irregular shapes; the distinguishing marks can also be equipped with a reflective layer so as to reflect different colors of light or different shapes of light spots when illuminated, where the different colors are determined by the coating of the reflective layer, and the different shapes are determined by the shape of the reflective layer or the shape of the distinguishing mark. Reflected light can facilitate machine recognition, thereby achieving automated bare chip sorting. In the present embodiment, the distinguishing mark 205A is a trapezoidal notch, and the distinguishing mark 205B is a rectangular notch. The distinguishing mark 205A is arranged on both sides of the first bare chip 101A, and the distinguishing mark 205B is arranged on the right side of the second bare chip 102A. While these settings are merely exemplary, in other embodiments, the distinguishing marks can be arranged on both sides, and can also be a depression or groove in the middle of the bare chip instead of a notch on the edge. In order not to manufacture distinguishing marks or to manufacture distinguishing marks with different positions or shapes, the target area can be not processed in the same process step or the position and / or range of etching can be controlled to not manufacture a test contact portion or to manufacture an anode contact portion with different positions or shapes.

[0100] Figure 3A and 3B FIG. 1 shows a schematic diagram of solder foot contact portions (hereinafter referred to as “contact portions”) of a first bare chip 101A and a second bare chip 102A according to the present invention, wherein Figure 3A The contacts of the first die 101A are shown, and Figure 3BThe contact portions of the second die 102A are shown. Each contact portion can be regarded as a terminal of a port for electrical connection with a corresponding terminal of a corresponding port.

[0101] like Figure 3A As shown in the upper contact portion 301A of the first bare chip 101A, the upper contact portion 301A includes, for example, the following contacts:

[0102] VSS, etc.: grounding;

[0103] VDD, etc.: power supply;

[0104] GSET, GRST, RRST, etc.: set, reset;

[0105] LCLK, etc.: clock signal;

[0106] DIN: cathode;

[0107] VDDP: Anode.

[0108] According to the definition of contacts, the upper side of the first bare chip 101A includes both an anode contact portion and a cathode contact portion, as well as some control signal terminals such as clock and set, as well as power and custom signal terminals.

[0109] like Figure 3A As shown in the lower contact portion 302A of the first bare chip 101A, the lower contact portion 302A includes, for example, the following contacts:

[0110] VSS, etc.: grounding;

[0111] VDD, etc.: power supply;

[0112] DIN: cathode;

[0113] VDDP: Anode.

[0114] According to the definition of contacts, the lower side of the first bare chip 101A mainly includes a power terminal and an anode contact portion.

[0115] The layout of the contacts or terminals mainly depends on the location of the drive circuit wiring and the light-emitting diode unit. In this embodiment, the difference in the structure of the wiring stack of the drive circuit of the first and second bare chips leads to the difference in the lead-out position of the above contacts. In different embodiments, different contact or terminal layouts can be used.

[0116] like Figure 3B As shown in the upper contact portion 301B of the second bare chip 102A, the upper contact portion 301B includes, for example, the following contacts:

[0117] VSS, etc.: grounding;

[0118] VDD, etc.: power supply;

[0119] GSET, GRST, RRST, ResSw, etc.: set, reset;

[0120] LCLK, etc.: clock signal;

[0121] DIN: cathode;

[0122] VDDP: Anode.

[0123] According to the definition of the contacts, the upper side of the second bare chip 102A includes both an anode contact portion and a cathode contact portion, as well as some control signal terminals such as clock and set, as well as power supply and custom signal terminals. Although the definitions of some contacts of the first and second bare chips are the same, the positions of some terminals are not the same. Moreover, some terminals only appear in the first bare chip, while other terminals only appear in the second bare chip. This is due to the difference in the wiring stacks in the driving circuits of the two.

[0124] like Figure 3B As shown in the lower contact portion 302B of the second bare chip 102A, the lower contact portion 302B includes, for example, the following contacts:

[0125] VSS, etc.: grounding;

[0126] VDD, etc.: power supply;

[0127] DIN: cathode;

[0128] VDDP: Anode.

[0129] According to the definition of contacts, the lower side of the first bare chip 101A mainly includes a power terminal and an anode contact portion.

[0130] The layout of the contacts or terminals mainly depends on the location of the drive circuit wiring and the light emitting diode unit. In different embodiments, different contact or terminal layouts can be used.

[0131] In addition, the left and right sides of the second bare chip 102A further include test contact portions, such as contacts RDBG, ENBGBF, BLT, etc. included on the left side, and contacts RNT, BLT, etc. included on the right side.

[0132] The layout of the contacts or terminals mainly depends on the location of the drive circuit wiring and the light-emitting diode unit. In this embodiment, the difference in the wiring stack structure of the drive circuit of the first and second bare chips leads to the difference in the lead-out position of the above contacts and the additional presence of the test contacts. In different embodiments, different contact or terminal layouts can be used.

[0133] Figure 4A4B and 4B are schematic diagrams showing a second embodiment of an alternating bare chip wafer according to the present invention.

[0134] Figure 4A and the second embodiment shown in 4B and Figure 1 The first embodiment shown is basically the same, and the main difference between the two is that in the first embodiment, the sizes of the first bare chip and the second bare chip are basically the same, and the difference is that the wiring of the driving circuit is different; while in the second embodiment, the sizes of the first bare chip and the second bare chip are different.

[0135] like Figure 4A As shown, the bare chip wafer 300 is a bare chip wafer of the prior art, which has a plurality of identical bare chips 300A. The edge bare chips cannot be used as normal chips due to their incomplete structures and are generally discarded. After removing the edge bare chips, the effective wafer area of ​​the bare chip wafer 300 is shown in the dotted box 302.

[0136] As shown in FIG. 4B , the bare chip wafer 300 according to the present invention is an alternating bare chip wafer in which a first bare chip 301A and a second bare chip 301B are alternately arranged. The size of the first bare chip 301A is larger than the size of the second bare chip 301B, and is equal to the size of the bare chip 300A of the bare chip wafer 300. Here, the width of the first bare chip 301A is larger than the length (lateral dimension) of the second bare chip 301B, and the widths (longitudinal dimensions) of the two are equal. As shown in FIG. 4B , by selecting the size, as many edge bare chips as possible can be the second bare chip 301B with a smaller size. The edge bare chip cannot be used as a normal chip due to its incomplete structure and is generally scrapped. Therefore, after removing the edge bare chip, the effective wafer area of ​​the alternating bare chip wafer 301 according to the present invention is shown in the dotted box 303.

[0137] from Figure 4A As can be seen from FIGS. 4B and 4B , the effective wafer area 303 of the alternating bare chip wafer 301 according to the present invention is significantly larger than the effective wafer area 302 of the bare chip wafer 300 of the prior art.

[0138] In addition, when the length relationship of the first and second bare chips is properly selected, a similar effect of increasing the effective wafer area 302 can be achieved. Alternatively, when both the length and width relationship of the first and second bare chips are properly selected, a similar effect of increasing the effective wafer area 302 can be achieved.

[0139] Figure 5 A schematic diagram of a micro light emitting diode chip of a light source machine according to the present invention is shown.

[0140] like Figure 5 As shown, the micro light emitting diode chip of the light emitting panel 101 of the light source machine includes the following components:

[0141] · Driving circuit 602 (i.e., driving backplane), driving circuit 602 may be based on silicon or glass, i.e., driving circuit 602 may have a silicon or glass substrate. Driving circuit 602 may, for example, be a driving circuit in various forms, such as a CMOS driving circuit or a thin film transistor TFT driving circuit, such as a 2T1C driving circuit, a 3T1C driving circuit, and a 5T2C driving circuit. Driving circuit 602 is configured to drive micro light emitting diodes, such as controlling the connection, disconnection, and brightness of micro light emitting diodes. Driving circuit 602 may, for example, include transistors, capacitors, a conductive circuit layer, an insulating layer, and a metal layer. The conductive circuit layer may be formed on a substrate and configured to power the micro light emitting diode array. The material of the substrate may, for example, include silicon, silicon oxide, silicon nitride, silicon carbide, gallium nitride, glass, aluminum nitride, sapphire, and germanium. An insulating layer is formed on the conductive circuit layer, wherein a through hole is provided in the insulating layer, and a through hole contact portion (e.g., an IC copper column) is provided in the through hole for electrically connecting the conductive circuit layer to the micro light emitting diode array. The metal layer is used for bonding and electrically contacting the micro light emitting diode. The conductive circuit layer, the metal layer and the insulating layer may have been formed on the substrate 601 by deposition, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). Depending on the specific application scenario, the metal layer and the insulating layer may be patterned by photolithography and through holes may be formed thereon. In addition, the transistors and capacitors in the conductive circuit layer may be formed by deposition and etching. In the present invention, the drive circuits of the first bare chip and the second bare chip may be structurally different from each other. For example, the two may differ in the arrangement of the insulating layer and the metal layer. Since the processes of the insulating layer and the metal layer are compatible with each other, the processes are fully compatible as long as the number of deposited layers of the drive circuit is the same. For example, the insulating layer of the first bare chip may be the metal layer of the second bare chip, or vice versa. Or the two stacks are the same, but the through hole positions are different. In addition, even if the number of layers of the two is slightly different, the processes may be made compatible by changing the layer thickness. For example, the two layers may be merged into one layer. The material of the insulating layer of the driving circuit may include, for example, silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or any combination thereof. The material of the metal layer of the driving circuit may include, for example, aluminum (Al), copper (Cu), tungsten (W), silver (Ag), gold (Au), nickel (Ni), platinum (Pt), tantalum (Ta), and molybdenum (Mo).

[0142] In one embodiment of the present invention, the circuit may be electrically connected to each micro-LED in the micro-LED array via a separate metal interconnect. In some embodiments, each micro-LED may be electrically controlled individually by a drive circuit. In some embodiments, the drive backplane may be electrically connected to electrodes of a micro-LED chip via a metal interconnect. In some embodiments, a dielectric layer may be formed in the gaps between the micro-LEDs. In some embodiments, a dielectric layer may also be formed in the gaps between the interconnects.

[0143] The micro LED chip includes a plurality of micro LED arrays, each of which includes a plurality of micro LEDs. The micro LEDs are driven by, for example, a passive matrix (PM) drive, in which the cathodes of all the micro LEDs in each array are connected to the cathode in common, and the micro LEDs with the same number in each array are connected to the corresponding anodes. Thus, the on / off and light brightness of each LED can be individually controlled by controlling the model numbers on the corresponding cathode and anode.

[0144] The insulating layer may be transparent to the light emitted from the light emitting mesa. In some embodiments, the insulating layer is made of a dielectric material such as a solid inorganic material or a plastic material. In some embodiments, the solid inorganic material includes silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or any combination thereof. In some embodiments, the plastic material includes a polymer such as SU-8, Permi Nex, benzocyclobutene (BCB), or a transparent plastic (resin) including spin-on glass (SOG), or adhesive microresist BCL-1200, or any combination thereof. In some embodiments, the insulating layer can facilitate the passage of light emitted from the light emitting mesa. In some embodiments, the insulating layer may include multiple parts, such as three embedded dielectric parts and two bonding dielectric parts. The embedded dielectric part refers to the dielectric layer surrounding each light-emitting diode structure; while the bonding dielectric part refers to the dielectric layer between two light-emitting diode structures. The embedded dielectric part and the bonding dielectric part may have the same or different compositions.

[0145] A micro-LED array 603, which includes an epitaxial layer 608. The micro-LED array 603 is formed on the driving circuit 602. The specific structure of the epitaxial layer can be found in the following description. The micro-LED array 603 is bonded to the driving circuit 602 or the substrate 601 by bonding, and the bonding method includes full-surface bonding and hybrid bonding. In some embodiments, the micro-LED array may include blue micro-LEDs. In some embodiments, the pitch of the micro-LED array, that is, the minimum center-to-center distance between the micro-LEDs, may be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on the micro-LED chip 100 may be between thousands and millions.

[0146] Each micro LED consists of the following components:

[0147] · Epitaxial layer 608, which is configured to emit light. The epitaxial layer includes a first epitaxial layer, a second epitaxial layer and a light-emitting layer arranged between the first epitaxial layer and the second epitaxial layer. The epitaxial layer 108 includes a first epitaxial layer, a light-emitting layer and a second epitaxial layer deposited in sequence, wherein the light-emitting layer includes a multi-quantum well layer and an electron blocking layer. In one embodiment of the present invention, the first epitaxial layer is an N-type GaN layer or an N-type Al GaN layer, and the second epitaxial layer is a P-type GaN layer or a P-type Al GaN layer, that is, the material of the second epitaxial layer can be a material layer of the second conductivity type containing at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer can be a material layer of the first conductivity type containing at least two or more elements of Ga, N, As, Al, In, and P. The multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / Al GaN multi-quantum well layer or an InGaAs / Al GaAs multi-quantum well layer. The electron blocking side is arranged on a first side of the light emitting layer, and the first side refers to a side along which electrons migrate out of the light emitting layer. In another embodiment of the present invention, the first epitaxial layer may also be a P-type GaN layer or a P-type AlGaN layer, and the second epitaxial layer may be an N-type GaN layer or an N-type AlGaN layer.

[0148] In one embodiment of the present invention, the first epitaxial layer (or the first type epitaxial layer) is a semiconductor material with a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first epitaxial layer may be, but is not limited to, Ga, N, As, P, In, and includes, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second epitaxial layer (or the second type epitaxial layer for short) is a semiconductor material with a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second epitaxial layer may be, but is not limited to, at least two or more elements of Ga, N, As, P, In, and Al. In addition, the first epitaxial layer may include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer may be formed on the confinement layer. In one embodiment of the present invention, the first epitaxial layer is an N-type GaN layer or an N-type Al GaN layer, and the second epitaxial layer is a P-type GaN layer or a P-type Al GaN layer, that is, the material of the second epitaxial layer can be a material layer of the second conductivity type containing at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer can be a material layer of the first conductivity type containing at least two or more elements of Ga, N, As, Al, In, and P. In another embodiment of the present invention, the first epitaxial layer can also be a P-type GaN layer or a P-type Al GaN layer, and the second epitaxial layer can be an N-type GaN layer or an N-type Al GaN layer. In an embodiment of the present invention, the light-emitting mesa is stepped or trapezoidal.

[0149] ·Cathode 611, which is electrically connected to the first epitaxial layer of epitaxial layer 603 through transparent conductive layer 609 and cathode contact portion 614 passing through passivation layer 615. Cathode 611 may also include an annular reflective electrode 612, which is arranged around epitaxial layer 608, which may be formed by magnetron sputtering or evaporation, and its material may be, for example, Al or Al alloy metal as a side wall reflective mirror, and the electrode stack metal may be Ni, Al, Ti, Ni, Pt, Au and other metal materials. Passivation layer 615 is arranged between transparent conductive layer 609 and epitaxial layer 608, and its function is not only to reduce current leakage at the side wall, but also to passivate side wall defects and prevent water, oxygen and the like from damaging the light-emitting table during operation. Passivation layer 615 may be deposited by using CVD process SiO 2 Material formation can also be achieved by using the ALD process to deposit Al 2 O 3 The cathode 611 may be a common cathode structure, that is, an array of micro-light emitting diodes are connected to a common cathode.

[0150] Anode 613, which is arranged at the bottom of epitaxial layer 608 to power anode 613. Anode 613 of each micro-LED of the array can be selectively connected to a signal contact (not shown). Common cathode and selective anode connection can form a passive matrix control method to control the on, off and brightness adjustment of each micro-LED. Additional layers, such as passivation layer 615, transparent conductive layer 609, cathode 611, etc., are also provided on epitaxial layer 608 and anode 613.

[0151] A microlens 601 is disposed above the light-emitting mesa 608 to shape the light emitted therefrom, such as converging or collimating. The microlens includes a lens portion 601A and a spacer portion 601B. The lens portion 601A is disposed at the outermost side, i.e., the uppermost side, and is configured to shape the light from the light-emitting mesa 608. The spacer portion 601B is disposed between the lens portion 601A and the light-emitting mesa 108 to adjust the focal position of the lens portion 601A. For example, the focal point of the lens portion 601A can be adjusted by adjusting the thickness of the spacer portion 601B and the curvature of the lens portion 601A and other parameters so that the focal point of the lens portion 601A is exactly located in the light-emitting mesa 108 of the micro-LED. The microlenses 601 correspond to the light-emitting mesa 608 one by one. Meanwhile, in the present embodiment, there is a gap between adjacent microlenses 601. The bottom of the gap is flush with the top of the light-emitting table 608 and is higher than the bottom of the light-emitting layer 101B of the light-emitting table 608, and the lens portion 601A is located above the cathode 612. The microlens 601 can be formed by multiple depositions. In the process of forming the microlens, SiO2 needs to be deposited first. 2 The film layer is then ion-etched, and the microlenses are formed on the surface of the transparent conductive layer 609 at positions corresponding to the light-emitting mesas 608 .

[0152] The microlens can be made of a variety of materials that are transparent at the wavelength emitted by a single micro-LED pixel. Examples of transparent materials used for microlenses include polymers, dielectrics, and semiconductors. In some embodiments, the dielectric material includes one or more materials, such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 260 is made of photoresist. In some embodiments, the shape of the microlens is generally hemispherical. In some embodiments, the central axis of the microlens is aligned with the central axis of a single micro-LED pixel without a lens or the two are the same. It should be understood that a complete display panel includes an array consisting of many single pixels and many microlenses. In addition, there is not necessarily a one-to-one correspondence between the microlens and the pixel light source, and there is not necessarily a one-to-one correspondence between the drive circuit (not shown) and the pixel light source. The pixel light source can also be composed of multiple separate light-emitting elements, for example, a single pixel light-emitting diode connected in parallel. In some embodiments, one microlens can cover several single light-emitting diode pixels without a lens. A single microlens has a positive optical focal length, and its position can reduce the divergence or viewing angle of the light emitted by the corresponding pixel light source. For example, the light beam emitted by the pixel light source originally has a fairly wide divergence angle. In one embodiment, the initial angle of the edge ray of the light beam relative to the vertical axis perpendicular to the substrate is greater than 60°. After the light is refracted by the microlens, the divergence angle of the new edge ray is now reduced. In one embodiment, the reduced angle is less than 30°. The microlenses in the microlens array are generally identical. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnel microlenses, and cylindrical microlenses.

[0153] A plurality of micro-LEDs constitute a micro-LED array, and a plurality of micro-LED arrays constitute a micro-LED chip. The size of each micro-LED chip does not exceed 1 cm, and the micro-LED is preferably not more than 2050 microns. The micro-LED structure is formed in the micro-LED chip in an array form, and the printing resolution is, for example, 1200DPI, 600DPI, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro-LED structure is at the nanometer level, for example, 20nm micrometer to 100 to 50nm micrometer, etc.

[0154] In some embodiments of the present invention, the micro-LED array may include a single layer of micro-LED structures. In some embodiments of the present invention, the micro-LED array may include multiple layers of vertically stacked micro-LED structures.

[0155] In some embodiments of the present invention, the micro-LED array may include blue micro-LEDs. In some embodiments of the present invention, the pitch of the micro-LED array, i.e., the minimum center-to-center distance between the micro-LEDs, may be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on a micro-LED chip may be between thousands and millions.

[0156] Although some embodiments of the present invention have been described in this application document, it will be appreciated by those skilled in the art that these embodiments are merely shown as examples. Those skilled in the art may conceive of numerous variations, alternatives, and improvements under the teachings of the present invention without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and thus cover methods and structures within the scope of these claims themselves and their equivalents.

Claims

1. An alternating bare chip wafer, comprising: substrate; a plurality of first die columns, wherein each first die column comprises a plurality of first die arranged in a column on a substrate; as well as A plurality of second bare chip columns, wherein each second bare chip column comprises a plurality of second bare chips arranged in a column on the substrate, and the first bare chip columns and the second bare chip columns are arranged alternately, wherein the structure of the first bare chip is different from the structure of the second bare chip.

2. The bare chip wafer according to claim 1, wherein the first and second bare chips are micro light emitting diode chips, and the structures of wiring stacks of driving circuits of the first and second bare chips are different. 3 . The bare chip wafer according to claim 2 , wherein the first chip has a first wiring stackup and the second chip has a second wiring stackup, wherein the first wiring stackup and the second wiring stackup are complementary to each other.

4. The bare chip wafer according to claim 3, wherein: The first wiring stack includes a first insulating layer and a first metal layer; as well as The second wiring stack includes a second insulating layer and a second metal layer, wherein the first insulating layer and the second metal layer are in the same layer, and the first metal layer and the second metal layer are in the same layer.

5. The bare chip wafer according to claim 3, wherein the first and / or second bare chips have: a cathode contact portion located on an upper side of the bare chip and configured to electrically connect a cathode of the bare chip; an anode contact portion located at the upper and lower sides of the bare chip and configured to electrically connect the anode of the bare chip; and The test contact portion is located on the left or right side or both sides of the bare chip and is configured to electrically connect the test port of the bare chip.

6. The bare chip wafer according to claim 3, wherein the first and / or second bare chips have: A distinguishing mark is disposed on the surface of the bare chip to distinguish the first and second bare chips.

7. The bare chip wafer according to claim 6, wherein the distinguishing mark comprises one or more of the following: Notches, pits, grooves. 8 . The bare chip wafer according to claim 7 , wherein the notch is a triangular, square, rectangular, trapezoidal, semicircular, polygonal, or irregular notch at the edge of the bare chip.

9. The bare chip wafer according to claim 6, wherein the distinguishing marks of the first bare chip and the second bare chip have different shapes, and the distinguishing marks have a reflective layer, which is configured to reflect light falling thereon to form reflected light, and the reflected light can be identified by a machine as the first or second bare chip. 10 . The bare chip wafer according to claim 9 , wherein one of the first and second bare chips is provided with the distinguishing mark, and the reflective layer is a metal layer.

11. The bare chip wafer according to claim 1, wherein: A spacing between a first bare chip column and an adjacent second bare chip column is 50 to 500 μm; and / or The spacing between adjacent first bare chips is 50 to 500 μm; and / or The interval between adjacent second bare chips is 50 to 500 μm.

12. The bare die wafer of claim 1, wherein the first bare die has a first size and the second bare die has a second size, wherein the first size is equal to the second size.

13. The bare chip wafer according to claim 1, wherein the first bare chip has a first size and the second bare chip has a second size, wherein the first size is larger than the second size, and the second size is determined so that a first wafer area occupied by edge bare chips of the bare chip wafer is smaller than a second wafer area occupied by edge bare chips of the bare chip wafer when only the first bare chip is arranged.

14. The bare chip wafer according to claim 13, wherein: The second size is determined so that one or both of the two bare chip columns arranged at the outermost edge of the bare chip wafer are second bare chip columns; or The first and second die are arranged such that one or both of the two die columns arranged at the outermost edge of the die wafer are the second die column.

15. The bare chip wafer according to any one of claims 12 to 14, wherein the dimensions include: Length and width.

16. The bare chip wafer according to claim 2, wherein the first bare chip and the second bare chip have: Same or different light emitting areas; and / or Same or different drive circuits.

17. The bare chip wafer according to claim 16, wherein the light emitting diode chip comprises: A driving circuit, a metal layer is provided on the surface of the driving circuit, a plurality of IC copper pillars are provided on the driving circuit, the IC copper pillars are electrically connected to the metal layer, the micro-LED array area is bonded to the driving circuit through a bottom conductive bonding layer, wherein the driving circuit further has a wiring stack under the metal layer, which is configured to lead out a first electrode; Light-emitting mesas, each light-emitting mesas corresponding to an IC copper column, and the light-emitting mesas include a first epitaxial layer, a light-emitting layer and a second epitaxial layer deposited in sequence; at least one first electrode electrically connected to the IC copper pillar; A passivation isolation layer covering the surface of the light-emitting mesa but exposing at least a portion of the second epitaxial layer; a transparent conductive layer, which is disposed on the surface of the passivation isolation layer and is in electrical contact with the first epitaxial layer; as well as The second electrode is disposed on the surface of the transparent conductive layer. The bare chip wafer according to claim 17 , wherein the second electrode is located between adjacent light emitting mesas. The bare chip wafer of claim 18 , wherein the second electrode surrounds each light emitting mesa.

20. The bare chip wafer of claim 17, wherein the second electrode has a polarity opposite to that of the first electrode.

21. The bare chip wafer according to claim 17, wherein the material of the second epitaxial layer is a material layer of a second conductive type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of a first conductive type comprising at least two or more elements of Ga, N, As, Al, In, and P, wherein the first conductive type is different from the second conductive type.

22. The bare chip wafer according to claim 17, wherein the light emitting layer comprises a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, an InGaAs / AlGaAs multi-quantum well layer, or an AlGaInP multi-quantum well layer. 23 . The bare chip wafer according to claim 17 , wherein an electron blocking layer is disposed on a first side of the light emitting layer, the first side being a side along which electrons migrate out of the light emitting layer.

24. The bare chip wafer according to claim 17, wherein the material of the passivation layer is Si3N4 film, SiO2 film or Al2O3 film.

25. The bare chip wafer according to claim 1, wherein the material of the substrate is selected from the group consisting of silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), gallium nitride (GaN), glass, aluminum nitride (AlN), sapphire (α-Al2O3), and germanium (Ge).

26. The bare chip wafer according to claim 4, wherein: The material of the first and / or second insulating layer is selected from the group consisting of silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or any combination thereof; and / or The material of the first and / or second metal layer is selected from the group consisting of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), gold (Au), nickel (Ni), platinum (Pt), tantalum (Ta), and molybdenum (Mo).

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