Method for manufacturing display device

Abstract

The invention relates to a manufacturing method of a display device. In general, according to an embodiment, a method of manufacturing a display device includes: forming a lower electrode; forming an insulating layer on the lower electrode; forming a partition wall including a lower portion disposed above the insulating layer and an upper portion having an end portion protruding from a side surface of the lower portion; disposing a resist covering the partition walls on the insulating layer; forming a rib portion and a pixel opening surrounded by the rib portion by removing a portion of the insulating layer exposed from the resist by etching; forming an organic layer covering the lower electrode through the pixel opening and emitting light in response to application of a voltage; and forming an upper electrode covering the organic layer, the end portion of the upper portion being exposed from the resist during the etching.

Description

[0001] Cross-references to related applications

[0002] This application claims the priority based on Japanese Patent Application No. 2023-193014 filed on November 13, 2023, and cites all the contents described in the Japanese Patent Application. Technical Field

[0003] An embodiment of the present invention relates to a method for manufacturing a display device. Background Art

[0004] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put into practical use. In such display devices, a technology capable of improving the yield is required. Summary of the invention

[0005] Generally speaking, according to an embodiment, a method for manufacturing a display device includes: forming a lower electrode; forming an insulating layer on the lower electrode; forming a partition wall, the partition wall including a lower portion arranged above the insulating layer and an upper portion having an end protruding from a side surface of the lower portion; configuring a resist covering the partition wall on the insulating layer; removing a portion of the insulating layer exposed from the resist by etching, thereby forming a rib and a pixel opening surrounded by the rib; forming an organic layer that covers the lower electrode through the pixel opening and emits light in response to the application of a voltage; and forming an upper electrode covering the organic layer, wherein the end of the upper portion is exposed from the resist in the middle of the etching.

[0006] According to the embodiment, a method for manufacturing a display device capable of improving yield can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a diagram showing a configuration example of a display device according to an embodiment.

[0008] Figure 2 It is a schematic plan view showing an example of the layout of sub-pixels.

[0009] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device taken along line III-III in FIG.

[0010] Figure 4 This is a diagram showing an example of a layer structure that can be applied to an organic layer.

[0011] Figure 5 This is a schematic cross-sectional view showing an example of a structure that can be applied to the partition wall.

[0012] Figure 6It is a schematic cross-sectional view showing a manufacturing process of the display device according to the present embodiment.

[0013] Figure 7 It means next Figure 6 A schematic cross-sectional view of the process.

[0014] Fig. 8A It means next Figure 7 A schematic cross-sectional view of the process.

[0015] Figure 8B It means next Fig. 8A A schematic cross-sectional view of the process.

[0016] Figure 8C It means next Figure 8B A schematic cross-sectional view of the process.

[0017] Fig.8D It means next Figure 8C A schematic cross-sectional view of the process.

[0018] Fig. 9 It means next Fig.8D A schematic cross-sectional view of the process.

[0019] Fig.10 It means next Fig. 9 A schematic cross-sectional view of the process.

[0020] Fig.11 It means next Fig.10 A schematic cross-sectional view of the process.

[0021] Fig.12 It means next Fig.11 A schematic cross-sectional view of the process.

[0022] Fig.13 It means next Fig.12 A schematic cross-sectional view of the process.

[0023] Fig.14 It means next Fig.13 A schematic cross-sectional view of the process.

[0024] Fig.15 It means next Fig.14 A schematic cross-sectional view of the process. DETAILED DESCRIPTION

[0025] Several embodiments are described with reference to the accompanying drawings.

[0026] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the gist of the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown compared with the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference numerals are marked for the constituent elements that have the same or similar functions as the constituent elements described in the figures that have appeared, and sometimes repeated detailed descriptions are appropriately omitted.

[0027] It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis and Z-axis are recorded as needed for easy understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. The third direction Z is the normal direction of the plane including the first direction X and the second direction Y. In addition, the method of observing various elements parallel to the third direction Z is called top view.

[0028] The display device involved in each embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, vehicle-mounted equipment, tablet terminals, smartphones, portable telephone terminals, and wearable terminals.

[0029] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to an embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 includes a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0030] In the present embodiment, the shape of the substrate 10 in plan view is a rectangle, but the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0031] The display area DA includes a plurality of pixels PX arranged in a matrix along the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may also include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3 or instead of any of the sub-pixels SP1, SP2, and SP3.

[0032] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0033] In the display area DA, a plurality of scanning lines GL for supplying scanning signals to the pixel circuits 1 of the sub-pixels SP, a plurality of signal lines SL for supplying video signals to the pixel circuits 1 of the sub-pixels SP, and a plurality of power supply lines PL are arranged. Figure 1 In the example of FIG. 8 , the scan line GL and the power line PL extend along the first direction X, and the signal line SL extends along the second direction Y.

[0034] The gate electrode of the pixel switch 2 is connected to the scanning line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the driving transistor 3 and the capacitor 4. The source electrode of the driving transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the driving transistor 3 is connected to the display element DE.

[0035] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0036] Figure 2 1 is a schematic top view showing an example of the layout of sub-pixels SP1, SP2, and SP3. Figure 2 In the example of FIG. 1 , the sub-pixels SP2 and SP3 are arranged along the first direction X with the sub-pixel SP1 . Furthermore, the sub-pixel SP2 and the sub-pixel SP3 are arranged along the second direction Y.

[0037] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, the display area DA includes columns in which the sub-pixels SP2 and SP3 are alternately arranged along the second direction Y, and columns in which a plurality of sub-pixels SP1 are repeatedly arranged along the second direction Y. These columns are alternately arranged in the first direction X. It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 .

[0038] The rib 5 is disposed in the display area DA. The rib 5 has pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1 has the largest opening ratio, and the sub-pixel SP3 has the smallest opening ratio. It should be noted that the sizes of the pixel openings AP1, AP2, and AP3 are not limited to this example. For example, the pixel openings AP2 and AP3 may also have the same size.

[0039] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 respectively overlapping with the pixel opening AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping with the pixel opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping with the pixel opening AP3.

[0040] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may also include a cover layer described later. The ribs 5 surround the above-mentioned display elements DE1, DE2, and DE3, respectively.

[0041] The partition wall 6 is disposed in the display area DA. The partition wall 6 is located above the rib 5 and overlaps with the rib 5 as a whole. Figure 2 In the example of FIG. 1 , the partition wall 6 has the same top view shape as the rib 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another point of view, the rib 5 and the partition wall 6 are lattice-shaped when viewed from above, and surround the display elements DE1, DE2, and DE3, respectively. The partition wall 6 has the function of serving as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0042] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP along the III-III line in FIG. A circuit layer 11 is arranged on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an organic insulating layer 12 , and the organic insulating layer 12 functions as a planarizing film that planarizes the unevenness generated in the circuit layer 11 .

[0043] The lower electrodes LE1, LE2, and LE3 are arranged on the organic insulating layer 12. The ribs 5 are arranged on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5. Figure 3 Although not shown in the cross section, the lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit 1 ( Figure 1The drain electrode of the driving transistor 3 shown is connected.

[0044] The partition wall 6 includes a conductive lower portion 61 disposed on the rib 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Thus, both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever shape.

[0045] exist Figure 3 In the example of FIG. 5 , the lower portion 61 has a bottom layer 63 and a shaft layer 64. The bottom layer 63 is located between the shaft layer 64 and the rib 5 and is formed to be thinner than the shaft layer 64. Figure 3 In the example of , both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64. In addition, the ends of the bottom layer 63 are located between the ends of the upper portion 62 and the side surfaces of the shaft layer 64 in a plan view.

[0046] exist Figure 3 In the example of FIG. 6 , the upper portion 62 has a first top layer 65 and a second top layer 66 . The first top layer 65 is arranged on the shaft layer 64 of the lower portion 61 . The second top layer 66 is arranged on the first top layer 65 .

[0047] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3. The upper electrodes UE1, UE2, UE3 are in contact with the side of the lower portion 61 of the partition wall 6.

[0048] The display element DE1 includes a cover layer CP1 covering the upper electrode UE1. The display element DE2 includes a cover layer CP2 covering the upper electrode UE2. The display element DE3 includes a cover layer CP3 covering the upper electrode UE3. The cover layers CP1, CP2, and CP3 respectively have the function of serving as optical adjustment layers to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3.

[0049] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0050] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 located around the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL2 located around the partition wall 6 (the portion constituting the display element DE2). In addition, a portion of the laminate film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL3 located around the partition wall 6 (the portion constituting the display element DE3).

[0051] Seal layers SE11, SE12, and SE13 covering laminate films FL1, FL2, and FL3 are provided in sub-pixels SP1, SP2, and SP3, respectively. Specifically, seal layer SE11 continuously covers cap layer CP1 and partition wall 6 around sub-pixel SP1. Seal layer SE12 continuously covers cap layer CP2 and partition wall 6 around sub-pixel SP2. Seal layer SE13 continuously covers cap layer CP3 and partition wall 6 around sub-pixel SP3.

[0052] exist Figure 3 In the example of FIG. 1 , the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6.

[0053] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least in the entire display area DA, and part of them also extend to the peripheral area SA.

[0054] A cover member such as a polarizing plate, a protective film or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0055] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiON). In one example, the rib 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0056] The lower electrodes LE1, LE2, and LE3 have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed of a metal material having excellent light reflectivity, such as silver. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0057] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0058] The bottom layer 63 and the axial layer 64 of the next wall 6 are formed of, for example, a metal material. As the metal material of the bottom layer 63, for example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW) or molybdenum-niobium alloy (MoNb) can be used. As the metal material of the axial layer 64, for example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY) or aluminum-silicon alloy (AlSi) can be used. It should be noted that at least one of the bottom layer 63 and the axial layer 64 may also have a stacked structure of multiple layers. In addition, the axial layer 64 may also include a layer formed by an insulating material.

[0059] For example, the first top layer 65 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. As the metal material forming the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 66, for example, ITO, IZO, or IGZO can be used. It should be noted that the upper portion 62 may also have a single-layer structure of a metal material. In addition, the upper portion 62 may also include a layer formed of an insulating material.

[0060] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 respectively in contact with the side surface of the lower portion 61. The pixel circuits 1 of the sub-pixels SP1, SP2, SP3 supply pixel voltages corresponding to the video signals of the signal lines SL to the lower electrodes LE1, LE2, LE3 respectively.

[0061] Figure 4: is a diagram showing an example of a layer structure applicable to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer EML. In the present embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are sequentially stacked along a third direction Z. However, the organic layers OR1, OR2, and OR3 may also have other structures such as a so-called series structure including a plurality of light-emitting layers EML.

[0062] The cover layers CP1, CP2, and CP3 have a stacked structure formed by overlapping multiple transparent layers. These transparent layers may include layers formed by inorganic materials and layers formed by organic materials. In addition, these transparent layers have different refractive indices from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the cover layers CP1, CP2, and CP3 may also be omitted.

[0063] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in a blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in a green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in a red wavelength range.

[0064] As another example, the light-emitting layers EML of the organic layers OR1, OR2, and OR3 may also emit light of the same color (for example, white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer EML into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer EML to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0065] Figure 5 1 is a schematic cross-sectional view showing an example of a structure that can be applied to the partition wall 6. Figure 5 In the example, the portion of the partition wall 6 located between the sub-pixels SP1 and SP2 is shown. The same method can also be applied to the portion of the partition wall 6 located between the sub-pixels SP1 and SP3 and the portion located between the sub-pixels SP2 and SP3. Figure 5 Same composition.

[0066] The upper portion 62 has an end E11 on the sub-pixel SP1 side and an end E12 on the sub-pixel SP2 side. The first top layer 65 has a lower surface L1. The second top layer 66 has an upper surface U1. The axial layer 64 has a side surface F21 on the sub-pixel SP1 side and a side surface F22 on the sub-pixel SP2 side. The bottom layer 63 has an end E31 on the sub-pixel SP1 side, an end E32 on the sub-pixel SP2 side, and an upper surface U3.

[0067] exist Figure 5 In the example, the end E11 of the upper portion 62 protrudes from the end E31 of the bottom layer 63 and the side F21 of the shaft layer 64. Similarly, the end E12 of the upper portion 62 protrudes from the end E32 of the bottom layer 63 and the side F22 of the shaft layer 64. In addition, the end E31 of the bottom layer 63 protrudes from the side F21 of the shaft layer 64. Similarly, the end E32 of the bottom layer 63 protrudes from the side F22 of the shaft layer 64. It should be noted that in Figure 5 In the example of FIG. 1 , the width of the second top layer 66 is the same as that of the first top layer 65 , but the width of the second top layer 66 may be smaller than that of the first top layer 65 . The shaft layer 64 is formed thicker than the bottom layer 63 , the first top layer 65 , and the second top layer 66 .

[0068] The rib 5 includes a first portion 51 and second portions 521 and 522. The first portion 51 is a portion of the rib 5 with a constant thickness. The "constant" here includes not only the case where the thickness of the rib 5 corresponding to the position in the XY plane does not change at all, but also the case where there is a slight change that is not intentionally formed. In one example, the first portion 51 is equivalent to the thickness of the rib 5 corresponding to the position in the XY plane. FIG. 8A to FIG. 8D The area not exposed to etching described later. The second portion 521 is a portion of the rib 5 whose thickness decreases toward the pixel opening AP1. The second portion 522 is a portion of the rib 5 whose thickness decreases toward the pixel opening AP2. The first portion 51 is located between the second portions 521 and 522.

[0069] exist Figure 5 In the example of FIG. 5 , the boundary B1 between the first portion 51 and the second portion 521 coincides with the end E11 of the upper portion 62 in a plan view. In addition, the boundary B2 between the first portion 51 and the second portion 522 coincides with the end E12 of the upper portion 62 in a plan view. As another example, the boundary B1 and the end E11 may be offset. In addition, the boundary B2 and the end E12 may be offset.

[0070] The first portion 51 has an upper surface U5. The second portion 521 has an inclined surface 531 inclined from the boundary B1 toward the pixel opening AP1. The second portion 522 has an inclined surface 532 inclined from the boundary B2 toward the pixel opening AP2. The lower electrode LE1 has an upper surface Uc1 and an end Ec1. The lower electrode LE2 has an upper surface Uc2 and an end Ec2. The end Ec1 and Ec2 overlap with the partition wall 6 when viewed from above. Specifically, the end Ec1 and Ec2 overlap with the shaft layer 64 when viewed from above.

[0071] like Figure 5 As shown, the upper surface U5 of the rib 5 has a step portion ST caused by the ends Ec1 and Ec2 of the lower electrodes LE1 and LE2. In this embodiment, these step portions ST are covered by the bottom layer 63 and the shaft layer 64. Figure 5 As shown, the upper surfaces of the shaft layer 64, the first top layer 65, and the second top layer 66 may also be deformed in accordance with the step portion ST.

[0072] exist Figure 5 In the example, the angle θ1 formed by the inclined surface 531 and the upper surface Uc1 of the lower electrode LE1 is equal to the angle θ2 formed by the inclined surface 532 and the upper surface Uc2 of the lower electrode LE2 (θ1=θ2). However, the angles θ1 and θ2 may be different. In one example, the angles θ1 and θ2 are less than 50°.

[0073] like Figure 5 As shown, regions AR1 and AR2 are formed below the upper portion 62. Regions AR1 and AR2 are regions surrounded by the lower surface of the upper portion 62, the side surface of the lower portion 61, and the upper surface of the rib 5. Specifically, region AR1 is surrounded by the lower surface L1 of the first top layer 65, the side surface F21 of the shaft layer 64, the upper surface U3 of the bottom layer 63, the end E31 of the bottom layer 63, and the upper surface U5 of the first portion 51. In addition, region AR2 is surrounded by the lower surface L1 of the first top layer 65, the side surface F22 of the shaft layer 64, the upper surface U3 of the bottom layer 63, the end E32 of the bottom layer 63, and the upper surface U5 of the first portion 51.

[0074] Next, an example of a method for manufacturing the display device DSP according to the present embodiment will be described. Figures 6 to 15 1 and 12 are schematic cross-sectional views showing the manufacturing process of the display device DSP according to the present embodiment. In these drawings, the substrate 10 and the circuit layer 11 are omitted. Figure 6 , Figure 7 and Figures 9 to 15 In the figure, the step portion ST caused by the end portion of the lower electrode is omitted.

[0075] When manufacturing the display device DSP, first, a circuit layer 11, an organic insulating layer 12, and lower electrodes LE1, LE2, and LE3 are formed on a substrate 10. Figure 6 As shown, an insulating layer L5 for being processed into ribs 5 is formed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3, a first layer L63 for being processed into a bottom layer 63 is formed on the insulating layer L5, a second layer L64 for being processed into an axis layer 64 is formed on the first layer L63, a third layer L65 for being processed into a first top layer 65 is formed on the second layer L64, and a fourth layer L66 for being processed into a second top layer 66 is formed on the third layer L65.

[0076] Next, the first layer L63, the second layer L64, the third layer L65, and the fourth layer L66 are patterned. The patterning includes a process of configuring a resist of a top view shape of the partition wall 6 on the fourth layer L66, a process of forming a second top layer 66 by etching the fourth layer L66, a process of forming a first top layer 65 by etching the third layer L65, a process of forming an axial layer 64 by etching the second layer L64, and a process of forming a bottom layer 63 by etching the first layer L63. After these processes, as shown in FIG. Figure 7 As shown in FIG. 1 , a partition wall 6 having a lower portion 61 and an upper portion 62 is formed on the insulating layer L5. Figure 5 As shown in FIG. 6A , the bottom layer 63 and the shaft layer 64 are included. Figure 5 As shown, it includes a first top layer 65 and a second top layer 66.

[0077] Next, use FIG. 8A to FIG. 8D The formation of the rib 5 is described below. FIG. 8A to FIG. 8D In the description, the portion of the insulating layer L5 and the partition wall 6 located between the lower electrodes LE1 and LE2 is described. The portion of the insulating layer L5 and the partition wall 6 located between the lower electrodes LE1 and LE3 and the portion located between the lower electrodes LE2 and LE3 are also described in the same manner. FIG. 8A to FIG. 8D The same process is formed.

[0078] First, if Fig. 8A As shown, a resist R1 covering the partition wall 6 is disposed on the insulating layer L5. The resist R1 has a lattice-like top view shape similar to the partition wall 6. For example, the resist R1 has a cross-sectional shape in which the thickness decreases as it approaches both ends. It is desirable that the size of the resist R1 is such that the end portions E11 and E12 are not exposed from the resist R1. Fig. 8A In the example of FIG. 5 , the end portions E11 and E12 of the upper portion 62 are covered with the resist R1 .

[0079] Then, if Figure 8BAs shown, the insulating layer L5 is anisotropically dry-etched using the resist R1 as a mask. FIG. 8B to FIG. 8D The double-dashed line shown in FIG. 1 shows the outer shape of the insulating layer L5 and the resist R1 before etching. In this etching, the portion of the insulating layer L5 exposed from the resist R1 is eroded. In addition, in this etching, the resist R1 is also eroded. Therefore, the width of the resist R1 gradually decreases during etching. As a result, as shown in FIG. Figure 8B As shown, inclined surfaces L51 and L52 are formed on the insulating layer L5.

[0080] In addition, since the width of the resist R1 is gradually reduced during the etching, a portion of the ends E11 and E12 of the upper portion 62 and a portion of the upper surface U1 are exposed. Therefore, the resist R1 is divided by the partition wall 6 into the resist R1a on the side of the region AR1 in the resist below the upper portion 62, the resist R1b on the side of the region AR2 in the resist below the upper portion 62, and the resist R1c on the upper portion 62. It should be noted that the second top layer 66 is formed of a conductive oxide and is less affected by the etching. Therefore, the portion of the upper surface U1 exposed from the resist R1c and the ends E11 and E12 are almost not corroded.

[0081] As etching progresses, the width of the resist R1 further decreases, as shown in FIG. Figure 8C As shown, the ends E11 and E12 of the upper portion 62 are completely exposed. In addition, the resist R1a in the area AR1 and the resist R1b in the area AR2 are located directly below the upper portion 62 in the third direction Z. Therefore, in this etching, the erosion of the resist R1a in the area AR1 and the resist R1b in the area AR2 is suppressed by the upper portion 62. On the other hand, the resist R1a outside the area AR1 and the resist R1b outside the area AR2 are eroded by the etching because they do not overlap with the upper portion 62 when viewed from above. Therefore, the end Ea aligned with the end E11 of the upper portion 62 in the third direction Z is formed at the resist R1a. Similarly, the end Eb aligned with the end E12 of the upper portion 62 in the third direction Z is formed at the resist R1b. It should be noted that in this etching, a protective film that hinders the erosion caused by the etching can also be formed at the ends Ea and Eb.

[0082] As the etching progresses further, Fig.8DAs shown, the width of the resist R1 is further reduced. As a result, the portion of the insulating layer L5 exposed from the resists R1a and R1b is removed by the etching, forming the rib 5 and the pixel openings AP1 and AP2 surrounded by the rib 5. In addition, by the etching, a first portion 51 with a constant thickness, a second portion 521 whose thickness decreases as it moves toward the pixel opening AP1, and a second portion 522 whose thickness decreases as it moves toward the pixel opening AP2 are formed in the rib 5. An inclined surface 531 is formed in the second portion 521, which is inclined from the boundary B1 between the first portion 51 and the second portion 521 toward the pixel opening AP1. Similarly, an inclined surface 532 is formed in the second portion 522, which is inclined from the boundary B2 between the first portion 51 and the second portion 522 toward the pixel opening AP2. At the time point when the rib 5 and the pixel openings AP1 and AP2 are formed, the etching is terminated. After the etching, the resist R1 is removed.

[0083] like Fig.8D As shown, at the end of the etching, resist R1a remains in region AR1, and resist R1b remains in region AR2. In addition, resist R1c remains on the upper surface U1 of the upper portion 62. In addition, the lower surface L1 of the first top layer 65 in region AR1, the side surface F21 of the shaft layer 64, the end E31 of the bottom layer 63, and the upper surface U5 of the first portion 51 in region AR1 are covered with resist R1a. Similarly, the lower surface L1 of the first top layer 65 in region AR2, the side surface F22 of the shaft layer 64, the end E32 of the bottom layer 63, and the upper surface U5 of the first portion 51 in region AR2 are covered with resist R1b. Fig.8D In the example of , the end E11 of the upper portion 62, the end Ea of the resist R1a, and the boundary B1 coincide with each other in a plan view. Similarly, the end E12 of the upper portion 62, the end Eb of the resist R1b, and the boundary B2 coincide with each other in a plan view.

[0084] After forming the rib 5, a process for forming the display elements DE1, DE2, and DE3 is performed. In this embodiment, it is assumed that the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0085] When forming the display element DE1, first Fig. 9 As shown in FIG. 1 , a laminate film FL1 and a sealing layer SE11 are formed. Figure 3 As shown, the organic layer OR1 contacts the lower electrode LE1 through the pixel opening AP1 , the upper electrode UE1 covering the organic layer OR1 , and the cover layer CP1 covering the upper electrode UE1 .

[0086] The organic layer OR1, the upper electrode UE1 and the cap layer CP1 are formed by evaporation. In addition, the sealing layer SE11 is formed by CVD (Chemical Vapor Deposition). The laminate film FL1 is partitioned into a plurality of parts by the cantilever-shaped partition wall 6. The sealing layer SE11 continuously covers the partitioned parts of the laminate film FL1 and the partition wall 6.

[0087] After forming the stacked film FL1 and the sealing layer SE11, as shown in FIG. Fig. 9 As shown in FIG. 1 , a resist R2 is disposed on the sealing layer SE11 . The resist R2 covers the sub-pixel SP1 and a part of the partition wall 6 around it.

[0088] Then, by etching using the resist R2 as a mask, Fig.10 As shown in FIG. 1 , the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist R2 are removed. Thus, the display element DE1 is formed in the sub-pixel SP1. For example, the etching includes wet etching and dry etching sequentially performed on the sealing layer SE11, the cap layer CP1, the upper electrode UE1 and the organic layer OR1. After the above etching, the resist R2 is removed.

[0089] The display element DE2 is formed in the same steps as the display element DE1. That is, when forming the display element DE2, Fig.11 As shown in FIG. 1 , a laminate film FL2 and a sealing layer SE12 are formed. Figure 3 As shown, it includes an organic layer OR2 contacting the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cover layer CP2 covering the upper electrode UE2.

[0090] The organic layer OR2, the upper electrode UE2 and the cap layer CP2 are formed by evaporation. In addition, the sealing layer SE12 is formed by CVD. The laminate film FL2 is partitioned into a plurality of parts by the cantilever-shaped partition wall 6. The sealing layer SE12 continuously covers the partitioned parts of the laminate film FL2 and the partition wall 6.

[0091] After forming the stacked film FL2 and the sealing layer SE12, as shown in FIG. Fig.11 As shown in FIG. 1 , a resist R3 is disposed on the sealing layer SE12. The resist R3 covers the sub-pixel SP2 and a part of the partition wall 6 around it.

[0092] Then, by etching using the resist R3 as a mask, Fig.12The portions of the laminated film FL2 and the sealing layer SE12 exposed from the resist R3 are removed as shown. Thus, the display element DE2 is formed in the sub-pixel SP2. For example, the etching includes wet etching and dry etching performed sequentially on the sealing layer SE12, the cover layer CP2, the upper electrode UE2 and the organic layer OR2. After the above etching, the resist R3 is removed.

[0093] The display element DE3 is formed in the same steps as the display elements DE1 and DE2. Fig.13 As shown in FIG. 1 , a laminate film FL3 and a sealing layer SE13 are formed. Figure 3 As shown, it includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cover layer CP3 covering the upper electrode UE3.

[0094] The organic layer OR3, the upper electrode UE3 and the cap layer CP3 are formed by evaporation. In addition, the sealing layer SE13 is formed by CVD. The laminate film FL3 is partitioned into a plurality of parts by the cantilever-shaped partition wall 6. The sealing layer SE13 continuously covers the partitioned parts of the laminate film FL3 and the partition wall 6.

[0095] After forming the stacked film FL3 and the sealing layer SE13, as shown in FIG. Fig.13 As shown in FIG. 1 , a resist R4 is disposed on the sealing layer SE13 . The resist R4 covers the sub-pixel SP3 and a part of the partition wall 6 around it.

[0096] Then, by etching using the resist R4 as a mask, Fig.14 The portions of the laminated film FL3 and the sealing layer SE13 exposed from the resist R4 are removed as shown. Thus, a display element DE3 is formed in the sub-pixel SP3. For example, the etching includes wet etching and dry etching sequentially performed on the sealing layer SE13, the cap layer CP3, the upper electrode UE3 and the organic layer OR3. After the above etching, the resist R3 is removed.

[0097] After forming the display elements DE1, DE2, DE3, as shown in FIG. Fig.15 As shown in FIG. 1 , the resin layer RS1 , the sealing layer SE2 , and the resin layer RS2 are sequentially formed. Through such steps, the display device DSP is completed.

[0098] In this embodiment, if FIG. 8A to FIG. 8DAs shown, the width of the resist R1 is reduced by utilizing anisotropic dry etching performed in the process of forming the rib 5 and the pixel openings AP1 and AP2, thereby exposing the ends E11 and E12 of the upper portion 62. That is, the resist R1 is partitioned by the partition 6 into the resists R1a and R1b located below the upper portion 62 and the resist R1c located above the upper portion 62. As for the portions of the resists R1a and R1b that overlap with the upper portion 62 in the third direction Z, since the etching is blocked by the upper portion 62, they are hardly corroded. Therefore, by this etching, the pixel openings AP1 and AP2 are formed in the rib 5 in such a manner that the end E11 of the upper portion 62 coincides with the boundary B1 of the first portion 51 and the second portion 521 when viewed from above, and the end E12 of the upper portion 62 coincides with the boundary B2 of the first portion 51 and the second portion 522 when viewed from above. That is, the width of the first portion 51 of the rib 5 is determined by the width of the upper portion 62. The same applies to the first portion 51 located between the pixel openings AP1 and AP3 and between the pixel openings AP2 and AP3.

[0099] On the other hand, when the amount of resist R1 applied is large, etching is completed before the resist R1 is blocked by the partition wall 6. In this case, the width of the first portion 51 of the rib 5 is determined by the width of the resist R1 at the end of etching. Therefore, there is a possibility that pixel openings of different sizes and positions are formed in each pixel due to the deviation of the amount of resist applied.

[0100] In contrast, in the present embodiment, as described above, the width of the first portion 51 of the rib 5 is determined by the width of the upper portion 62. Therefore, pixel openings having substantially the same size and position can be formed in each pixel. In addition, a larger pixel opening can be formed compared to a case where the amount of resist applied is large.

[0101] Thus, according to the manufacturing method of the display device DSP according to the present embodiment, the yield rate when manufacturing the display device DSP can be improved. In addition, according to the present embodiment, various suitable effects can be obtained.

[0102] As long as the gist of the present invention is included, all methods for manufacturing a display device that can be implemented by a person skilled in the art by appropriately changing the design based on the method for manufacturing a display device described above as an embodiment of the present invention also fall within the scope of the present invention.

[0103] Within the scope of the concept of the present invention, those skilled in the art can think of various variations, and these variations should also be understood to belong to the scope of the present invention. For example, the scheme obtained by adding, deleting or designing the above-mentioned embodiments appropriately by those skilled in the art, or the scheme obtained by adding, omitting or changing the conditions of the processes, as long as they have the gist of the present invention, is also included in the scope of the present invention.

[0104] In addition, regarding other effects brought about by the scheme described in the above-mentioned embodiment, the effects that can be clearly understood from the description of this specification or the technical effects that can be appropriately thought of by those skilled in the art should of course be understood as the effects brought about by the present invention.

Claims

1. A method for manufacturing a display device, comprising: forming a lower electrode; forming an insulating layer on the lower electrode; forming a partition wall including a lower portion disposed above the insulating layer and an upper portion having an end portion protruding from a side surface of the lower portion; disposing a resist covering the partition wall on the insulating layer; removing a portion of the insulating layer exposed from the resist by etching, thereby forming a rib portion and a pixel opening surrounded by the rib portion; forming an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; and forming an upper electrode covering the organic layer, During the etching, the end portion of the upper portion is exposed from the resist.

2. The method for manufacturing a display device according to claim 1, wherein: The width of the resist is gradually reduced by the etching.

3. The method for manufacturing a display device according to claim 1, wherein: When the etching is completed, the resist remains in a region surrounded by the lower surface of the upper portion, the side surface of the lower portion, and the upper surface of the rib portion.

4. The method for manufacturing a display device according to claim 3, wherein: When the etching is completed, the end of the upper portion coincides with an end of the resist remaining in the region in a plan view.

5. The method for manufacturing a display device according to claim 1, wherein: When the etching is completed, the resist remains on the upper surface of the upper portion.

6. The method for manufacturing a display device according to claim 1, wherein: By the etching, the rib portion including a first portion having a constant thickness and a second portion having a thickness decreasing toward the pixel opening is formed.

7. The method for manufacturing a display device according to claim 6, wherein: When the etching is completed, the end of the upper portion coincides with a boundary between the first portion and the second portion in a plan view.

8. The method for manufacturing a display device according to claim 7, wherein: The second portion has an inclined surface inclined from the boundary toward the pixel opening, An angle formed between the inclined surface and the upper surface of the lower electrode is less than 50°.

9. The method for manufacturing a display device according to claim 1, wherein: An end portion of the lower electrode overlaps with the partition wall in a plan view.

10. The method for manufacturing a display device according to claim 1, wherein: The upper portion has a first top layer disposed on the lower portion and a second top layer disposed on the first top layer, The second top layer is formed of a conductive oxide.

11. The method for manufacturing a display device according to claim 10, wherein: At the end of the etching, the lower surface of the first top layer is covered by the resist.

12. The method for manufacturing a display device according to claim 1, wherein: The lower part has a shaft layer and a bottom layer arranged between the shaft layer and the ribs, The end of the bottom layer is located between the end of the upper portion and the side surface of the shaft layer in a plan view.

13. The method for manufacturing a display device according to claim 12, wherein: An end portion of the lower electrode overlaps with the shaft layer in a plan view.

14. The method for manufacturing a display device according to claim 12, wherein: At the end of the etching, the end of the bottom layer is covered by the resist.

15. The method for manufacturing a display device according to claim 12, wherein: At the end of the etching, the side surface of the shaft layer is covered by the resist.

16. The method for manufacturing a display device according to claim 1, wherein: The etching is dry etching.

17. The method for manufacturing a display device according to claim 1, wherein: The etching is anisotropic etching.

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