Configurable flash physical interface in host device

Abstract

A flash memory physical interface in a host device may be configured based on a select signal indicating whether a flash memory system is of a first type or a second type. A first differential memory data signal input of the driver circuit or a second differential memory data signal input of the driver circuit may be coupled to a differential data input of the flash memory system based on the select signal. Based on the select signal, the differential data output of the flash memory system may be coupled to a first differential memory data signal output of the receiver circuit or a second differential memory data signal output of the receiver circuit.

Description

Background Art

[0001] Mobile computing devices such as smartphones typically include one of two types of flash memory systems as their main memory: Universal Flash Storage ("UFS") and Non-Volatile Memory Express ("NVMe"). Thus, the host processing system in some mobile computing devices may be configured to interface with UFS, while the host processing system in other mobile computing devices may be configured to interface with NVMe.

[0002] The UFS physical layer interface or link between the UFS host and the UFS storage device may conform to a protocol called M-PHY. The M-PHY interface may include six signal paths (e.g., wires or other conductors). Two of the conductors form a first differential pair that is configured to carry data from the UFS host to the UFS storage device, and two of the conductors form a second differential pair that is configured to carry data from the UFS storage device to the UFS host. The remaining two conductors may be configured to carry a clock signal and a reset signal.

[0003] The NVMe physical interface or link between the host and the NVMe storage device may conform to a protocol called Peripheral Component Interconnect Express ("PCIe"). The PCIe interface may include four signal paths (e.g., conductors). Two of the conductors form a first differential pair that is configured to carry data from the host to the NVMe storage device, and two of the conductors form a second differential pair that is configured to carry data from the NVMe storage device to the host.

[0004] A host device, such as a system on a chip ("SoC"), may include only one of the above types of physical interfaces, depending on the computing device the SoC is included in. For example, a first smartphone may include UFS as its flash memory and accordingly include a SoC with an M-PHY flash physical interface, while a second smartphone may include NVMe as its flash memory and accordingly include a SoC with a PCIe flash physical interface. Summary of the invention

[0005] Systems, methods, computer-readable media, and other examples for configuring a flash memory physical interface in a host device are disclosed.

[0006] An exemplary system for selectively configuring a flash memory physical interface may include a driver circuit and a receiver (buffer) circuit. The driver circuit may have a first differential memory data signal input and a second differential memory data signal input. The driver circuit may also have a driver selector input configured to receive a selection signal indicating one of a first flash memory type and a second flash memory type. The driver circuit may be configured to couple a selected one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of a flash memory system based on the selection signal. The receiver circuit may be coupled to a differential data output of the flash memory system. The receiver circuit may have a receiver selector input configured to receive a selection signal. The receiver circuit may also have a first differential memory data signal output and a second differential memory data signal output. The receiver circuit may be configured to couple a differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on the selection signal.

[0007] An exemplary method for selectively configuring a flash memory physical interface may include providing a selection signal indicating a selected one of a first flash memory type and a second flash memory type. The method may also include coupling, by a driver circuit, one of a first differential memory data signal input and a second differential memory data signal input to a differential data input of a flash memory system based on the selection signal. The method may also include coupling, by a receiver circuit, a differential data output of the flash memory system to a selected one of a first differential memory data signal output and a second differential memory data signal output based on the selection signal.

[0008] Another exemplary system for selectively configuring a flash memory physical interface may include: means for providing a selection signal indicating a selected one of a first flash memory type and a second flash memory type. The exemplary system may also include: means for coupling one of a first differential memory data signal input and a second differential memory data signal input to a differential data input of a flash memory system based on the selection signal. The exemplary system may also include: means for coupling a differential data output of the flash memory system to a selected one of a first differential memory data signal output and a second differential memory data signal output based on the selection signal.

[0009] An exemplary system on chip or "SoC" may include a processing system configured to direct memory transactions to a flash memory system, memory type selection logic, and flash memory physical interface configuration logic. The memory type selection logic may be configured to provide a selection signal indicating whether the flash memory system is a first flash memory type or a second flash memory type. The flash memory physical interface configuration logic may include a driver circuit and a receiver (buffer) circuit. The driver circuit may have a first differential memory data signal input and a second differential memory data signal input. The driver circuit may have a driver selector input configured to receive a selection signal. The driver circuit may be configured to couple a selected one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of the flash memory system based on the selection signal. The receiver circuit may be coupled to a differential data output of the flash memory system. The receiver circuit may have a receiver selector input configured to receive a selection signal. The receiver circuit may have a first differential memory data signal output and a second differential memory data signal output. The receiver circuit may be configured to couple a selected one of the first differential memory data signal output and the second differential memory data signal output to a differential data output of the flash memory system based on the selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with alphabetic characters, such as "101A" or "101B", the alphabetic characters may distinguish between two similar parts or elements in the same figure. When it is intended that a reference numeral encompass all parts having the same reference numeral in all figures, the alphabetic characters of the reference numeral may be omitted.

[0011] Figure 1 is a block diagram of a system for selectively configuring a flash memory physical interface according to an exemplary embodiment.

[0012] Figure 2 is a block diagram of flash memory physical interface configuration logic and a configurable impedance matching network according to an exemplary embodiment.

[0013] Figure 3 is a block diagram of the transmit or TX portion of the flash physical interface configuration logic according to an exemplary embodiment.

[0014] Figure 4 is a block diagram of an example of a driver circuit according to an exemplary embodiment.

[0015] Figure 5 is a block diagram of another example of a driver circuit according to an exemplary embodiment.

[0016] Figure 6is a block diagram of the receive or RX portion of the flash physical interface configuration logic according to an exemplary embodiment.

[0017] Figure 7 is a block diagram of an example of a receiver or buffer circuit according to an exemplary embodiment.

[0018] Figure 8 is a block diagram of another example of a receiver or buffer circuit according to an exemplary embodiment.

[0019] Fig. 9 is a block diagram of configurable TX and RX impedance networks according to an exemplary embodiment.

[0020] Fig.10 is a block diagram of a configurable clock circuit according to an exemplary embodiment.

[0021] Fig.11 is a flow chart illustrating a method for selectively configuring a flash memory physical interface according to an exemplary embodiment.

[0022] Fig.12 is a block diagram of a portable computing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0023] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "illustrative" may be used synonymously with "exemplary" herein. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] like Figure 1 As shown, in an illustrative or exemplary embodiment, system 100 may include a host device 102 and a flash memory device or system 104. Host device 102 may be, for example, a system on a chip ("SoC"). Flash memory system 104 may be coupled to the SoC. Figure 1 1 and 10. Although not shown for clarity in FIG. 1 , host device 102 and flash memory system 104 may be included in a computing device such as a mobile computing device. In an exemplary embodiment, flash memory system 104 may include one of two types of flash memory: Universal Flash Memory ("UFS") and Non-Volatile Memory Express ("NVMe").

[0025] The term "UFS" is used herein to refer to a series of storage access and transmission protocols promulgated by the industry consortium JEDEC. An example of such a protocol is UFS version 4.0 (published as JESD220F UFS 4.0). As understood by those of ordinary skill in the art, UFS may use a UFS physical layer interface known as M-PHY. The UFS version 4.0 protocol may incorporate or reference protocols promulgated by the Mobile Industry Processor Interface ("MIPI") Alliance. For example, UFS version 4.0 references the MIPI M-PHY v5.0 physical layer specification and the MIPI UNIPRO v2.0 transport layer specification.

[0026] The term "NVMe" is used herein to refer to a series of storage access and transmission protocols for flash memory and solid-state storage drives promulgated by the industry consortium NVMe Working Group. As understood by those of ordinary skill in the art, the NVMe protocol accesses flash memory via a peripheral component interconnect express ("PCIe") bus. The host device 102 may include UFS, M-PHY, NVMe, PCIe, etc., which are related to the communication between the host device 102 and the flash memory system 104. Because such features are well understood by those of ordinary skill in the art, they are not described herein.

[0027] Regardless of whether the flash memory system 104 is UFS or NVMe, the signal path of the physical interface that couples the flash memory system 104 to the host device 102 may include: a differential data output signal path 106, which is configured to carry a true output data signal Dout_t and a complementary output data signal Dout_c, respectively; and a differential data input signal path 108, which is configured to carry a true input data signal Din_t and a complementary input data signal Din_c, respectively. The host device 102 can send data to the differential data input of the flash memory system 104 on the differential data output signal path 106, and receive data from the differential data signal output of the flash memory system 104 on the differential data input signal path 108.

[0028] The host device 102 may include a flash memory interface configuration logic 110. The flash memory interface configuration logic 110 may have a first data input configured to receive a PCIe data output signal 112 ("PCIe Data Out") and a second data input configured to receive an M-PHY data output signal 114 ("M-PHY Data Out"). The configuration logic 110 may also have a first data output configured to provide a PCIe data input signal 116 (also referred to as "PCIe Data In") and a second data output configured to provide an M-PHY data input signal 118 ("M-PHY Data In"). The PCIe Data Out signal and the M-PHY Data Out signal are configured to provide data that the host device 102 is sending to the flash memory 104 (i.e., leaving the host device 102). The PCIe Data In signal path and the M-PHY Data In signal path are configured to receive data from the flash memory 104 (i.e., entering the host device 102). Although the term "data" is used herein for convenience, it should be understood that the "data" transferred between the host device 102 and the flash memory system 104 may include any type of information.

[0029] The host device 102 may also include memory type selection logic 120. The memory type selection logic 120 may be configured to provide a selection signal 122 ("Select") to the flash interface configuration logic 110. The selection signal 122 may indicate whether the flash memory 104 is UFS or NVMe. The memory type selection logic 120 may have any of a variety of structures (not shown for clarity). In one example, the memory type selection logic 120 may include a SoC pin hardwired to a voltage, wherein a first voltage level (e.g., ground) may indicate UFS, and a second voltage level (e.g., a positive voltage) may indicate NVMe. In another example, the memory type selection logic 120 may include an impedance, wherein a first impedance level may indicate UFS, and a second impedance level may indicate NVMe. In yet another example, the memory type selection logic 120 may include a fuse connector (fuse or eFuse), wherein a fuse state (i.e., intact or blown) may indicate UFS or NVMe. In yet another example, the memory type selection logic 120 may include a register that may be loaded by a processor with a bit value indicating UFS or NVMe. The memory type selection logic 120 may include a detector circuit that detects voltage, impedance, fuse state, bit value, etc., and generates a selection signal 122 based on the detection result.

[0030] The signal path that couples the flash memory system 104 to the physical interface of the host device 102 may also include a reference clock signal path 124 and a reset signal path 126. The flash memory 104 may utilize a reference clock signal received on the reference clock signal path 124. The flash memory 104 may utilize a reset signal received on the reset signal path 126. The host device 102 may include a configurable clock circuit 128. The configurable clock circuit 128 may be configurable based on the select signal 122.

[0031] like Figure 2 As shown, the system 200 may include a flash memory interface configuration logic 202. The flash memory interface configuration logic 202 may be the flash memory interface configuration logic 102 ( Figure 1 ). Flash interface configuration logic 202 may include transmit (“TX”) interface configuration logic 204 and receive (“RX”) interface configuration logic 206.

[0032] TX interface configuration logic 204 may have a first data input configured to receive a PCIe data output signal 212 (“PCIe Data Out”) and a second data input configured to receive an M-PHY data output signal 214 (“M-PHY Data Out”). RX interface configuration logic 206 may have a first data output configured to provide a PCIe data input signal 216 (“PCIe Data In”) and a second data output configured to provide an M-PHY data input signal 218 (“M-PHY Data In”). TX interface configuration logic 204 and RX interface configuration logic 206 may each receive a select signal 222.

[0033] The data output of the TX interface configuration logic 204 can be coupled to the TX impedance matching network 208. The impedance coupled by the TX impedance matching network 208 can be controlled or selected based on the selection signal 222. Similarly, the data input of the RX interface configuration logic 206 can be coupled to the RX impedance matching network 210. The impedance coupled by the RX impedance matching network 210 can be controlled or selected based on the selection signal 222. The TX impedance matching network 208 can thus couple a configurable or selectable impedance to the flash interface configuration logic 202 and the flash memory ( Figure 2 Similarly, the RX impedance matching network 210 can couple a configurable or selectable impedance to the flash interface configuration logic 202 and the flash memory (not shown). Figure 2 ) between the differential data input signal path 226.

[0034] exist Figure 3 , a TX interface configuration logic 300 is shown. The TX interface configuration logic 300 may be the above-mentioned TX interface configuration logic 204 ( Figure 2). The TX interface configuration logic 300 may include encoding logic 302, a serializer 304, a multi-level signaling formatter 306, and a driver circuit 308, each of which may have a selector input configured to receive a select signal 310.

[0035] The encoding logic 302 may be configured to receive the PCIe data output signal 312 and the M-PHY data output signal 314. For example, the PCIe data output signal 312 and the M-PHY data output signal 314 may be received from a processing unit (not shown). Such a processing unit may include a processor, such as a central processing unit ("CPU"), an application processor ("AP"), a graphics processing unit ("GPU"), or other processor that may initiate or control memory transactions. Such a processor may be configured to provide PCIe data (i.e., PCIe data output signal 312) to the encoding logic 302 via a PCIe bus, and similarly provide M-PHY data (i.e., M-PHY data output signal 314) via the bus. Alternatively, such a processing unit may be an intermediate component (not shown), such as a peripheral interface block, which receives data from a processor via a bus or other data interconnect. Such a peripheral block may include a processor, a finite state machine, or specific hardware, etc. The peripheral block may format the data received from the processor into a PCIe or M-PHY format. The peripheral blocks may be configured to provide PCIe data to the encoding logic 302 via a PCIe bus, and similarly provide M-PHY data via the bus.

[0036] The encoding logic 302 may include PCIe specific encoding logic 316, M-PHY specific encoding logic 318, and common (for both PCIe and M-PHY) encoding logic 320. The encoding logic 302 encodes PCIe output data and M-PHY output data according to the PCIe and M-PHY protocols, respectively. Since such encoding logic 316-320 is well understood by those of ordinary skill in the art, these elements are not described in further detail herein.

[0037] The encoding logic 302 may provide the encoded output data to the serializer 304, which may convert the encoded output data from a parallel format to a serial format. The serializer 304 may provide the resulting serial format data to the multi-level signaling formatter 306. The multi-level signaling formatter 306 may convert its input signal from a serial format to a pulse width modulation ("PWM"), a pulse amplitude modulation ("PAM") (such as PAM-3, PAM-4, etc.), or any combination thereof. The multi-level signaling formatter 306 may provide a PCIe differential data output signal (including a true signal PCIe Dout_t and a complementary signal PCIe Dout_c, respectively) and an M-PHY differential data output signal (including a true signal M-PHY Dout-t and a complementary signal M-PHY Dout_c, respectively) to the driver circuit 308. As described below, the driver circuit 308 may provide a differential data output signal 322 selected from a PCIe differential memory data signal or an M-PHY differential memory signal based on a selection signal 310.

[0038] exist Figure 4 , a driver circuit 400 is shown. The driver circuit 400 may be the driver circuit 308 ( Figure 3 ). The driver circuit 400 may include a first three-state differential driver 402 and a second three-state differential driver 404. The first three-state differential driver 402 may receive a PCIe differential data output signal 406, and the second three-state differential driver 404 may receive an M-PHY differential data input signal 408. The outputs of the first three-state differential driver 402 and the second three-state differential driver 404 are coupled together to provide a differential data output including Dout_t and Dout_c signals. The first three-state differential driver 402 and the second three-state differential driver 404 may operate in a complementary manner relative to each other in response to the selection signal 410. That is, when the selection signal 410 indicates that the memory is NVMe (i.e., the physical interface protocol is PCIe), the second three-state differential driver 404 drives its output to a high impedance, and the first three-state differential driver 402 drives its output to provide a PCIe differential data output signal. Conversely, when the select signal 410 indicates that the memory is UFS (ie, the physical interface protocol is M-PHY), the first tri-state differential driver 402 drives its output to high impedance and the second tri-state differential driver 404 drives its output to provide an M-PHY differential data output signal.

[0039] Drivers 402 and 404 may drive respective signals using respective voltage levels. A first voltage level ("V1") may be provided to the first driver 402, and a second voltage level ("V2") may be provided to the second driver 404. Thus, when the physical interface protocol is PCIe, driver 402 drives the differential data output (including Dout_t and Dout_c signals) at the first voltage level, and when the physical interface protocol is M-PHY, driver 404 drives the differential data output at the second voltage level.

[0040] exist Figure 5 , a driver circuit 500 is shown. The driver circuit 500 may be the driver circuit 308 ( Figure 3 ) is another example. The driver circuit 500 and the above-mentioned driver circuit 400 ( Figure 4 ) may be alternatives to each other. Driver circuit 500 may include a differential mode signal multiplexer ("MUX") 502 configured to select a PCIe differential data output signal 504 or an M-PHY differential data output signal 506 in response to a selection signal 508. A pair of drivers 510 and 512 may receive the output of the differential mode signal MUX 502 and provide differential data outputs including Dout_t and Dout_c signals.

[0041] Drivers 510 and 512 may drive respective signals using voltage levels provided by power rail selector 514. Power rail selector 514 may provide a first voltage level (“V1”) or a second voltage level (“V2”) in response to selection signal 508. For example, when selection signal 508 indicates that the memory is NVMe (i.e., the physical interface protocol is PCIe), power rail selector 514 may provide a first voltage level, and when selection signal 508 indicates that the memory is UFS (i.e., the physical interface protocol is M-PHY), power rail selector 514 may provide a second voltage level.

[0042] exist Figure 6 , the RX interface configuration logic 600 is shown. The RX interface configuration logic 600 may be the RX interface configuration circuit 206 ( Figure 2 ). The RX interface configuration logic 600 may include a buffer circuit (also referred to as a receiver circuit) 608, a multi-stage signaling deformatter 606, a parallelizer or deserializer 604, and a decoding logic 602, each of which may have a selector input configured to receive a selection signal 610.

[0043] The receiver or buffer circuit 608 may receive the differential data output signal 622 , which may be a PCIe differential data output signal or an M-PHY differential data output signal. The buffer circuit 608 provides the PCIe differential data output signal or the M-PHY differential data output signal to the multi-level signaling deformatter 606 .

[0044] The multi-level signaling deformatter 606 can convert its input signal from PWM, PAM, etc. to a serial format. The output of the multi-level signaling deformatter 606 can be provided to the deserializer 604, which can convert the data from the serial format to a parallel format. The deserializer 604 can provide the resulting parallel format data to the decoding logic 602. In some examples, the output of the multi-level signaling deformatter 606 can also be provided to the clock data recovery ("CDR") logic 612. The CDR logic 612 can recover the clock signal from the data signal. The host device can use the recovered clock signal to further process the data.

[0045] The decoding logic 602 may be configured to decode data, which may be PCIe data or M-PHY data. The decoding logic 602 may include PCIe specific decoding logic 616, M-PHY specific decoding logic 618, and common (for both PCIe and M-PHY) decoding logic 620. The decoding logic 602 decodes PCIe data and M-PHY data according to the PCIe and M-PHY protocols, respectively. Since such decoding logic 616-620 is well understood by those of ordinary skill in the art, these elements are not described in further detail herein. The output of the decoding logic 602 may include a PCIe data input signal 624 ("PCIe data input") and an M-PHY data input signal 626 ("M-PHY data input").

[0046] The decoding logic 602 may provide the PCIe data input signal 624 and the M-PHY data input signal 626 to the Figure 3 The processing unit to which the decoding logic 602 provides the PCIe data input signal 624 may be the encoding logic 302 ( Figure 3 ) may be the same processing unit from which the PCIe data output signal 312 is received, or it may be a different processing unit. The processing unit to which the decode logic 602 provides the M-PHY data input signal 626 may be the same processing unit from which the encode logic 302 receives the M-PHY data output signal 314, or it may be a different processing unit. The PCIe data may be provided to the processing unit via a PCIe bus, and the M-PHY data may similarly be provided via the bus.

[0047] exist Figure 7 , a receiver or buffer circuit 700 is shown. The buffer circuit 700 may be the buffer circuit 608 ( Figure 6 ). Buffer circuit 700 may include a first differential mode buffer 702 and a second differential mode buffer 704. Buffers 702 and 704 may be tri-state buffers. The first buffer 702 and the second buffer 704 may each receive a differential data input including Din_t and Din_c signals. Buffers 702 and 704 may drive respective signals using respective voltage levels. A first voltage level ("V1") may be provided to the first buffer 702, and a second voltage level ("V2") may be provided to the second buffer 704. Thus, when the physical interface protocol is PCIe, the first buffer 702 may drive the PCIe differential data input signal 706 at a first voltage level, and when the physical interface protocol is M-PHY, the second buffer 704 may drive the M-PHY differential data input signal 708 at a second voltage level.

[0048] In an example where buffers 702 and 704 are tri-state buffers, buffers 702 and 704 may operate in a complementary manner relative to each other in response to a select signal 710. That is, when the select signal 710 indicates that the memory is NVMe (i.e., the physical interface protocol is PCIe), the second buffer 704 sets its output to high impedance, while the first buffer 702 drives its output to provide a PCIe differential data input signal. Conversely, when the select signal 710 indicates that the memory is UFS (i.e., the physical interface protocol is M-PHY), the first buffer 702 sets its output to high impedance, while the second buffer 704 drives its output to provide an M-PHY differential data input signal.

[0049] exist Figure 8 , a receiver or buffer circuit 800 is shown. The buffer circuit 800 may be the buffer circuit 608 ( Figure 6 ) is another example. The buffer circuit 800 and the above-mentioned driver circuit 700 ( Figure 7 ) may be alternatives to each other. The buffer circuit 800 may include a differential mode signal demultiplexer (“DEMUX”) 802 configured to provide a PCIe differential data output signal 804 or an M-PHY differential data input signal 806 in response to a selection signal 808 .

[0050] A pair of buffers 810 and 812 can receive differential data inputs including Din_t and Din_c signals. Buffers 810 and 812 can receive corresponding signals using reference voltage levels provided by power rail selector 814 (e.g., by setting a signal detection threshold level for the corresponding signal). Power rail selector 814 can provide a first reference voltage level (“V1”) or a second reference voltage level (“V2”) in response to selection signal 808. For example, when selection signal 808 indicates that the memory is NVMe (i.e., the physical interface protocol is PCIe), power rail selector 814 can provide a first reference voltage level, and when selection signal 808 indicates that the memory is UFS (i.e., the physical interface protocol is M-PHY), power rail selector 814 can provide a second reference voltage level. When receiving data, buffers 810 and 812 can compare differential data inputs including Din_t and Din_c signals with the selected reference voltage level.

[0051] exist Fig. 9 , a TX impedance network 902 and an RX impedance network 904 are shown. The TX impedance network 902 and the RX impedance network 904 may be the above-mentioned TX impedance matching network 208 and the RX impedance matching network 210 ( Figure 2 ) example.

[0052] The TX impedance network 902 may include a first impedance 906 , a second impedance 908 , a third impedance 910 , and a fourth impedance 912 . The RX impedance network 904 may include a fifth impedance 914 , a sixth impedance 916 , a seventh impedance 918 , an eighth impedance 920 , and a ninth impedance 922 .

[0053] The first impedance 906 may be in the Dout_t signal path between the input side and the output side of the TX impedance network 902. The second impedance 908 may be in the Dout_c signal path between the input side and the output side of the TX impedance network 902. The third impedance 910 may be in the Dout_c signal path between the input side and the ground of the TX impedance network 902. The fourth impedance 912 may be in the Dout_t signal path between the input side and the ground of the TX impedance network 902. The first impedance 906 and the second impedance 908 may have the same impedance value Z1. The third impedance 910 and the fourth impedance 912 may have the same impedance value Z2. Each of the first impedance 906, the second impedance 908, the third impedance 910, and the fourth impedance 912 may have a control input configured to receive a selection signal 913. Each of the first impedance 906, the second impedance 908, the third impedance 910, and the fourth impedance 912 may change the values ​​of Z1 and Z2 in response to the selection signal 913. For example, the combination of the first impedance 906, the second impedance 908, the third impedance 910, and the fourth impedance 912 may take a first impedance configuration in response to the selection signal 913 indicating a PCIe physical interface type, and may take a second impedance configuration in response to the selection signal 913 indicating an M-PHY physical interface type.

[0054] The fifth impedance 914 may be in the Din_t signal path between the input side and the output side of the RX impedance network 904. The sixth impedance 916 may be in the Din_c signal path between the input side and the output side of the RX impedance network 904. The seventh impedance 918 may be in the Din_c signal path between the input side and the ground of the RX impedance network 904. The eighth impedance 920 may be in the Din_t signal path between the input side and the ground of the RX impedance network 904. The ninth impedance 922 may span the Din_t and Din_c signal paths on the input side of the input impedance network 902. The fifth impedance 914 and the sixth impedance 916 may have an impedance value Z1. The seventh impedance 918 and the eighth impedance 92 may have an impedance value Z2. The ninth impedance 922 may have another impedance value Z3. Each of the fifth impedance 914, the sixth impedance 916, the seventh impedance 918, the eighth impedance 920, and the ninth impedance 922 may have a control input configured to receive the selection signal 913. Each of the fifth impedance 914, the sixth impedance 916, the seventh impedance 918, the eighth impedance 920, and the ninth impedance 922 may change the values ​​of Z1, Z2, and Z3 in response to the selection signal 913. For example, the combination of the fifth impedance 914, the sixth impedance 916, the seventh impedance 918, the eighth impedance 920, and the ninth impedance 922 may adopt a third impedance configuration in response to the selection signal 913 indicating a PCIe physical interface type, and may adopt a fourth impedance configuration in response to the selection signal 913 indicating an M-PHY physical interface type.

[0055] exist Fig.10 , a configurable clock circuit 1000 is shown. The configurable clock circuit 1000 may be the configurable clock circuit 128 ( Figure 1 ). The configurable clock circuit 1000 may include a differential driver 1002, a first level shifter 1004, a first clock buffer 1006, a single-ended driver 1008, a second level shifter 1010, a second clock buffer 1012, a clock MUX 1014, and a phase-locked loop (“PLL”) 1016. The differential mode driver 1002 may receive a differential mode clock signal (“Clock” and its complement “Clock_N”). The single-ended driver 1008 may receive the clock signal. The output of the differential driver 1002 may be provided to an input of the first level shifter 1004. The output of the first level shifter 1004 may be provided to an input of the first clock buffer 1006. The output of the first clock buffer 1006 may be provided to a first input of the clock MUX 1014. The output of the single-ended driver 1008 may be provided to an input of the second level shifter 1010. The output of the second level shifter 1010 may be provided to an input of the second clock buffer 1012. The output of the second clock buffer 1012 may be provided to a second input of a clock MUX 1014. The clock MUX 1014 may have a selector input configured to receive a select signal 1018. In response to the select signal 1018, the clock MUX 1014 may select a differential clock signal (such as processed by the differential driver 1002, the first level shifter 1004, and the first clock buffer 1006) or a single-ended clock signal (such as processed by the single-ended driver 1008, the second level shifter 1010, and the second clock buffer 1012) as its output. The output of the clock MUX 1014 (i.e., the selected clock signal) may be provided to the PLL 1016. The output of the PLL 1016 may be used as a reference clock signal 1020, as described above with respect to the reference clock signal 124 ( Figure 1 ) described.

[0056] exist Fig.11In the embodiment of the present invention, a method 1100 for selectively configuring a flash memory physical interface is shown in block diagram form. As shown in block 1102, the method 1100 may include: providing a selection signal indicating a selected one of a first flash memory type and a second flash memory type. As shown in block 1104, the method 1100 may also include: coupling, by a driver circuit, one of a first differential memory data signal input of a driver circuit and a second differential memory data signal input of the driver circuit to a differential data input of a flash memory system based on the selection signal. As shown in block 1106, the method 1100 may also include: coupling, by a receiver circuit, a differential data output of the flash memory system to a selected one of a first differential memory data signal output of a receiver circuit and a second differential memory data signal output of the receiver circuit based on the selection signal.

[0057] Fig.12 An example of a portable computing device ("PCD") 1200 is shown in which exemplary embodiments of systems, methods, computer-readable media, and other examples of selectively configuring a flash memory physical interface may be provided. PCD 1200 may be, for example, a laptop or palmtop computer, a cellular or smart phone, a personal digital assistant, a navigation device, a smartbook, a portable game console, a satellite phone, etc. For clarity, some data buses, interconnects, signals, etc. are not shown in the figure. Fig.12 For example, a PCIe bus is not shown, but may be included and configured to interconnect various processing systems, memories, etc., as will be understood by one of ordinary skill in the art.

[0058] PCD 1200 may include SoC 1202. SoC 1202 may include CPU 1204, GPU 1206, digital signal processor ("DSP") 1207, analog signal processor 1208, modem / modem subsystem 1254, or other processors. CPU 1204 may include one or more CPU cores, such as first CPU core 1204A, second CPU core 1204B, and so on, up to Nth CPU core 1204N.

[0059] The PCD 1200 may include a display controller 1210 and a touch screen controller 1212 coupled to the CPU 1204. A touch screen display 1214 external to the SoC 1202 may be coupled to the display controller 1210 and the touch screen controller 1212. The PCD 1200 may also include a video decoder 1216 coupled to the CPU 1204. A video amplifier 1218 may be coupled to the video decoder 1216 and the touch screen display 1214. A video port 1220 may be coupled to the video amplifier 1218. A universal serial bus (“USB”) controller 1222 may also be coupled to the CPU 1204, and a USB port 1224 may be coupled to the USB controller 1222. A subscriber identity module (“SIM”) card 1226 may also be coupled to the CPU 1204.

[0060] The CPU 1204 may be coupled to one or more memories with which the CPU 1204 may initiate memory transactions. The one or more memories may include both volatile and non-volatile memory or NVM. Examples of volatile memory include static random access memory ("SRAM") 1228 and dynamic random access memory ("DRAM") 1230. Such memory may be internal to the SoC 1202, as in the illustrated embodiment, or alternatively, may be external to the SoC 1202. A DRAM controller 1229 coupled to the CPU 1204 may control writing data to and reading data from the DRAM 1230.

[0061] The one or more memories may also include flash memory 1231. Flash memory 1231 may be NVMe or UFS. A flash memory controller 1229 coupled to CPU 1204 may control various aspects of writing data to and reading data from flash memory 1231. In an example where flash memory 1231 is NVMe, some or all NVMe controller functions may be included within flash memory 1231, and flash memory 1231 may be coupled to CPU 1204 via a PCIe bus (not shown).

[0062] The flash memory interface configuration logic 1233 may be coupled in a path between the flash memory controller 1229 and the flash memory 1231. The flash memory interface configuration logic 1233 may be the flash memory interface configuration logic 110 ( Figure 1 ) or 202( Figure 2 ). Although for clarity purposes Fig.12 Not shown, but the flash interface configuration logic 1233 may be coupled to a source of the above-mentioned selection signal indicating whether the flash memory 1231 is NMVe or UFS.

[0063] A stereo audio CODEC 1234 may be coupled to the analog signal processor 1208. In addition, an audio amplifier 1236 may be coupled to the stereo audio CODEC 1234. A first stereo speaker 1238 and a second stereo speaker 1240 may be coupled to the audio amplifier 1236, respectively. In addition, a microphone amplifier 1242 may be coupled to the stereo audio CODEC 1234, and a microphone 1244 may be coupled to the microphone amplifier 1242. A frequency modulation ("FM") radio tuner 1246 may be coupled to the stereo audio CODEC 1234. An FM antenna 1248 may be coupled to the FM radio tuner 1246. In addition, a stereo headset 1250 may be coupled to the stereo audio CODEC 1234. Other devices that may be coupled to the CPU 1204 include one or more digital (e.g., CCD or CMOS) cameras 1252.

[0064] A modem or RF transceiver 1254 can be coupled to the analog signal processor 1208 and the CPU 1204. An RF switch 1256 can be coupled to the RF transceiver 1254 and the RF antenna 1258. In addition, a keyboard 1260, a mono headset with a microphone 1262, and a vibrator device 1264 can be coupled to the analog signal processor 1208.

[0065] SoC 1202 may have one or more internal or on-chip thermal sensors 1270A and may be coupled to one or more external or off-chip thermal sensors 1270B. Analog-to-digital converter controller 1272 may convert the voltage drop generated by thermal sensors 1270A and 1270B into a digital signal. Power supply 1274 and power management integrated circuit (“PMIC”) 1276 may provide power to SoC 1202.

[0066] The firmware or software may be stored in any of the above-described memories, such as DRAM 1230, flash memory 1231, SRAM 1228, etc., or may be stored in local memory directly accessible by the processor hardware on which the software or firmware is executed. The execution of such firmware or software may control aspects of any of the above-described methods, or configure aspects of any of the above-described systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium" as that term is understood in the patent dictionary.

[0067] Implementation examples are described in the following numbered clauses.

[0068] 1. A system for selectively configuring a flash memory physical interface, comprising:

[0069] a driver circuit having a first differential memory data signal input and a second differential memory data signal input, the driver circuit having a driver selector input configured to receive a select signal indicative of a selected one of a first flash memory type and a second flash memory type, the driver circuit configured to couple the selected one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of a flash memory system based on the select signal; and

[0070] a receiver circuit coupled to the differential data output of the flash memory system and having a receiver selector input configured to receive the select signal, the receiver circuit having a first differential memory data signal output and a second differential memory data signal output, the receiver circuit being configured to couple the differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on the select signal.

[0071] 2. The system of clause 1, wherein the driver circuit comprises:

[0072] a first tri-state differential driver coupled to said first differential memory data signal input; and

[0073] A second three-state differential driver is coupled to the second differential memory data signal input, and the output of the first three-state differential driver and the output of the second three-state differential driver are coupled together.

[0074] 3. The system of clause 1, wherein the driver circuit comprises a differential signal multiplexer.

[0075] 4. The system of any of clauses 1-3, wherein the first flash memory type is Universal Flash Storage ("UFS") and the second flash memory type is Non-Volatile Memory Express ("NVMe").

[0076] 5. A system according to any one of clauses 1 to 4, further comprising:

[0077] encoding logic configured to encode output data for transmission to the flash memory system through the driver circuit, the encoding logic comprising M-PHY encoding logic and Peripheral Component Interconnect Express (“PCIe”) encoding logic, the M-PHY encoding logic configured to encode the output data using the M-PHY protocol, the PCIe encoding logic configured to encode the output data using the PCIe protocol; and

[0078] A decoding logic is configured to decode input data received from the flash memory system through the receiver circuit, the decoding logic comprising M-PHY decoding logic and PCIe decoding logic, the M-PHY decoding logic is configured to decode the input data using the M-PHY protocol, and the PCIe decoding logic is configured to decode the input data using the PCIe protocol.

[0079] 6. A system according to any one of clauses 5, further comprising:

[0080] serializer logic configured to receive parallel output data from the encoding logic and convert the parallel output data into serial output data; and

[0081] A deserializer logic is configured to receive serial input data from the receiver circuit and convert the serial input data to parallel input data.

[0082] 7. A system according to any one of clauses 1 to 6, further comprising:

[0083] a configurable transmit-side impedance network coupled to a differential data output of the driver circuit and the differential data input of the flash memory system, the configurable transmit-side impedance network configured to provide a selected one of a first impedance configuration and a second impedance configuration based on the select signal; and

[0084] A configurable receive-side impedance network is coupled to the differential data input of the receiver circuit and the differential data output of the flash memory system, the configurable receive-side impedance network being configured to provide a selected one of a third impedance configuration and a fourth impedance configuration based on the selection signal.

[0085] 8. The system of any one of clauses 1-7, further comprising a clock signal circuit configured to select one of the first clock signal and the second clock signal based on the selection signal and provide the selected clock signal to the flash memory system.

[0086] 9. The system of any of clauses 1-8, wherein the system is included in a system on a chip ("SoC"), and the SoC includes at least one processing system configured to initiate memory transactions with the flash memory system.

[0087] 10. A method for selectively configuring a flash memory physical interface, comprising:

[0088] providing a selection signal indicating a selected one of a first flash memory type and a second flash memory type;

[0089] coupling, by a driver circuit, one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of a flash memory system based on the select signal; and

[0090] A differential data output of the flash memory system is coupled to a selected one of a first differential memory data signal output and a second differential memory data signal output based on the select signal by a receiver circuit.

[0091] 11. The method of clause 10, wherein the first flash memory type is Universal Flash Storage ("UFS") and the second flash memory type is Non-Volatile Memory Express ("NVMe").

[0092] 12. The method according to clause 10 or 11, further comprising:

[0093] encoding output data for transmission to the flash memory system through the driver circuit, including encoding the output data using an M-PHY protocol and encoding the output data using a Peripheral Component Interconnect Express (“PCIe”) protocol; and decoding input data received from the flash memory system through the receiver circuit, including decoding the input data using an M-PHY protocol and decoding the input data using the PCIe protocol.

[0094] 13. The method according to any one of clauses 12, further comprising:

[0095] converting the encoded parallel output data into serial output data; and

[0096] Serial input data from the receiver circuit is converted to parallel input data.

[0097] 14. A method according to any one of clauses 10 to 13, further comprising:

[0098] coupling, via a configurable output impedance network, one of a first impedance configuration and a second impedance configuration to a differential data output of the driver circuit and a differential data input of the flash memory system based on the select signal; and

[0099] One of a third impedance configuration and a fourth impedance configuration is coupled to a differential data input of the receiver circuit and the differential data output of the flash memory system based on the select signal through a configurable output impedance network.

[0100] 15. A method according to any one of clauses 10 to 14, further comprising:

[0101] selecting one of a first clock signal and a second clock signal based on the selection signal; and

[0102] A selected clock signal is provided to the flash memory system.

[0103] 16. A system for selectively configuring a flash memory physical interface, comprising:

[0104] means for providing a selection signal indicating a selected one of a first flash memory type and a second flash memory type;

[0105] a first unit for coupling one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of a flash memory system based on the select signal; and

[0106] A second unit for coupling a differential data output of the flash memory system to a selected one of a first differential memory data signal output and a second differential memory data signal output based on the select signal.

[0107] 17. The system of clause 16, wherein the first flash memory type is Universal Flash Storage ("UFS") and the second flash memory type is Non-Volatile Memory Express ("NVMe").

[0108] 18. A system according to clause 16 or 17, further comprising:

[0109] means for encoding output data for transmission to the flash memory system via the differential data output, including means for encoding the output data using an M-PHY protocol and encoding the output data using a Peripheral Component Interconnect Express ("PCIe") protocol; and

[0110] The means for decoding input data received from the flash memory system via the differential data input includes means for decoding the input data using an M-PHY protocol and decoding the input data using the PCIe protocol.

[0111] 19. The system according to clause 18, further comprising:

[0112] A unit for converting the encoded parallel output data into serial output data; and

[0113] Means for converting serial input data from said first means for coupling into parallel input data.

[0114] 20. A system according to any one of clauses 16 to 19, further comprising:

[0115] means for coupling one of a first impedance configuration and a second impedance configuration to a differential data output of the driver circuit and a differential data input of the flash memory system based on the select signal; and

[0116] Means for coupling one of a third impedance configuration and a fourth impedance configuration to a differential data input of the second means for coupling and the differential data output of the flash memory system based on the select signal.

[0117] 21. The system of any of clauses 16-20, further comprising means for selecting one of the first clock signal and the second clock signal based on the selection signal.

[0118] 22. A system on a chip (“SoC”), comprising:

[0119] a processing system configured to direct memory transactions to a flash memory system;

[0120] memory type selection logic configured to provide a selection signal indicating whether the flash memory system is a first flash memory type or a second flash memory type;

[0121] Flash physical interface configuration logic, including:

[0122] a driver circuit having a first differential memory data signal input and a second differential memory data signal input, the driver circuit having a driver selector input configured to receive the select signal, the driver circuit being configured to couple a selected one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of the flash memory system based on the select signal; and

[0123] a receiver circuit coupled to a differential data output of the flash memory system and having a receiver selector input configured to receive the select signal, the receiver circuit having a first differential memory data signal output and a second differential memory data signal output, the receiver circuit being configured to couple the differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on the select signal.

[0124] 23. The SoC of clause 22, wherein the selection logic comprises at least one of: a register configurable by a processor; a fuse; a voltage detector responsive to a predetermined voltage level indicative of a flash memory type; or an impedance detector responsive to a predetermined impedance level indicative of a flash memory type.

[0125] 24. A SoC according to clause 22 or 23, wherein the driver circuit comprises:

[0126] a first tri-state differential driver coupled to said first differential memory data signal input; and

[0127] A second three-state differential driver is coupled to the second differential memory data signal input, and the output of the first three-state differential driver and the output of the second three-state differential driver are coupled together.

[0128] 25. The SoC of clause 22 or 23, wherein the driver circuit comprises a differential signal multiplexer.

[0129] 26. The SoC of any of clauses 22-25, wherein the first flash memory type is Universal Flash Storage ("UFS") and the second flash memory type is Non-Volatile Memory Express ("NVMe").

[0130] 27. A SoC according to any one of clauses 22 to 26, further comprising:

[0131] encoding logic comprising M-PHY encoding logic configured to encode output data using the M-PHY protocol and Peripheral Component Interconnect Express (“PCIe”) encoding logic configured to encode output data using the PCIe protocol; and

[0132] The decoding logic includes an M-PHY decoding logic and a PCIe decoding logic, wherein the M-PHY decoding logic is configured to decode input data using the M-PHY protocol, and the PCIe decoding logic is configured to decode the input data using the PCIe protocol.

[0133] 28. The SoC according to clause 27, further comprising:

[0134] serializer logic configured to receive parallel output data from the encoding logic and convert the parallel output data into serial output data; and

[0135] A deserializer logic is configured to receive serial input data from the receiver circuit and convert the serial input data to parallel input data.

[0136] 29. A SoC according to any of clauses 22 to 28, further comprising:

[0137] a configurable transmit-side impedance network coupled to a differential data output of the driver circuit and the differential data input of the flash memory system, the configurable transmit-side impedance network configured to provide a selected one of a first impedance configuration and a second impedance configuration based on the select signal; and

[0138] A configurable receive-side impedance network is coupled to the differential data input of the receiver circuit and the differential data output of the flash memory system, the configurable receive-side impedance network being configured to provide a selected one of a third impedance configuration and a fourth impedance configuration based on the selection signal.

[0139] 30. The SoC according to any one of clauses 22-29, further comprising a clock signal circuit configured to select one of the first clock signal and the second clock signal based on the selection signal and provide the selected clock signal to the flash memory system.

[0140] Alternative embodiments will become apparent to those skilled in the art.Thus, although selected aspects have been shown and described in detail, it should be understood that various substitutions and changes may be made therein.

Claims

1. A system for selectively configuring a flash memory physical interface, comprising: a driver circuit having a first differential memory data signal input and a second differential memory data signal input, the driver circuit having a driver selector input configured to receive a select signal indicative of a selected one of a first flash memory type and a second flash memory type, the driver circuit configured to couple the selected one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of a flash memory system based on the select signal; as well as a receiver circuit coupled to the differential data output of the flash memory system and having a receiver selector input configured to receive the select signal, the receiver circuit having a first differential memory data signal output and a second differential memory data signal output, the receiver circuit being configured to couple the differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on the select signal.

2. The system according to claim 1, wherein: The driver circuit comprises: a first tri-state differential driver coupled to said first differential memory data signal input; and A second three-state differential driver is coupled to the second differential memory data signal input, and the output of the first three-state differential driver and the output of the second three-state differential driver are coupled together.

3. The system according to claim 1, wherein: The driver circuit includes a differential signal multiplexer.

4. The system according to claim 1, wherein: The first flash memory type is Universal Flash ("UFS") and the second flash memory type is Non-Volatile Memory Express ("NVMe").

5. The system according to claim 4, further comprising: encoding logic configured to encode output data for transmission to the flash memory system via the driver circuit, the encoding logic comprising M-PHY encoding logic configured to encode the output data using the M-PHY protocol and Peripheral Component Interconnect Express ("PCIe") encoding logic configured to encode the output data using the PCIe protocol; as well as A decoding logic is configured to decode input data received from the flash memory system through the receiver circuit, the decoding logic comprising M-PHY decoding logic and PCIe decoding logic, the M-PHY decoding logic is configured to decode the input data using the M-PHY protocol, and the PCIe decoding logic is configured to decode the input data using the PCIe protocol.

6. The system according to claim 5, further comprising: a serializer logic configured to receive parallel output data from the encoding logic and convert the parallel output data into serial output data; as well as A deserializer logic is configured to receive serial input data from the receiver circuit and convert the serial input data to parallel input data.

7. The system of claim 1, further comprising: a configurable transmit-side impedance network coupled to a differential data output of the driver circuit and the differential data input of the flash memory system, the configurable transmit-side impedance network configured to provide a selected one of a first impedance configuration and a second impedance configuration based on the select signal; as well as A configurable receive-side impedance network is coupled to the differential data input of the receiver circuit and the differential data output of the flash memory system, the configurable receive-side impedance network being configured to provide a selected one of a third impedance configuration and a fourth impedance configuration based on the selection signal. 8 . The system of claim 1 , further comprising a clock signal circuit configured to select one of a first clock signal and a second clock signal based on the selection signal and provide the selected clock signal to the flash memory system.

9. The system according to claim 1, wherein: The system is included in a system on a chip ("SoC"), and the SoC includes at least one processing system configured to initiate memory transactions with the flash memory system.

10. A method for selectively configuring a flash memory physical interface, comprising: providing a selection signal indicating a selected one of a first flash memory type and a second flash memory type; coupling, by a driver circuit, one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of a flash memory system based on the select signal; as well as A differential data output of the flash memory system is coupled to a selected one of a first differential memory data signal output and a second differential memory data signal output based on the select signal by a receiver circuit.

11. The method according to claim 10, wherein: The first flash memory type is Universal Flash Storage ("UFS") and the second flash memory type is Non-Volatile Memory Express ("NVMe").

12. The method according to claim 11, further comprising: encoding output data for transmission to the flash memory system via the driver circuit, including encoding the output data using an M-PHY protocol and encoding the output data using a Peripheral Component Interconnect Express ("PCIe") protocol; as well as Decoding input data received from the flash memory system through the receiver circuit includes decoding the input data using an M-PHY protocol and decoding the input data using the PCIe protocol.

13. The method according to claim 12, further comprising: converting the encoded parallel output data into serial output data; as well as Serial input data from the receiver circuit is converted to parallel input data.

14. The method according to claim 10, further comprising: coupling, via a configurable output impedance network, one of a first impedance configuration and a second impedance configuration to a differential data output of the driver circuit and a differential data input of the flash memory system based on the select signal; as well as One of a third impedance configuration and a fourth impedance configuration is coupled to a differential data input of the receiver circuit and the differential data output of the flash memory system based on the select signal through a configurable output impedance network.

15. The method according to claim 10, further comprising: selecting one of a first clock signal and a second clock signal based on the selection signal; as well as A selected clock signal is provided to the flash memory system.

16. A system for selectively configuring a flash memory physical interface, comprising: means for providing a selection signal indicative of a selected one of a first flash memory type and a second flash memory type; a first unit for coupling one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of a flash memory system based on the select signal; as well as A second unit for coupling a differential data output of the flash memory system to a selected one of a first differential memory data signal output and a second differential memory data signal output based on the select signal.

17. The system of claim 16, wherein: The first flash memory type is Universal Flash Storage ("UFS") and the second flash memory type is Non-Volatile Memory Express ("NVMe").

18. The system of claim 17, further comprising: means for encoding output data for transmission to the flash memory system via the differential data output, including means for encoding the output data using an M-PHY protocol and encoding the output data using a Peripheral Component Interconnect Express ("PCIe") protocol; as well as The means for decoding input data received from the flash memory system via the differential data input includes means for decoding the input data using an M-PHY protocol and decoding the input data using the PCIe protocol.

19. The system of claim 18, further comprising: a unit for converting the encoded parallel output data into serial output data; as well as Means for converting serial input data from said first means for coupling into parallel input data.

20. The system of claim 16, further comprising: means for coupling one of a first impedance configuration and a second impedance configuration to a differential data output of the driver circuit and a differential data input of the flash memory system based on the select signal; as well as Means for coupling one of a third impedance configuration and a fourth impedance configuration to a differential data input of the second means for coupling and the differential data output of the flash memory system based on the select signal.

21. The system of claim 16, further comprising: Means for selecting one of a first clock signal and a second clock signal based on the selection signal.

22. A system on a chip ("SoC") comprising: a processing system configured to direct memory transactions to a flash memory system; memory type selection logic configured to provide a selection signal indicating whether the flash memory system is a first flash memory type or a second flash memory type; Flash physical interface configuration logic, including: a driver circuit having a first differential memory data signal input and a second differential memory data signal input, the driver circuit having a driver selector input configured to receive the select signal, the driver circuit being configured to couple a selected one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of the flash memory system based on the select signal; as well as a receiver circuit coupled to a differential data output of the flash memory system and having a receiver selector input configured to receive the select signal, the receiver circuit having a first differential memory data signal output and a second differential memory data signal output, the receiver circuit being configured to couple the differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on the select signal.

23. The SoC according to claim 22, wherein: The selection logic includes at least one of: a register configurable by a processor; a fuse; a voltage detector responsive to a predetermined voltage level indicative of a flash memory type; or an impedance detector responsive to a predetermined impedance level indicative of a flash memory type.

24. The SoC according to claim 22, wherein: The driver circuit comprises: a first tri-state differential driver coupled to said first differential memory data signal input; and A second three-state differential driver is coupled to the second differential memory data signal input, and the output of the first three-state differential driver and the output of the second three-state differential driver are coupled together.

25. The SoC according to claim 22, wherein: The driver circuit includes a differential signal multiplexer.

26. The SoC according to claim 25, wherein: The first flash memory type is Universal Flash Storage ("UFS") and the second flash memory type is Non-Volatile Express ("NVMe").

27. The SoC according to claim 26, further comprising: encoding logic including M-PHY encoding logic configured to encode output data using the M-PHY protocol and Peripheral Component Interconnect Express ("PCIe") encoding logic configured to encode output data using the PCIe protocol; as well as The decoding logic includes an M-PHY decoding logic and a PCIe decoding logic, wherein the M-PHY decoding logic is configured to decode input data using the M-PHY protocol, and the PCIe decoding logic is configured to decode the input data using the PCIe protocol.

28. The SoC according to claim 27, further comprising: a serializer logic configured to receive parallel output data from the encoding logic and convert the parallel output data into serial output data; as well as A deserializer logic is configured to receive serial input data from the receiver circuit and convert the serial input data to parallel input data.

29. The SoC according to claim 22, further comprising: a configurable transmit-side impedance network coupled to a differential data output of the driver circuit and the differential data input of the flash memory system, the configurable transmit-side impedance network configured to provide a selected one of a first impedance configuration and a second impedance configuration based on the select signal; as well as A configurable receive-side impedance network is coupled to the differential data input of the receiver circuit and the differential data output of the flash memory system, the configurable receive-side impedance network being configured to provide a selected one of a third impedance configuration and a fourth impedance configuration based on the selection signal.

30. The SoC according to claim 22, further comprising a clock signal circuit configured to select one of the first clock signal and the second clock signal based on the selection signal and provide the selected clock signal to the flash memory system.

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