SOT MRAM with double-layer spin orbit moment (SOT) metal

Abstract

A magnetic random access memory (MRAM) device includes: a magnetic tunnel junction (MTJ) stack; a spin orbit torque (SOT) layer under the MTJ stack; and a dielectric pillar under the SOT layer and the MTJ stack. The SOT layer has a stepped profile.

Description

Technical Field

[0001] The present invention relates to the electrical, electronic and computer fields, and more particularly to the manufacture of non-volatile memory. Background Art

[0002] Figure 1 A spin-orbit torque (SOT) magnetic random access memory (MRAM memory cell) 100 according to the prior art is depicted, excluding the main portion of the bottom electrode. The MRAM 100 is formed on a substrate 101. The MRAM 100 includes a top (read) electrode 104, a magnetic tunnel junction (MTJ) stack 108, and a spin-orbit torque (SOT) layer 110. The SOT layer 110 includes a left region 102 and a right region 106, which are connected to a first (supply) bottom electrode and a second (write) bottom electrode, respectively, which are out of the plane of the drawing view. The MTJ stack 108 includes a pinned layer 112, a barrier layer 114, and a free layer 116. The MRAM 100 SOT senses the switching of the free layer 116 (for writing) by injecting an in-plane current from the first bottom electrode to the write electrode through the SOT layer 110 with or without the assistance of a static in-plane magnetic field. This implements the concept of a three-terminal MTJ based on isolated read / write paths, thereby improving device endurance and read stability. Furthermore, due to the SOT spin-transfer geometry, the delay time is negligible, which allows for reliable switching operation on a sub-nanosecond timescale.

[0003] Occasionally, it is also undesirable for the MRAM 100 to have a metal bridge 118 spanning across the edge of the barrier layer 114. The bridge 118 is discussed further below. Summary of the invention

[0004] The present invention provides a technique for a spin-orbit torque (SOT) magnetic random access memory (MRAM) controlled by an improved patterning process. In one aspect, an exemplary magnetic random access memory (MRAM) device includes: a magnetic tunnel junction (MTJ) stack; a spin-orbit torque (SOT) layer located below the MTJ stack, wherein the SOT layer has a stepped profile; and a dielectric pillar located below the SOT layer and the MTJ stack.

[0005] According to another aspect, an exemplary method includes: forming a dielectric substrate of a first dielectric material, and a dielectric pillar of a second dielectric material, wherein the dielectric pillar protrudes from the dielectric substrate; forming a first intermediate structure by depositing a first conductive material layer onto the dielectric substrate, the first conductive material layer being thick enough to cover the pillar and the substrate; forming a planarized structure by planarizing the first intermediate structure to expose the pillar; and depositing a second spin-orbit torque metal layer onto the planarized structure.

[0006] According to another aspect, an exemplary magnetic random access memory (MRAM) device includes: a magnetic tunnel junction (MTJ) stack; and a spin-orbit torque (SOT) layer located below the MTJ stack. The SOT layer has an upper step directly below the MTJ stack, and a lower step adjacent to and below the upper step. The upper step includes a spin-orbit torque metal.

[0007] Based on the foregoing, the technology of the present invention can provide substantially beneficial technical effects. For example, one or more embodiments provide one or more of the following:

[0008] SOT MRAM has enhanced reliability due to reduced presence of metal bridges on the barrier layer.

[0009] SOT MRAM has enhanced switching time due to the improved geometry of the SOT layer.

[0010] Some embodiments may not have these potential advantages, and these potential advantages are not required for all embodiments.These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments of the invention, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A SOT MRAM according to the prior art is schematically depicted.

[0012] Figure 2 A SOT MRAM according to an exemplary embodiment is schematically depicted.

[0013] Figure 3 The flowchart depicts the process for manufacturing Figure 2 The SOT MRAM method is shown.

[0014] Figures 4 to 9 The schematic diagram depicts the Figure 3 The method steps shown result in a structure. Figures 5 to 9 is Figure 4 The cross section is taken at 5.

[0015] Fig.10 The schematic diagram depicts Figure 2 An alternative embodiment of a SOT MRAM is shown.

[0016] Fig.11 The schematic diagram depicts Figure 2 Another alternative embodiment of a SOT MRAM is shown. DETAILED DESCRIPTION

[0017] exist Figure 1In the manufacturing of the SOT MRAM 100 shown, according to conventional methods, there is a step of anisotropic etching (usually reactive ion etching (RIE) or ion beam etching (IBE)) to define the MTJ stack 108. During the etching step, metal from the SOT layer 110 is sputtered and redeposited onto the edge of the barrier layer 114. The redeposited metal sometimes forms a bridge 118, which electrically shorts the barrier layer 114, thereby rendering the MRAM 100 inoperable.

[0018] One or more embodiments advantageously provide a method for manufacturing an MRAM that does not form bridges across the barrier layer in a first instance, or eliminates these bridges if they are formed. Such a SOT MRAM 200 is Figure 2 Disclosed herein are unique intermediate and final structures.

[0019] Initial efforts to provide such methods considered the bridge 118 to be an artifact of "under-etching" on the MTJ stack 108 and SOT layer 110. It was believed that additional etching could eliminate the bridge. However, the additional etching resulted in excessive thinning ("over-etching") of the SOT layer 110, which undesirably increased the resistance of read and write operations. In contrast, the MRAM 200 advantageously implements additional etching without excessively thinning its spin-orbit torque (SOT) layer 210.

[0020] The MRAM 200 includes a top (read) electrode 204, a magnetic tunnel junction (MTJ) stack 208, and a SOT layer 210. The SOT layer 210 includes a left region 202 and a right region 206, which are connected to a first (supply) bottom electrode and a second (write) bottom electrode, respectively, that are out of the plane of the drawing view. The MTJ stack 208 includes a pinned layer 212, a barrier layer 214, and a free layer 216. In the MRAM 200, switching of the free layer 216 (for writing) is induced by injecting an in-plane current from the supply bottom electrode to the write electrode through the SOT layer 210 with or without the assistance of a static in-plane magnetic field. The MRAM 200 is disposed atop a dielectric pillar 404, which will be referred to below Figure 4 and Figure 5 Further discussion. Another dielectric 218 encapsulates the MRAM 200 and insulates it from adjacent memory cells.

[0021] and Figure 1 Unlike the prior art shown, the SOT layer 210 has a stepped profile having an upper step 222 and a lower step 224 joined by a riser 226. The steps 222, 224 and the riser 226 have a substantially uniform thickness so that the resistance is not impaired. The stepped profile of the SOT layer 210 is based on the Figure 3The method 300 shown in the flowchart in FIG. 2 is generated by the interconnect layer 220.

[0022] Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacture of semiconductor chips can start with multiple CAD (computer-aided design) generated device patterns, which are then replicated on a substrate. The replication process can involve the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processes.

[0023] Many different precursors can be used for the deposition of semiconductors or other materials. In some embodiments, the gas source for material deposition may include silicon (Si) deposited by silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, disilane, and combinations thereof. In other examples, when the material includes germanium, the germanium gas source may be selected from a group consisting of germane, digermane, halogengermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. In other examples, when the material includes a metal or a metal compound, the gas source may include a pure elemental metal or metal compound, such as in physical vapor deposition (PVD) / physical vapor transport (PVT) or atomic layer deposition (ALD). Other deposition methods that may also be applicable to the structures of things described herein include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Various chemical vapor deposition processes typically utilize multiple precursors that react on their way to the deposition surface to produce a final composition (which typically has a higher sublimation temperature than the precursors).

[0024] refer to Figure 3 , at 302, formed in Figure 4 and Figure 5 The precursor structure 400 is shown. The structure 400 includes a first dielectric substrate 402, and a second dielectric formed into pillars 404 and bars 406. The pillars 404 will be Figure 2 A replication of the MRAM 200 shown provides a substrate. Pillars 404 and strips 406 protrude from substrate 402. Substrate 402 is made of a different dielectric than pillars 404 and strips 406 so that the substrate can be selectively etched relative to the pillars and strips. Suitable materials for substrate 402 include, for example, silicon nitride, aluminum oxide, hafnium oxide, and the like.

[0025] There are many techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are generally referred to as "etching". For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, which are all known techniques for removing selective materials when forming a semiconductor structure. Standard Clean Solution 1 (SC1) contains a strong base, typically ammonium hydroxide and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. The techniques and applications of etching are well known to those skilled in the art.

[0026] As an exemplary subtractive process, in a photolithography process, a layer of photoresist material may be first applied on top of a substrate and then selectively exposed according to a predetermined device pattern or patterns. Portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beam, X-rays, etc.) may undergo some changes in their solubility in certain solutions. The photoresist may then be developed in a developer solution to remove the unexposed (in a negative resist) or exposed (in a positive resist) portions of the resist layer to create a photoresist pattern or photomask. The photoresist pattern or photomask may then be copied or transferred to a substrate beneath the photoresist pattern.

[0027] At 304, a first material (eg, spin-orbit torque metal) layer 602 is deposited to form a Figure 6 The structure 600 is shown. The first layer 602 will be formed later on Figure 2 The lower step 224 is shown. In one or more embodiments, suitable SOT materials include, for example, β-Ta, β-W, Cu x Pt 1-x , Cu 1-x T ax , Pd x Pt 1-x 、Au x Pt 1-x ,Pt,Bi2Se3,WTe2,PtTe2,TaS2,Pt x R 1-x or any metal alloy with an average atomic weight higher than 80. As mentioned, such materials are suitable for deposition by, for example, PVD, ALD, or MBE. In structure 600 , first layer 602 covers both pillars 404 and bars 406 .

[0028] It should be noted that in some embodiments, the first layer 602 need not be a spin-orbit torque metal, but instead may be any conductive material that is compatible with a spin-orbit torque metal.

[0029] At 306, the structure 600 is planarized to form Figure 7Structure 700 is shown. In one or more embodiments, methods such as chemical mechanical polishing (CMP) can be used for planarization. In structure 700, first layer 602 has been made flush with the tops of pillars 404 and strips 406, so that those structures interrupt first layer 602. Later in the manufacture of MRAM 200, this allows strips 406 to provide boundaries for the MRAM.

[0030] At 308, a second SOT material layer 802, a free layer 216, a barrier layer 214, a pinned layer 212, and a top electrode 204 are deposited to form a Figure 8 The structure 800 is shown. After the addition process in step 312, the second layer 802 will form the upper step 222 of the SOT layer 210. For the free layer and the pinned layer, suitable materials include CoFeB or MgO-based materials. For the top electrode, suitable materials include TiN, TaN, W, etc. It can be seen that in the structure 800, the second layer 802 covers the strip 406 and the column 404.

[0031] At 310, a dielectric hard mask (HM) (SiN, SiOx, SiXByCzNt, etc.) (not shown) is deposited and patterned by photolithography, reactive ion etching, or ion beam etching to form a Fig. 9 The structure 900 shown in FIG. 1 has a stop on the lower step 224 of the SOT layer 210 (see FIG. 2 ). Figure 2 ). This etching step defines the MTJ stack 208 (see Figure 2 ). In one or more embodiments, anisotropic etching (e.g., reactive ion etching (RIE) or ion beam etching (IBE)) is used to remove material to expose the MTJ stack 208. In the prior art, the etching step is where the etched SOT metal is back-sputtered onto the edge of the barrier layer and often forms an undesirable bridge 118. Back-sputtering is a common side effect of RIE or IBE. However, according to an exemplary embodiment, the lower step 224 of the SOT layer 210 provides additional thickness. Therefore, it can be Figure 8 The structure 800 is etched down far enough to remove any bridges that might otherwise form on the edge of the barrier layer 214 without compromising (increasing) the resistance of the SOT layer 210 to read and write currents. In addition, etching the structure 800 results in the SOT layer 210 not covering the strips 406 in the structure 900; therefore, the strips 406 can set boundaries for the MRAM 200 as expected.

[0032] At 312, by utilizing dielectric 218 (see Figure 2 ) for packaging and also forming an interconnect layer 220 (see Figure 2) to complete the MRAM 200. One of ordinary skill will be familiar with dielectric materials (eg, silicon oxide, silicon nitride, silicon carbide) and interconnects, their purpose and shape, and appropriate interconnect materials (eg, copper, tungsten, ruthenium, aluminum, silver).

[0033] In one or more embodiments, the dielectric pillar 404 may include a spacer to further improve the thickness uniformity of the stepped SOT layer 210. Fig.10 In the structure 1000 shown, the column 404 may include a convex spacer 1002. On the other hand, in the Fig.11 In the illustrated structure 1100, pillars 404 may include concave spacers 1102. Those of ordinary skill are familiar with methods for forming spacers on the sides of a structure during semiconductor device fabrication.

[0034] Given the discussion thus far, it will be appreciated that, in general, the exemplary magnetic random access memory (MRAM) device 200 includes a magnetic tunnel junction (MTJ) stack 208; a spin-orbit torque (SOT) layer 210 beneath the MTJ stack, wherein the SOT layer has a stepped profile; and a dielectric pillar 404 beneath the SOT layer and the MTJ stack.

[0035] In one or more embodiments, the MTJ stack includes a pinned layer 212, a barrier layer 214, and a free layer 216. Each layer has a horizontal edge, and the edge of the barrier layer has no metal bridges.

[0036] In one or more embodiments, the edge of the MTJ stack protrudes outward beyond the periphery of the dielectric pillar.

[0037] In one or more embodiments, the SOT layer 210 has an upper step 222 directly below the MTJ stack and covering the dielectric pillar, a lower step 224 below and on either side of the upper step, and a riser 226 connecting the lower step to the upper step.

[0038] In one or more embodiments, the dielectric column has a spacer 1002 at its top end, and the spacer imposes a convex shape on the facade. In one or more embodiments, the dielectric column has a spacer 1102 at its top end, and the spacer imposes a concave shape on the facade.

[0039] In one or more embodiments, the lower step of the SOT layer has an upper surface flush with an upper surface of the dielectric pillar, while the upper step of the SOT layer is coextensive with the MTJ stack.

[0040] In one or more embodiments, the lower step of the SOT layer has the same thickness as the upper step of the SOT layer. In one or more embodiments, the facade of the SOT layer has the same thickness as the lower step and the upper step. In one or more embodiments, the upper step and the lower step and the facade are all composed of the same material.

[0041] In one or more embodiments, the device further includes a dielectric substrate 402 surrounding the dielectric pillar and a dielectric strip 406 protruding from the dielectric substrate at an edge of the SOT layer 210 .

[0042] According to another aspect, an exemplary method 300 includes: at 302, forming a dielectric substrate 402 of a first dielectric material and a dielectric pillar 404 of a second dielectric material, wherein the dielectric pillar protrudes from the dielectric substrate; at 304, forming a first intermediate structure by depositing a first conductive material layer 602 onto the dielectric substrate, the first conductive material layer 602 being thick enough to cover the pillar and the substrate; at 306, forming a planarized structure 700 by planarizing the first intermediate structure to expose the pillar; and at 308, depositing a second spin-orbit torque metal layer 802 onto the planarized structure.

[0043] In one or more embodiments, method 300 also includes: at 310, depositing an additional layer onto the second spin-orbit torque metal layer, wherein the additional layer includes a free layer, a barrier layer, and a pinned layer; and forming a magnetic tunnel junction stack on top of the pillar by etching the additional layer and the second spin-orbit torque metal layer around the pillar without a bridge on the edge of the barrier layer.

[0044] In one or more embodiments, the method further comprises etching through the second spin-orbit torque metal layer down to the first spin-orbit torque metal layer. In one or more embodiments, the method further comprises etching into the first spin-orbit torque metal layer.

[0045] In one or more embodiments, etching the additional layer and the second spin-orbit torque metal layer includes etching the additional layer with at least one first ion; and etching the second spin-orbit torque metal layer with a second ion different from any of the at least one first ion.

[0046] In one or more embodiments, the method further comprises: before depositing the first spin-orbit torque metal layer, forming a spacer at the protruding upper end of the pillar. In one or more embodiments, forming the spacer comprises forming a convex spacer. In one or more embodiments, forming the spacer comprises forming a concave spacer.

[0047] According to another aspect, an exemplary magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack 208; and a spin-orbit torque (SOT) layer 210, which is located below the MTJ stack. The SOT layer 210 has an upper step 222 directly below the MTJ stack, and a lower step 224 adjacent to and below the upper step. The upper step includes a spin-orbit torque metal.

[0048] In one or more embodiments, the lower step of the SOT layer includes a spin-orbit torque metal. In one or more embodiments, the upper step and the lower step of the SOT layer have uniform thickness. In one or more embodiments, the upper step of the SOT layer is coextensive with the MTJ stack.

[0049] In one or more embodiments, the device further includes: a dielectric substrate 402 located below the lower step of the SOT layer; and a dielectric pillar 404 protruding from the dielectric substrate below the MTJ stack and the upper step of the SOT layer. In one or more embodiments, the device further includes: a dielectric strip 406 protruding from the dielectric substrate at the edge of the lower step of the MTJ stack.

[0050] The description of various embodiments of the present invention has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A magnetic random access memory (MRAM) device, comprising: Magnetic tunnel junction MTJ stack; A spin-orbit torque SOT layer located below the MTJ stack, wherein the SOT layer has a step-shaped profile; as well as A dielectric pillar is located below the SOT layer and the MTJ stack.

2. The apparatus of claim 1, wherein the MTJ stack comprises a pinned layer, a barrier layer, and a free layer, wherein each layer has a horizontal edge, and wherein an edge of the barrier layer is free of metal bridges. 3 . The apparatus of claim 2 , wherein an edge of the MTJ stack protrudes outward beyond a periphery of the dielectric pillar.

4. The device of claim 1 , wherein the SOT layer includes an upper step directly below the MTJ stack and covering the dielectric pillar, a lower step below the upper step and on either side of the upper step, and a facade connecting the lower step to the upper step.

5. The apparatus of claim 4, wherein the dielectric pillar comprises a spacer at a top end thereof, and wherein the spacer imposes a convex shape on the facade.

6. The apparatus of claim 4, wherein the dielectric pillar comprises a spacer at a top end thereof, and wherein the spacer imposes a concave shape on the facade. 7 . The apparatus of claim 4 , wherein a lower step of the SOT layer has an upper surface flush with an upper surface of the dielectric pillar, and an upper step of the SOT layer is coextensive with the MTJ stack. 8 . The apparatus of claim 7 , wherein a lower step of the SOT layer has the same thickness as an upper step of the SOT layer. 9 . The device of claim 8 , wherein a facade of the SOT layer has the same thickness as the lower step and the upper step.

10. The apparatus of claim 4, wherein the upper step and the lower step and the facade are all composed of the same material.

11. The device according to claim 1, further comprising: a dielectric substrate surrounding the dielectric pillar; as well as A dielectric strip protrudes from the dielectric base at an edge of the SOT layer.

12. A method comprising: forming a dielectric base of a first dielectric material and a dielectric pillar of a second dielectric material, wherein the dielectric pillar protrudes from the dielectric base; forming a first intermediate structure by depositing a first layer of conductive material onto the dielectric substrate, the first layer of conductive material being thick enough to cover the pillars and the substrate; forming a planarized structure by planarizing the first intermediate structure to expose the pillars; as well as A second spin-orbit torque metal layer is deposited onto the planarized structure.

13. The method according to claim 12, further comprising: depositing an additional layer onto the second spin-orbit torque metal layer, wherein the additional layer comprises a free layer, a barrier layer, and a pinned layer; as well as By etching the additional layer and the second spin-orbit torque metal layer around the pillar, a magnetic tunnel junction stack is formed on top of the pillar without a bridge on the edge of the barrier layer.

14. The method according to claim 13, further comprising: Etching through the second spin-orbit torque metal layer down to the first conductive material layer.

15. The method according to claim 14, further comprising: Etching into the first conductive material layer.

16. The method according to claim 13, wherein: Etching the additional layer and the second spin-orbit torque metal layer comprises: etching the additional layer using at least one first ion; and The second spin-orbit torque metal layer is etched using a second ion, the second ion being different from any of the at least one first ion.

17. The method according to claim 13, further comprising: Prior to depositing the first spin-orbit torque metal layer, spacers are formed at the protruding upper ends of the pillars.

18. The method according to claim 17, wherein: Forming the spacers includes forming convex spacers.

19. The method according to claim 17, wherein: Forming the spacers includes forming concave spacers.

20. A magnetic random access memory (MRAM) device comprising: Magnetic tunnel junction MTJ stack; as well as A spin-orbit torque SOT layer is located below the MTJ stack, wherein the SOT layer has an upper step directly below the MTJ stack and a lower step adjacent to and below the upper step, wherein the upper step includes a spin-orbit torque metal. 21 . The apparatus of claim 20 , wherein the lower step of the SOT layer comprises a spin-orbit torque metal. 22 . The apparatus of claim 20 , wherein the upper and lower steps of the SOT layer have uniform thicknesses.

23. The apparatus of claim 20, wherein an upper step of the SOT layer is coextensive with the MTJ stack.

24. The apparatus of claim 20, further comprising: a dielectric substrate located below the lower step of the SOT layer; as well as A dielectric pillar protrudes from the dielectric substrate below the MTJ stack and an upper step of the SOT layer.

25. The apparatus of claim 24, further comprising: A dielectric strip protrudes from the dielectric substrate at an edge of a lower step of the MTJ stack.

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