Broadband supply circuitry for plasma processing systems

Abstract

Embodiments provided herein generally include apparatuses, plasma processing systems, and methods for dynamic impedance matching over multiple frequency bands of a power supply. One example method includes amplifying a broadband signal; separating the amplified broadband signal on a plurality of channel paths coupled with an impedance matching network; and adjusting, based at least in part on feedback associated with the broadband signal, at least one first impedance associated with the impedance matching network to achieve a second impedance within a threshold. The impedance matching network includes a plurality of impedance matching circuits coupled with the plasma excitation circuitry, and each of the impedance matching circuits is coupled with a different one of the plurality of channel paths and an output node.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to systems for semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to plasma processing systems for processing substrates. Background Art

[0002] Reliably forming, processing, and filling high aspect ratio features are some of the key technical challenges for next generation semiconductor devices. High aspect ratio openings for forming features are often formed using plasma-assisted processes, such as a reactive ion etching (RIE) process that enables directionally controlled (i.e., anisotropic) material removal to transfer a pattern from a mask layer to exposed portions of the substrate surface beneath it. Similarly, other key processes that utilize plasmas include physical vapor deposition (PVD) and plasma enhanced chemical vapor deposition (PECVD) processes, which often utilize plasma-generated ions to re-sputter and / or reshape deposited material layers as the substrate surface is bombarded with plasma-generated ions. As feature sizes continue to shrink and pattern densities continue to increase, the degree of anisotropy and process uniformity of the RIE, PVD, or PECVD processes are important factors in forming and / or filling closely spaced (fine pitch) high aspect ratio openings.

[0003] For plasma-assisted processes where plasma ions play a major role, ion energy control has always posed a challenge to the semiconductor equipment industry. In a typical plasma-assisted process, a substrate is positioned on a substrate support, such as an electrostatic chuck (ESC) disposed in a processing chamber. During etching processes, and during at least a portion of a PVD or PECVD process, a plasma can be formed above the substrate to enable ions to be accelerated from the plasma toward the substrate through a plasma sheath (i.e., an electron depletion region) formed between the plasma and the substrate surface. Traditionally, RF substrate bias methods that use a single driving radio frequency (RF) frequency sinusoidal waveform to excite the plasma and form the plasma sheath have been unable to ideally form and / or process these smaller device feature sizes with plasma.

[0004] A typical plasma processing chamber includes a radio frequency (RF) bias generator that supplies an RF voltage to a "power electrode" (e.g., bias electrode) (e.g., a metal plate adjacent to an "electrostatic chuck" (ESC) assembly, more commonly referred to as a "cathode"). In a capacitively coupled gas discharge, the plasma is created by using a radio frequency (RF) generator coupled to the RF electrode through an RF matching network ("RF match") that adjusts the apparent load to 50Ω to minimize reflected power and maximize power delivery efficiency. Application of the RF voltage to the power electrode causes an electron-repelling plasma sheath (also referred to as a "cathode sheath") to form over the processing surface of the substrate, which is positioned on the substrate support surface of the ESC assembly during processing. The formed plasma sheath causes rectification of the applied RF field, resulting in a direct current (DC) voltage drop or "self-bias" between the substrate and the plasma, thereby causing the substrate potential to be negative relative to the plasma potential. The resulting voltage drop determines the average energy of the plasma ions accelerated toward the substrate, while the provided RF waveform determines the ion energy distribution function (IEDF) of the plasma ions used in the etching process or at least a portion of the deposition process. In a typical plasma utilizing an RF bias, the IEDF typically has two non-discrete peaks, one at low energy and one at high energy, with the energy range of the ion population of the IEDF extending between the two peaks. The presence of the ion population between the two peaks of the IEDF reflects the fact that the voltage drop between the substrate and the plasma oscillates at the RF bias frequency. In addition, conventional plasma processing systems tend to produce plasma non-uniformity and non-ideal ion energy distribution function (IEDF) due to the interaction of the delivered one or more RF frequencies and / or related harmonics with the complex load formed by the plasma in the process chamber. The non-uniform plasma and non-ideal IEDF will affect the properties of the etching and / or deposition process performed on the substrate, such as the etching profile, etching uniformity, re-sputtering uniformity of the deposited film when the substrate is biased during processing, and the re-sputtering rate. As feature sizes continue to decrease and aspect ratios increase, and the control requirements of feature profiles become more stringent, it becomes more necessary to have a well-controlled IEDF at the substrate surface during the plasma process.

[0005] As the demand for smaller and smaller microelectronic feature sizes increases, there is a need in the field of plasma processing technology to further improve plasma processing technology. Therefore, there is a need for an apparatus and method for processing a substrate that can solve the above-mentioned problems. Summary of the invention

[0006] Embodiments provided herein generally include apparatus for processing a substrate in a plasma processing system, a plasma processing system, and a method. In one example, the plasma processing system includes a physical vapor deposition chamber.

[0007] One embodiment of the present disclosure is directed to a method of processing a substrate in a plasma processing chamber. The method generally includes: amplifying a broadband signal; splitting the amplified broadband signal on a plurality of channel paths coupled to an impedance matching network; and adjusting at least one first impedance associated with the impedance matching network to achieve a second impedance within a threshold value based at least in part on feedback associated with the broadband signal. The impedance matching network includes a plurality of impedance matching circuits coupled to a plasma excitation circuit system, and each of the impedance matching circuits is coupled to a different one of the plurality of channel paths and an output node.

[0008] One embodiment of the present disclosure relates to a plasma processing system. The system generally includes: an amplifier configured to amplify a broadband signal; a filter array coupled to the amplifier and configured to separate the amplified broadband signal on a plurality of channel paths; an impedance matching network including an input side coupled to the channel paths, and an output side, wherein the output side of the impedance matching network includes a plurality of impedance matching circuits coupled to an output node, the output node being configured to couple to an electrode of a plasma processing chamber within the plasma processing system, and each of the impedance matching circuits being coupled to a different path of the plurality of channel paths. The system further includes a memory and a processor coupled to the memory. The processor is configured to: adjust at least one first impedance associated with the impedance matching network to achieve a second impedance within a threshold value based at least in part on feedback associated with the broadband signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to be able to understand the above-mentioned features of the present disclosure in detail, a more detailed description of the present disclosure briefly summarized above can be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate exemplary embodiments and should not be considered as limiting the scope of such embodiments, and other equally effective embodiments are acceptable.

[0010] Figure 1 is a schematic cross-sectional view of a processing system configured to perform the methods described herein, according to one or more embodiments.

[0011] Figure 2A Example voltage waveforms over time are shown according to one or more implementations.

[0012] Figure 2B Shown by Figure 2A An example voltage waveform produced by combining the voltage waveforms described in .

[0013] Figure 3 Example ion energy distribution functions (IEDFs) associated with excitation waveforms generated using three, five, and seven harmonics, respectively, are illustrated.

[0014] Figure 4 is a diagram illustrating an example broadband supply circuit.

[0015] Figure 5 Is the description and Figure 4 Figures related to further aspects of the impedance matching circuitry of the example broadband supply circuit described in.

[0016] Fig. 6A and 6B Example ion populations across the energy spectrum are illustrated for different excitation waveforms including channels with different phase offsets.

[0017] Figure 7 is a process flow diagram illustrating an example method for processing a substrate in a plasma processing chamber.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized in other aspects without specific recitation. DETAILED DESCRIPTION

[0019] As semiconductor manufacturing processes progress toward higher component densities, fabricating smaller features with larger aspect ratios involves atomic precision for most plasma processing processes. Embodiments of the present disclosure describe a biasing scheme configured to provide a radio frequency (RF) generated waveform from a power supply to one or more electrodes within a processing chamber to produce a desired ion energy distribution function (IEDF) at a substrate surface during one or more plasma processing steps performed within the processing chamber. The plasma processes disclosed herein can be used to control the shape of the IEDF, thereby controlling the interaction of the plasma with the substrate surface during processing. In some configurations, the plasma processes disclosed herein are used to control the profile of features formed in the substrate surface during processing.

[0020] Some embodiments of the present disclosure generally relate to techniques and apparatus for dynamic impedance matching in broadband supply circuitry within a power supply for performing a plasma process on a substrate. The broadband supply circuitry can provide multiple frequency band specific impedance matching circuits for a power supply for a plasma processing system using the concept of voltage waveform customization. Impedance matching can be applied to multiple frequency bands to provide a specific impedance for each frequency band. For example, the broadband circuitry can adjust the impedance associated with each of a plurality of impedance matching circuits, where each impedance matching circuit is for a different frequency band.

[0021] Techniques and apparatus for dynamic impedance matching described herein can provide various advantages for capacitively coupled plasma processes such as etching, physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), or plasma enhanced chemical vapor deposition (PECVD) processes. For example, techniques and apparatus for dynamic impedance matching described herein can allow for individual control of average ion energy and flux using phase control of a radio frequency signal applied to one of the electrodes disposed in a plasma processing chamber. In one example, the radio frequency signal is applied to an electrode disposed within a substrate support on which the substrate is placed during processing. Techniques and apparatus for dynamic impedance matching described herein can allow for control of the shape of the ion energy distribution function (IEDF), which in turn can achieve selectivity in etching and / or deposition, improved feature shaping, and improved process uniformity. Techniques and apparatus for dynamic impedance matching described herein can allow for control of the electron energy distribution function (EEDF). Techniques and apparatus for dynamic impedance matching can achieve control of plasma uniformity, for example, due to efficient and accurate power delivery to the excitation circuitry of the plasma processing system.

[0022] Examples of Plasma Processing Systems

[0023] Although it is not intended to limit the scope of the disclosure provided herein, the apparatus and methods described herein include a dynamic impedance matching system that is connected to and / or disposed within a PVD type plasma processing chamber. However, the dynamic impedance matching system disclosed herein and the methods using the system may also be used in other similarly configured types of plasma processing chambers, such as dry etching chambers (e.g., RIE chambers), PECVD processing chambers, plasma enhanced atomic layer deposition (PEALD) chambers, plasma doping (PLAD) chambers, or other plasma processing chambers that require biasing of a substrate during one or more stages of a plasma process performed therein.

[0024] Figure 11 is a schematic cross-sectional view of a plasma processing system 100 configured to perform one or more plasma processing methods (e.g., PVD deposition processes) described herein. The plasma processing system 100 may include a processing chamber 102. In one embodiment, the processing chamber 102 is adapted to deposit a suitable sputtered film on a surface of a substrate 104. The processing chamber 102 includes a vacuum chamber 106, a target 108, a magnetron 110, a vacuum pumping system 112, a substrate support assembly 114, and a process kit 116. The vacuum chamber 106 supports the target 108, which is sealed at one end of the vacuum chamber 106 by a target isolator 118 using a plurality of O-rings. The target 108 has at least one surface portion composed of a material to be sputter-deposited on the substrate 104, which is disposed on the substrate support assembly 114. As an example, the target 108 may include any of a variety of sputtering materials, such as a sputtering metal, a sputtering alloy, or a sputtering compound. In some cases, the sputtering material of the target can include aluminum, copper, tungsten, cobalt, silver, gold, carbon, iron, titanium, or a combination thereof. In some cases, the sputtering material of the target can include other types of materials, such as various metal oxides, metal nitrides, or silicon.

[0025] The magnetron 110 disposed adjacent to and rotating relative to the target 108 includes a plurality of magnets 122A, 122B that are used to confine a plasma "P" generated in a processing region 124 by biasing the target 108 using a first power source 126 to "sputter" material from a target surface 128. The first power source 126 will typically include a direct current (DC) power source and / or a radio frequency power source configured to apply a desired amount of bias to the target 108 to enable sputtering of target material and / or to maintain a plasma "P" formed in the processing region 124 disposed between the substrate 104 and the target 108. It should be understood that the type of magnetron may vary depending on the particular PVD application.

[0026] In other non-PVD type plasma processing systems, the processing chamber 102 may include a different configuration of the upper portion of the processing chamber 102. For example, when the processing chamber 102 is adapted to perform a PECVD process, a RIE process, or a PEALD process, Figure 1 The illustrated magnetron 110 and target 108 would typically be replaced by a plate electrode (not shown) or showerhead (not shown) positioned above the substrate support assembly 114 and configured to distribute one or more process gases (e.g., precursor or etchant gases) to a processing region 124 of the processing chamber 102 during processing.

[0027] The vacuum pumping system 112 generally includes a pump assembly 134 and a valve 136. The pump assembly 134 generally may include a cryopump (not shown) and a primary pump (not shown) for maintaining a specific pressure in the processing region 124 of the processing chamber 102.

[0028] The substrate support assembly 114 may include a substrate support pedestal 138, which may include a pedestal electrode 140 and an electrostatic chuck 142 having a support surface adapted to support the substrate 104 above the pedestal electrode 140. It should be understood that other devices may be used to hold the substrate 104 in place during processing. Resistive heaters (not shown), cryogen channels (not shown), and thermally conductive gas chambers (not shown) may be formed in the substrate support pedestal 138 to provide thermal control of the substrate 104 during processing. In some applications, as will be further discussed below, the pedestal electrode 140 is coupled to a second power supply 144 so that a bias voltage can be supplied to the substrate 104 to attract ions generated in the plasma "P". The second power supply 144 includes a broadband supply circuit system to dynamically adjust the impedance matching applied to the electrodes (e.g., the pedestal electrode 140) within the substrate support 114 over multiple frequency bands, as described herein. Figure 4-7 Further description of .

[0029] The process kit 116 may generally include a cover ring 146, a darkspace shield 148, and a chamber shield 150, which are separated by a dielectric shield isolator 152. The process kit 116 components are positioned within the vacuum chamber 106 to protect the chamber wall 154 (which typically includes electrically grounded metal) from the sputtered material generated in the processing area 124. The darkspace shield 148 may be allowed to float electrically, while the chamber shield 150 may be electrically grounded. However, in some aspects, either or both shields may be grounded, floated, or biased to the same or different non-ground levels. The shields 148, 150 are typically composed of stainless steel, and their respective inner sides 156 may be bead blasted or otherwise roughened to promote adhesion of the material deposited thereon by sputtering. However, during long-term sputtering, at some point, the deposited material will accumulate to a certain thickness and is likely to flake off, thereby generating harmful particles. Before this point is reached, the shields 148, 150 may be cleaned or replaced.

[0030] The plasma process performed in the processing chamber 102 may include one or more steps in which: 1) a deposition process is performed primarily on a substrate; 2) a process in which both deposition and partial etching of a deposited thin film layer occur simultaneously; or 3) a process in which etching occurs primarily on a surface of a substrate or a deposited thin film layer. The apparatus and process described herein may be used to adjust the plasma uniformity above the substrate 104 and to adjust the sheath formed above the substrate 104 to control the IEDF of ions interacting with the substrate during one or more steps of a process performed in the processing chamber 102. In some embodiments, a direct current (DC), pulsed direct current, radio frequency, and / or pulsed radio frequency bias signal may be applied to the pedestal electrode 140 by the second power supply 144 while the target 108 is biased by the first power supply 126. It has been found that such a signal may significantly improve etching, deposition, or re-sputtering of a deposited layer, or forming features in a substrate surface during an etching process. In some embodiments, for example, to attract ions generated by the plasma to the substrate 104, the electrode 140 may be biased by the second power supply 144 to provide an average power of 1 to 5 kilowatts. The DC and / or RF bias signal applied to the electrode 140 may include a signal having a plurality of alternating first intervals and second intervals, wherein during each first interval, the voltage of the applied bias signal is negative to attract ions to the substrate, and during the alternating second intervals, the applied bias signal is positive to dissipate charge accumulation accumulated during the first intervals. In some configurations, during the deposition process, the pedestal electrode 140 is negatively biased by the second power supply 144 at a negative voltage of zero to -1000 volts, such as approximately -300 VDC, to negatively bias the substrate 104 to attract ionized deposition material to the substrate 104.

[0031] The processing system 100 may also include a system controller 120. The system controller 120 (also referred to herein as a processing chamber controller) includes a processor 162, a memory 164, and a circuit system 166. The system controller 120 is used to control a process sequence for processing the substrate 104, including performing certain aspects of spectral impedance matching as further described herein. The processor 162 may include a general-purpose computer processor that is configured for use in an industrial environment to control a processing chamber and sub-processors associated therewith. The processor 162 may include a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, which are designed to perform the functions described herein. The processor 162 is coupled to the memory 164. The memory 164, which is generally a non-volatile memory described herein, may include a random access memory, a read-only memory, a floppy disk or hard disk drive, or other suitable forms of local or remote digital storage. Circuitry 166 is conventionally coupled to processor 162 and includes caches, clock circuits, input / output subsystems, power supplies, and the like, as well as combinations thereof. Software instructions (e.g., executable instructions) and data may be encoded and stored in memory 164 for directing processor 162. A software program (or computer instructions) readable by processor 162 in system controller 120 determines which tasks are executable by components in processing system 100.

[0032] Generally, the program readable by the processor 162 in the system controller 120 includes code that, when executed by the processor 162, performs the methods related to the plasma processing schemes described herein. The code may include executable instructions for controlling various hardware and electrical components within the processing system 100 to perform various process tasks and various process sequences for implementing the methods described herein. In some aspects, the code includes instructions for performing the methods described herein in conjunction with Figure 7 In some aspects, the system controller 120 can communicate with the first power source 126 and / or the second power source 144 to control the output signals generated by the first power source 126 and / or the second power source 144.

[0033] The first gas source 168 provides a process gas or sputtering working gas, for example, a chemically inert gas such as argon (Ar), to the vacuum chamber 106 through a mass flow controller 170. In some aspects, the system controller 120 can communicate with the mass flow controller 170 to control the flow rate of the working gas supplied to the processing chamber 102. The working gas can enter the top of the vacuum chamber, or as shown, enter the bottom thereof, either using one or more inlet pipes penetrating through holes in the bottom of the chamber shield 150, or through gaps between the chamber shield 150, the electrostatic chuck 142, and the substrate support base 138. In some aspects, during the reactive PVD process, the process gas can also include a nitrogen-containing gas delivered from a second gas source 172 to form a nitride-containing layer, such as aluminum nitride, on the substrate 104. In a plasma processing configuration where etching is to be performed, a reactive etching gas can be supplied to the processing region 124 of the processing chamber 102 by the first gas source 168.

[0034] Broadband supply circuit system

[0035] Certain embodiments of the present disclosure are generally directed to techniques and apparatus for dynamically impedance matching over multiple frequency bands of a power supply for a plasma processing system (e.g., a PVD processing system). In some embodiments, a broadband supply circuit system disposed within a second power supply 144 described below is configured to dynamically adjust a bias voltage applied to a substrate 104 disposed on a substrate support pedestal 138. The applied bias voltage includes multiple frequency bands that are dynamically impedance matched.

[0036] Voltage Waveform Tailoring (VWT) is a technique for generating a customized voltage waveform based on the Fourier series of harmonics of a fundamental frequency. The drive voltage waveform can be realized as the Fourier series of N consecutive harmonics of a fundamental frequency (f) according to the following expression:

[0037]

[0038] where N is the number of consecutive harmonics of the fundamental frequency f, φ k is the amplitude of a given harmonic; θ k is the phase angle of a given harmonic. The total amplitude of the waveform (φ tot ) can be determined as follows:

[0039]

[0040] The customized voltage waveform signal formed by the VWT can be applied to the excitation circuitry of the PVD processing system, such as the electrode 140 disposed within the substrate support pedestal 138. The customized voltage waveform signal can be formed by adjusting the phase and / or amplitude of the harmonics to control the sheath and ion flux energy in the processing chamber.

[0041] Figure 2A An example voltage waveform signal as a function of time is illustrated that may be applied to a plasma (e.g., a composite load) by a power supply coupled to one or more electrodes (e.g., electrode 140) disposed within a plasma processing chamber. In this example, the duty cycle of the first voltage waveform 202 may be thirty percent and the duty cycle of the second voltage waveform 204 may be seventy percent. The voltage waveforms 202, 204 are examples of waveforms that may be used for voltage waveform customization.

[0042] Figure 2B Explained by Figure 2A 2. In this example, the phase and amplitude of the voltage waveforms 202, 204 may be adjusted so that the sum of the voltage waveforms 202, 204 may produce the voltage waveform 206 with voltage waveform customization applied.

[0043] Figure 3 Example ion energy distribution functions (IEDFs) 302a-c associated with excitation waveforms generated with three, five, and seven harmonics, respectively, are illustrated. In this example, the three-harmonic waveform provides an IEDF 302a with a minimum peak at higher impact energies. The five-harmonic waveform provides an IEDF 302b with a peak at an impact energy between the three-harmonic waveform and the seven-harmonic waveform. The seven-harmonic waveform can provide an IEDF 302c with a maximum peak at the lowest impact energy. It will be appreciated that VWT can be used to customize the IEDF of a plasma processing system (such as a PVD system). In some aspects, the three-harmonic waveform can be used due to the lower complexity and cost of manufacturing circuit systems that support more harmonics.

[0044] Certain aspects of VWT may be extended to controlling impedance matching of power circuitry of a plasma processing system, such as second power supply 144. For example, the power circuitry may include impedance matching circuits for certain harmonics that may be used to form (or constitute) an ignition signal.

[0045] Figure 4 4 is a diagram illustrating an example broadband supply circuit 400. The broadband supply circuit 400 may be a circuit as described herein. Figure 1 Examples of any power source described, such as the second power source 144. In this example, the broadband supply circuit 400 may include a signal generator 402, a power amplifier 404, and an impedance matching circuit system 406. The broadband supply circuit 400 may be coupled to an electrode (e.g., electrode 140) disposed within a processing chamber 408 (e.g., processing chamber 102).

[0046] The signal generator 402 may include a device for creating an electronic signal, which may have a specific waveform (e.g., a sine wave, a square wave, a sawtooth, etc.). In some cases, the signal generator 402 may output a broadband signal having a broadband band (e.g., a frequency band having multiple harmonics or frequency channels). For example, the broadband signal may include a fundamental frequency of 13.56 MHz, a second harmonic frequency of 27.12 MHz, and a third harmonic frequency of 40.68 MHz (or any combination of channels and / or harmonics). The signal generator 402 may include a waveform generator, a radio frequency (RF) signal generator, and / or a DC voltage supply. The waveform generator may generate a pulse waveform signal, wherein a radio frequency signal is superimposed by a radio frequency signal generator, and a DC voltage supply may output a DC bias voltage for the pulse waveform signal. In some embodiments, the signal generator 402 includes at least a radio frequency signal generator, which is configured to adjust the amplitude, frequency, and waveform of the output signal. The signal generator 402 may be coupled to the power amplifier 404 and the impedance matching circuit system 406 via a first signal path 410. Signal generator 402 may output a signal to an input of power amplifier 404 and an input of impedance matching circuitry 406 via a first signal path 410 .

[0047] The power amplifier 404 may include a high-power broadband power amplifier. For example, the power amplifier 404 may be configured to amplify the signal to a power of 3 kilowatts (kW) or more over a spectrum of 1 to 100 megahertz (MHz). The power amplifier 404 may be coupled between the signal generator 402 and the impedance matching circuit system 406. The power amplifier 404 may obtain a signal output from the signal generator 402 via a first signal path 410 and output the amplified signal to the impedance matching circuit system 406 via a second signal path 412. In some configurations, the synchronization signal is provided from the signal generator 402 to the impedance matching circuit system 406 via a communication signal path 411, and / or via a similar communication signal path (e.g., Figure 5 Path 411 in is provided to the system controller 120.

[0048] Impedance matching circuitry 406 may include circuitry for separating the amplified signal received from path 412 into multiple frequency channels (eg, harmonic channels), and an impedance matching network, as described herein. Figure 5406. The impedance matching circuit system 406 may also obtain the signal output from the signal generator 402 and use the signal in determining how to adjust the impedance matching applied to the impedance matching network. The impedance matching circuit system 406 is coupled between the power amplifier 404 and the processing chamber 408. The impedance matching circuit system 406 may output the excitation signal applied to the electrode (e.g., electrode 140) within the processing chamber through an output node 415 disposed along a third signal path 414.

[0049] The processing chamber 408 may include a plasma processing chamber, such as Figure 1 4. In some aspects, a capacitively coupled plasma (CCP) in a processing chamber 408 can be modeled as a composite load 421 having an inductor 416, a capacitor 418, and a resistor 420, wherein the inductor 416 is coupled in series with a capacitive load including the capacitor 418 coupled in parallel with the resistor 420. The capacitor 418 can represent a high frequency (RF) reactive component of the complex impedance, while the resistor 420 can represent a low frequency (e.g., DC) resistive component of the complex impedance. As an example, the inductor 416 can be 100 nanohenry (nH), the capacitor 418 can be 400 picofarads (pF), and the resistor 420 can be 300 ohms.

[0050] Figure 5 Is the description and Figure 4 4. The impedance matching circuit system 406 of the example broadband supply circuit 400 described in FIG. 4 may include a filter array 522, an impedance matching network 524, a first sensor 526, and a second sensor 528. The impedance matching circuit system 406 may also include a processor and a memory, such as the processor 162 and the memory 164 included in the system controller 120.

[0051] The filter array 522 can be a filter bank with multiple filters 522a-n coupled in parallel to each other. The filter array 522 can be used as a channelizer, wherein the filter array 522 includes a group of parallel bandpass filters (or a combination of low-pass filters, bandpass filters and high-pass filters) that separate the input broadband signal into a group of narrow sub-bands or channels. As an example, any one of the filters 522a-n can include an inductor-capacitor (LC) filter. The filter array 522 is coupled to the amplifier via the second signal path 412. The filter array 522 is configured to separate the amplified signal output from the power amplifier 404 on multiple channel paths 530a-n, wherein each of the channel paths 530a-n can correspond to a different frequency channel or sub-band. Each of the filters 522a-n can be configured to allow a specific frequency channel (sub-band) of the amplified signal to pass through and attenuate other frequencies. Each of the filters 522a-n can be configured as a bandpass (notch) filter with different center frequencies. In some cases, the center frequencies and / or passbands of filters 522a-n may include harmonics of a particular fundamental frequency, such that subbands or channels associated with channel paths 530a-n may include corresponding harmonics.

[0052] The broadband signal can be separated into any number of harmonics or frequency channels, such as two harmonics or channels, three harmonics or channels, five harmonics or channels, or seven harmonics or channels, for example, as described herein. Figure 3 Description. For example, filter 522a-n may include three filters, wherein the center frequency of the first filter is 13.56MHz, the center frequency of the second filter is 27.12MHz, and the center frequency of the third filter is 40.68MHz. In some cases, the broadband signal can be separated into any combination of harmonics or frequency channels. For example, the broadband signal can be separated into a fundamental frequency (such as 13.56MHz) and a second harmonic (such as 27MHz), separated into a fundamental frequency (such as 13.56MHz) and a third harmonic (such as 40MHz), or separated into a fundamental frequency (such as 13.56MHz) and a higher order channel (such as 60MHz). In some cases, the filter associated with the lowest channel (e.g., filter 522a) can be configured as a low pass filter, while the filter associated with the highest channel (e.g., filter 522n) can be configured as a high pass filter. In some cases, the filter associated with the lowest channel (e.g., filter 522a) can be configured as a combination of a low pass filter and a band pass filter.

[0053] In certain aspects, different gains and / or phase shifts applied to the harmonics of the broadband signal output from the power amplifier 404 by the filter array 522 may allow the application of VWT to form the signal described herein. Figure 2A ,2B and 3. Each of the filters 522a-n can be configured to apply a certain gain and / or a certain phase shift to a harmonic or channel associated with the broadband signal output from the power amplifier 404. For example, the filters 522a-n can include three filters, wherein the first filter can have a first gain and / or a first phase shift (e.g., a phase shift of 0 degrees) applied to the first harmonic (e.g., 13.56 MHz), the second filter can have a second gain and / or a second phase shift (e.g., a phase shift of 90 degrees) applied to the second harmonic (e.g., 27.12 MHz), and the third filter can have a third gain and / or a third phase shift (e.g., a phase shift of 165 degrees) applied to the third harmonic (e.g., 40.68 MHz).

[0054] In some aspects, different or separate phase shifts can be applied to different harmonics or channels by filters 522a-n. The separate phase shifts applied at filters 522a-n can enable impedance matching circuit system 406 to control the ion energy distribution associated with the excitation waveform applied to the electrode (e.g., electrode 140). For example, impedance matching circuit system 406 can apply a first set of phases at filters 522a-n for deposition operations, and apply a second set of phases at filters 522a-n for etching operations. In some cases, impedance matching circuit system 406 may include multiple groups of filters 522a-n, which have different or separate filter characteristics, such as center frequency or passband, gain and / or phase shift. System controller 120 can select a specific group of filters 522a-n for forming an excitation waveform, for example, by a multiplexer or switch (not shown) coupled between PA 404 and filters 522a-n.

[0055] For certain aspects, the phase shift may be applied in stages, where the PA 404 may apply a first phase shift (e.g., a fine phase shift) and the filters 522a-n may apply a second phase shift (e.g., a coarse phase shift). The system controller 120 may control the phase shift applied at the PA 404, for example, via a phase control signal 548. The phase control signal 548 may indicate the phase shift applied at the PA 404.

[0056] The impedance matching network 524 may include a plurality of impedance matching circuits 532a-n, wherein each of the impedance matching circuits 532a-n is coupled to a different path (e.g., a different harmonic sub-band) in the plurality of channel paths 530a-n. The impedance matching network 524 may include an input side coupled to the channel paths 530a-n, and an output side. The output side of the impedance matching network 524 may include impedance matching circuits 532a-n, which are coupled to an output node 415 (which corresponds to the third signal path 414, for example). In some cases, a DC offset may be applied to the output node 415 to provide a DC bias for the excitation waveform. For example, a DC power supply 550 may be coupled to the output node 415, and the DC power supply 550 may output a DC offset signal. The output node of the broadband supply circuit may be configured to be coupled to an excitation circuit system (e.g., a target 108 and / or an electrode 140) of the plasma chamber 408.

[0057] As shown, the impedance matching circuit 532a may include various circuit systems having a composite output impedance that can match the input impedance of the plasma excitation circuit system associated with the plasma chamber 408. Any of the other impedance matching circuits 532b-n may have similar circuit systems or the same circuit systems as described herein for the impedance matching circuit 532a. The impedance matching circuit 532a may include a first capacitor 534, a first inductor 536, a second capacitor 538, and a second inductor 540, wherein the first capacitor 534 and the first inductor 536 may be coupled in series to a branch coupled to the input node, and the second capacitor 538 and the second inductor 540 may be coupled in series between the input node and the output node. In some cases, the various circuit systems of the impedance matching circuit 532a may have one or more variable or adjustable properties, such as resistance, inductance, capacitance, reactance, and / or impedance. For example, the capacitors 534, 538 may include variable capacitors, such as (high voltage) vacuum variable capacitors, variable reactors (varactors), or variable capacitance diodes (varicaps). The system controller 120 can adjust the impedance of the impedance matching circuit 532a (e.g., via a variable capacitor) to match the input impedance of the plasma ignition circuitry, as further described herein. Each of the impedance matching circuits 532a-n can be dynamically configured (e.g., adjusted) to match the input impedance of the plasma ignition circuitry in response to feedback. Each of the impedance matching circuits 532a-n can be configured and / or adjusted to have a different complex impedance to facilitate efficient delivery of power to the plasma chamber 408 at various harmonics of a broadband signal.

[0058] The processor 162 may be configured to adjust at least one first impedance associated with the impedance matching network 524 to meet a threshold associated with a second impedance of the plasma ignition circuit system based at least in part on feedback associated with the signal. The first impedance may include an output impedance associated with each of the impedance matching circuits 532a-n. The second impedance may include an input impedance of the plasma ignition circuit system, such as the impedance of the composite load 421. The threshold may correspond to a difference between the first impedance and the second impedance, such as plus or minus (±) a certain percentage difference (±5%). If the difference between the first impedance and the second impedance is within a certain percentage difference of the second impedance (e.g., ±5% or 10%), the first impedance may meet the threshold.

[0059] Feedback associated with the signal may include measurements obtained from the first sensor 526 and / or the second sensor 528 through the first feedback path 542 and the second feedback path 544, respectively. Each first sensor 526 may be coupled to a different path in the channel path 530a-n to allow individual measurement of harmonics. The second sensor may be coupled to the third signal path 414 to measure the output of the impedance matching network 524. Feedback may also include a synchronization signal from the signal generator 402 obtained through the first communication signal path 411. The synchronization signal may indicate the time when the waveform changes, such as a pulse, a radio frequency waveform, a rise or fall. Measurements from the first sensor 526 and / or the second sensor 528 may include one or more properties associated with the sub-band and / or broadband signal of the signal. For example, the measurement may include any one of voltage, current, phase, amplitude and / or power.

[0060] The feedback may enable the processor 162 to evaluate the performance of the impedance matching network 524, and the processor 162 may adjust the output impedance of each of the impedance matching circuits 532a-n to provide a specific output impedance for each frequency band. The feedback may indicate that the broadband supply circuit is receiving electrical reflections from the plasma chamber 408. For example, the power increase exhibited on the third signal path 414 may indicate electrical reflections, thereby indicating an impedance mismatch. In response to the feedback, the processor 162 may adjust the output impedance of the specific impedance matching circuit 532a-n. For example, the processor 162 may output a control signal through a control path 546 coupled to each of the impedance matching circuits 532a-n. In some aspects, the control path 546 may include a separate control path for each of the impedance matching circuits 532a-n. The control signal may indicate an impedance adjustment for the specific impedance matching circuit 532a-n. As an example, assuming that the variable capacitors 534, 538 are voltage controlled, the control signal may be a voltage signal coupled to the variable capacitor of the impedance matching circuit such that the capacitance of the capacitors 534, 538 depends on the voltage level of the control signal.

[0061] Fig. 6A and 6B Example ion populations across the energy spectrum are illustrated for different excitation waveforms including channels with different phase offsets. Fig. 6A , curve 602 is associated with an excitation waveform formed by two signals in different channels (e.g., 13.56 MHz and 60 MHz) having the same phase (e.g., 0 degrees). In this example, the ion population is within a very narrow range of values ​​across the energy spectrum, allowing for a relatively uniform ion distribution across the energy spectrum.

[0062] refer to Figure 6B , curve 604 is associated with an excitation waveform formed by two signals in different channels (e.g., 13.56 MHz and 60 MHz) having a phase offset of 165 degrees. For example, the phase of the first signal may be 0 degrees and the phase of the second signal may be 165 degrees. In this example, the ion group has a peak at a certain energy level, thereby allowing the ions to be concentrated at such an energy level. Fig. 6A and 6B It is shown that phase control can enable the impedance matching circuit system described herein to control the ion energy distribution produced by the excitation waveform. In certain aspects, the phase control described herein can allow the impedance matching circuit system to select the ion energy distribution produced by the excitation waveform, for example, based on a specific plasma processing operation (such as a deposition operation or an etching operation).

[0063] Figure 7 7 is a process flow diagram illustrating an exemplary method 700 for processing a substrate in a physical vapor deposition chamber. The method 700 may be performed by a processing system (such as the processing system 100) using a broadband supply circuit (such as the broadband supply circuit 400).

[0064] Method 700 may optionally begin with activity 702 , where a processing system may amplify a broadband signal, for example, with an amplifier such as power amplifier 404 .

[0065] At activity 704, the processing system may separate the amplified broadband signal on a plurality of channel paths coupled to an impedance matching network (e.g., impedance matching network 524), wherein each channel path is coupled to a separate impedance matching circuit of the impedance matching network. As an example, the amplified signal may be separated into certain harmonic channels (or sub-bands) using a filter array (e.g., filter array 522). The processing system may separate the amplified signal by a filter array configured as a channelizer. The filter array may include a plurality of bandpass filters arranged in parallel. In some cases, the filter array may include a low-pass filter, a bandpass filter, and a high-pass filter arranged in parallel. As described herein, the amplified signal may be separated into channels associated with harmonics of the fundamental frequency (e.g., harmonics including 13.56 MHz, 27.12 MHz, and 40.68 MHz).

[0066] At activity 706, the processing system can adjust at least one first impedance (e.g., output impedance) associated with the impedance matching network to achieve a second impedance (e.g., equivalent to the input impedance of the composite load 419) within a threshold value based at least in part on feedback associated with the broadband signal. In some cases, the first impedance can be adjusted to match the second impedance within a threshold value (e.g., ±5% or 10%). The impedance matching network includes a plurality of impedance matching circuits (e.g., impedance matching circuits 532a-n) coupled to the plasma excitation circuit system, and each of the impedance matching circuits is coupled to a different one of the plurality of channel paths and an output node (e.g., output node 415).

[0067] In some aspects, the filter array can apply some gain and / or some phase shift to the broadband signal. The filter array can apply a phase shift to at least one channel path, for example, as described herein with respect to Figure 6B Description of . The channel paths can have the same or different phase offsets applied by the filter array. The filter array can apply a specific gain (e.g., power gain, voltage gain, and / or current gain) to at least one channel path.

[0068] In certain aspects, the processing system can adjust the first impedance in response to feedback, for example, when the feedback indicates that reflections from the plasma chamber, overvoltage and / or overcurrent occur at the output of the impedance matching network due to impedance mismatch. The feedback can include one or more first measurements on the plurality of channel paths (e.g., by the first sensor 526a-n) and / or one or more second measurements associated with the output of the impedance matching network (e.g., by the second sensor 528). The measurements can include any of a voltage, current, phase, amplitude and / or power associated with the corresponding signal. The feedback can further include a synchronization signal of the signal generator, for example, via the communication signal path 411.

[0069] The processing system may obtain feedback through at least a plurality of first electrical sensors (e.g., first sensors 526a-n) and / or second electrical sensors (e.g., second sensor 528). Each of the plurality of first electrical sensors may be coupled in series between a different one of the channel paths (e.g., channel paths 530a-n) and a different one of the impedance matching circuits (e.g., impedance matching circuits 532a-n). The second electrical sensor may be coupled to the output of the impedance matching network.

[0070] For certain aspects, to adjust the first impedance, the processing system may tune / adjust passive electrical components (e.g., capacitors, resistors, and / or inductors) associated with at least one impedance matching circuit. The passive electrical components may include variable capacitors, variable resistors, variable inductors, or combinations thereof.

[0071] In certain aspects, the adjustment at activity 706 can be performed for each impedance matching circuit associated with a channel path and / or for a particular impedance matching circuit associated with a particular channel path. The processing system can adjust a third impedance associated with at least one impedance matching circuit to meet a threshold associated with a second impedance corresponding to at least one channel path. For example, the third impedance can be an output impedance of the impedance matching circuit 532a to achieve a certain impedance (e.g., 50 ohm impedance) at the composite load of the plasma excitation circuit system.

[0072] The impedance matching network can be configured to couple to a single component of the plasma ignition circuitry. For example, the processing system can couple the output of the impedance matching network to a single electrode (e.g., electrode 140) of the plasma ignition circuitry. In some other cases, the processing system can additionally couple the output of the impedance matching network to an electrode disposed near or within a substrate support disposed within a plasma processing chamber (e.g., a PVD chamber). In some embodiments, the plasma processing system can include a plurality of broadband supply circuits 400 (not shown), each having an output coupled to an electrode disposed within the processing chamber.

[0073] Techniques and apparatus for dynamic impedance matching described herein can provide various advantages for capacitively coupled plasma processes such as CCP etch chambers and PVD chambers. It will be appreciated that the techniques and apparatus described herein can allow efficient and accurate power delivery to electrodes disposed within a plasma processing system, for example, through harmonic specific impedance matching. Techniques and apparatus described herein can prevent overheating, overcurrent, and / or overvoltage at RF supply circuitry.

[0074] The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C can still be considered coupled to each other - even if objects A and C are not directly physically touching each other. For example, a first object can be coupled to a second object even if the first object has never directly come into physical contact with the second object.

[0075] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the following claims.

Claims

1. A method for processing a substrate in a plasma processing chamber, the method comprising: Amplify broadband signals; separating the amplified broadband signal on a plurality of channel paths coupled to an impedance matching network; as well as Based at least in part on feedback associated with the broadband signal, adjusting at least one first impedance associated with the impedance matching network to achieve a second impedance within a threshold, wherein: The impedance matching network includes a plurality of impedance matching circuits coupled to the plasma excitation circuit system, and Each of the impedance matching circuits is coupled to a different one of the plurality of channel paths and an output node.

2. The method of claim 1, wherein the feedback comprises one or more first measurements on the plurality of channel paths and one or more second measurements associated with an output of the impedance matching network.

3. The method of claim 2, wherein the feedback further comprises one or more third measurements of the wideband signal.

4. The method of claim 1 , wherein separating the amplified broadband signal comprises: The amplified broadband signal is separated by a filter array.

5. The method of claim 4, wherein separating the amplified broadband signal comprises: A phase shift is applied to at least one of the channel paths by the filter array.

6. The method of claim 4, wherein separating the amplified broadband signal comprises: Gain is applied to at least one of the channel paths through the filter array.

7. The method of claim 1 , wherein adjusting at least one first impedance associated with the impedance matching network comprises: Passive electrical components associated with at least one of the impedance matching circuits are adjusted.

8. The method of claim 7, wherein the passive electrical component comprises a variable capacitor, a variable resistor, a variable inductor, or a combination thereof.

9. The method of claim 1, further comprising: The feedback is obtained by at least a plurality of first electrical sensors and a second electrical sensor, wherein each of the plurality of first electrical sensors is coupled in series between a different one of the channel paths and a different one of the impedance matching circuits, and the second electrical sensor is coupled to an output of the impedance matching network.

10. The method of claim 1, wherein adjusting the at least one first impedance associated with the impedance matching network comprises: A third impedance associated with at least one of the impedance matching circuits is adjusted to meet the threshold associated with the second impedance corresponding to at least one of the channel paths.

11. The method of claim 1, further comprising: An output of the impedance matching network is coupled to a single electrode of the plasma ignition circuitry.

12. The method of claim 1, wherein the plasma processing chamber comprises a physical vapor deposition chamber, and the method further comprises: An output of the impedance matching network is coupled to an electrode disposed proximate a substrate supporting surface of a substrate support within the physical vapor deposition chamber.

13. A plasma processing system, comprising: an amplifier configured to amplify a broadband signal; a filter array coupled to the amplifier and configured to separate the amplified broadband signal on a plurality of channel paths; an impedance matching network including an input side coupled to the channel path, and an output side, wherein the output side of the impedance matching network includes a plurality of impedance matching circuits coupled to an output node configured to be coupled to a plasma excitation circuit system of the plasma processing system, and each of the impedance matching circuits is coupled to a different one of the plurality of channel paths and the output node.

14. The system of claim 13, further comprising: Memory; as well as A processor is coupled to the memory, the processor being configured to adjust at least one first impedance associated with the impedance matching network to achieve a second impedance within a threshold based at least in part on feedback associated with the broadband signal.

15. The system of claim 13, wherein the filter array is configured to apply a phase shift to at least one of the channel paths.

16. The system of claim 13, wherein the filter array is configured to apply gain to at least one of the channel paths.

17. The system of claim 14, wherein to adjust at least one first impedance associated with the impedance matching network, the processor is configured to adjust a passive electrical component associated with at least one of the impedance matching circuits.

18. The system of claim 17, wherein the passive electrical component comprises a variable capacitor, a variable resistor, a variable inductor, or a combination thereof.

19. The system of claim 14, wherein: The processor is further configured to obtain the feedback at least through a plurality of first electrical sensors and a second electrical sensor, Each of the plurality of first electrical sensors is coupled in series between a different one of the channel paths and a different one of the impedance matching circuits, and The second electrical sensor is coupled to an output of the impedance matching network.

20. The system of claim 13, wherein the plasma processing system comprises a plasma processing chamber and the output of the impedance matching network is coupled to an electrode disposed proximate a substrate supporting surface of a substrate support disposed within the plasma processing chamber.

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