Semiconductor wafer, semiconductor device, power conversion device, and cooling system

Abstract

The purpose of the present disclosure is to provide a technique capable of suppressing cracks from extending to the lower side of an interlayer insulating film when an external stress accompanying a thermal shrinkage stress acts on a corner portion of a semiconductor element. A semiconductor wafer (1) is provided with a semiconductor substrate (10) in which an interlayer insulating film (9) and a surface protection film (8) covering the interlayer insulating film (9) are laminated on the upper surface. A plurality of semiconductor elements (3) cut into small pieces along openings (2a) formed on a surface protection film (8) are formed on a semiconductor substrate (10). The end portion of the interlayer insulating film (9) is set back from the end portion of the surface protective film (8) with respect to the end portion of the semiconductor substrate (10) to be formed by dicing, and the shape of the end portion of the interlayer insulating film (9) is set such that the end portion of the interlayer insulating film (9) is set so that the end portion of each semiconductor element (3) after dicing becomes smaller than the end portion of the surface protective film (8). The distance Lx from the corner of the semiconductor substrate (10) to be formed by dicing to the end of the interlayer insulating film (9) and the thickness (d) of the semiconductor substrate (10) satisfy the relationship of mathematical expression 1.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor wafer, a semiconductor device, a power conversion device, and a cooling system. Background Art

[0002] Patent Document 1 discloses a structure in which an interlayer insulating film and a surface protective film are formed on a semiconductor wafer, and the surface protective film is formed on the interlayer insulating film in a manner that overlaps and covers the interlayer film. For example, in this structure, in addition to the width of the opening of the surface protective film of 80 μm and the groove of the scribe line of 50 μm, the length from the end of the semiconductor element to the surface protective film is 30 μm / 2=15 μm, and the thickness of the product is 180 μm. Prior art literature Patent Literature

[0003] Patent Document 1: Japanese Patent Application Publication No. 2016-225511 Summary of the invention Technical problem to be solved by the invention

[0004] In the technology described in Patent Document 1, since the length from the end of the semiconductor element to the surface protection film is short, about 15 μm, external stress accompanied by thermal shrinkage stress is applied to the end of the semiconductor element, so there is a problem that cracks are easily generated from the surface protection film to the lower side of the interlayer insulating film. If the crack extends to the lower side of the interlayer insulating film, the withstand voltage of the semiconductor element decreases, so the length of the crack becomes important. Even in the end of the semiconductor element, at the four corners, since the external stress accompanied by thermal shrinkage stress becomes large, the withstand voltage of the semiconductor element is easily reduced because the crack extends to the lower side of the interlayer insulating film.

[0005] In addition, such semiconductor elements are mounted on power modules. For example, the power module of the power conversion device mounted on the vehicle is used in a harsh thermal cycle environment with a wider range of operating temperatures (for example, a range of above -40°C and below 150°C) than the power module used indoors. In addition, in a low temperature environment, torque is applied to the motor at startup, so the temperature of the entire drive device rises sharply. Therefore, there is a problem of separation between the sealing resin and the semiconductor element in the power module, resulting in insulation damage of the semiconductor element.

[0006] Therefore, an object of the present disclosure is to provide a technology capable of suppressing the extension of cracks to the lower side of an interlayer insulating film when external stress accompanied by thermal shrinkage stress is applied to a corner portion of a semiconductor element. Technical solutions to technical problems

[0007] The semiconductor chip involved in the present disclosure has a semiconductor substrate with an interlayer insulating film and a surface protection film covering the interlayer insulating film stacked on the upper surface, and a plurality of semiconductor elements cut into small pieces along an opening formed on the surface protection film are formed on the semiconductor substrate. The end of the interlayer insulating film is retreated from the end of the surface protection film relative to the end of the semiconductor substrate to be formed by cutting, and the shape of the end of the interlayer insulating film is set so that in each of the semiconductor elements after cutting, the distance Lx from the corner of the semiconductor substrate to be formed by cutting to the end of the interlayer insulating film and the thickness d of the semiconductor substrate satisfy the relationship of mathematical formula 1. Effects of the Invention

[0008] According to the present invention, since the distance Lx from the corner of the semiconductor substrate to the end of the interlayer insulating film is increased, when external stress accompanied by thermal shrinkage stress is applied to the corner of the semiconductor element, it is possible to suppress cracks from extending to the lower side of the interlayer insulating film.

[0009] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a top view of the semiconductor wafer according to the first embodiment. Figure 2 These are a plan view and a cross-sectional view of a corner portion of a semiconductor element to be formed by dicing in the semiconductor wafer according to the first embodiment. Figure 3 This is a graph showing the relationship between the length of a crack starting from a corner of a semiconductor element and the thickness of the semiconductor element when an external stress accompanied by thermal shrinkage stress is applied to the corner of the semiconductor element. Figure 4 This is a cross-sectional view of a corner portion of a semiconductor element to be formed by dicing in the semiconductor wafer according to the third embodiment. Figure 5 This is a cross-sectional view of a corner portion of a semiconductor element to be formed by dicing in the semiconductor wafer according to the fourth embodiment. Figure 6 This is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the fifth embodiment is applied. Figure 7 This is a block diagram showing the configuration of a cooling system according to the sixth embodiment. DETAILED DESCRIPTION

[0011] <Implementation method 1> Embodiment 1 will be described below using the drawings. Figure 1It is a top view of the semiconductor wafer 1 according to the first embodiment. Figure 2 (a) is a plan view of a corner portion of a semiconductor element 3 to be formed by dicing in the semiconductor wafer according to the first embodiment. Figure 2 (b) is a cross-sectional view of a corner portion of the semiconductor element 3 to be formed by dicing in the semiconductor wafer 1 according to the first embodiment.

[0012] like Figure 1 As shown, the semiconductor wafer 1 is formed in a disk shape. In the area other than the peripheral portion of the semiconductor wafer 1, a plurality of semiconductor elements 3 cut into small pieces are formed. In addition, in the area other than the peripheral portion of the semiconductor wafer 1, a plurality of cutting lines 2 for dividing into a plurality of semiconductor elements 3 are formed in mutually intersecting directions. Each semiconductor element 3 obtained from the semiconductor wafer 1 is mounted on a semiconductor device (power module) after a known process.

[0013] like Figure 2 As shown in FIGS. 2( a ) and 2 ( b ), the semiconductor wafer 1 includes a semiconductor substrate 10 , an interlayer insulating film 9 , and a surface protection film 8 .

[0014] The semiconductor substrate 10 is formed in a disk shape. The base material of the semiconductor substrate 10 is SiC. Alternatively, the base material of the semiconductor substrate 10 may be Si or GaN. An interlayer insulating film 9 and a surface protection film 8 are stacked on the upper surface of the semiconductor substrate 10 .

[0015] The interlayer insulating film 9 is, for example, a TEOS film, and covers the upper surface of the semiconductor substrate 10. Specifically, the interlayer insulating film 9 is provided in the region other than the peripheral portion of the semiconductor element 3 to be formed by cutting, and the portions of the interlayer insulating film 9 corresponding to the four corners of the semiconductor element 3 are formed into a chamfered curved shape when viewed from above.

[0016] The surface protection film 8 is, for example, polyimide and is provided to cover the interlayer insulating film 9 from the upper side. The cutting line 2 is formed by the opening 2a that opens to the upper side. The end of the interlayer insulating film 9 is retreated from the end of the surface protection film 8 relative to the end of the semiconductor substrate 10 to be formed by cutting. That is, the surface protection film 8 covers the entire interlayer insulating film 9. In addition, Figure 2 The arrow in (b) is the direction of crack extension.

[0017] In embodiment 1, when external stress accompanied by thermal shrinkage stress is applied to the corner of the semiconductor element 3, in order to suppress the extension of cracks to the lower side of the interlayer insulating film 9, the shape of the end of the interlayer insulating film 9 is set in each semiconductor element 3 after cutting so that the distance Lx from the corner of the semiconductor substrate 10 to be formed by cutting to the end of the interlayer insulating film 9 and the thickness d of the semiconductor substrate 10 satisfy the relationship of mathematical formula 1.

[0018] [Mathematical formula 1] Lx>10×d-717μm

[0019] The following describes the reason why the shape of the end of the interlayer insulating film 9 is set to satisfy the relationship of Mathematical Formula 1, so that when external stress accompanied by thermal shrinkage stress acts on the corner of the semiconductor element 3, the extension of cracks to the lower side of the interlayer insulating film 9 can be suppressed. Figure 3 This is a graph showing the relationship between the length D of a crack starting from the corner of the semiconductor element 3 and the thickness d of the semiconductor element 3 when an external stress accompanied by thermal contraction stress is applied to the corner of the semiconductor element 3 .

[0020] When the thickness d of the semiconductor element 3 becomes thicker, the thermal shrinkage stress on the semiconductor element 3 becomes larger, and therefore, it becomes easier to apply external stress. The part with the highest external stress is the corner of the semiconductor element 3, and cracks are easily generated at this part. Therefore, the larger the thickness d (hereinafter also referred to as "thickness d") of the semiconductor substrate 10, the more countermeasures are needed to deal with the occurrence of cracks. Specifically, by lengthening the distance Lx (hereinafter also referred to as "distance Lx") from the corner of the semiconductor substrate 10 to the end of the interlayer insulating film 9, even if cracks occur, it is difficult to extend to the end of the interlayer insulating film 9. Therefore, when the thickness d becomes larger, the distance Lx needs to be increased. The inventors of the present application conducted experiments using semiconductor elements 3 with different thicknesses d, and found that the relationship between the distance Lx and the thickness d is expressed by the linear relationship of mathematical formula 1.

[0021] Figure 3 Using data for evaluating semiconductor elements 3 with different thicknesses d, the relationship between the length D of a crack starting from a corner of the semiconductor element 3 and the thickness d is shown. Figure 3 As shown, in the case of the semiconductor element 3 with d=100 μm and the semiconductor element 3 with d=300 μm, the length D of the crack is longer in the case of the semiconductor element 3 with d=300 μm, and the relationship is expressed by the linear relationship of Mathematical Formula 1. When the distance Lx is longer than the length D of the crack, the crack does not extend to the end of the interlayer insulating film 9, so the above-mentioned effect can be obtained by satisfying Mathematical Formula 1.

[0022] Here, thickness d is, for example, about 100 μm, and distance Lx is, for example, about 300 μm. Interlayer insulating film 9 is completely covered by surface protection film 8 to the end, and the width of interlayer insulating film 9 covered by surface protection film 8 is, for example, about 1 / 3 of distance Lx.

[0023] As described above, the semiconductor wafer 1 according to the first embodiment includes a semiconductor substrate 10 on which an interlayer insulating film 9 and a surface protection film 8 covering the interlayer insulating film 9 are stacked on the upper surface, and a plurality of semiconductor elements 3 are formed on the semiconductor substrate 10, and the plurality of semiconductor elements 3 are obtained by cutting into small pieces along the opening 2a formed in the surface protection film 8. With respect to the end of the semiconductor substrate 10 to be formed by cutting, the end of the interlayer insulating film 9 is retreated from the end of the surface protection film 8, and in each semiconductor element 3 after cutting, the shape of the end of the interlayer insulating film 9 is set so that the distance Lx from the corner of the semiconductor substrate 10 to be formed by cutting to the end of the interlayer insulating film 9 and the thickness d of the semiconductor substrate 10 satisfy the relationship of Mathematical Formula 1.

[0024] Therefore, since the distance Lx from the corner of the semiconductor substrate 10 to the end of the interlayer insulating film 9 is increased, when external stress accompanied by thermal shrinkage stress is applied to the corner of the semiconductor element 3, it is possible to suppress the extension of cracks to the lower side of the interlayer insulating film 9. As a result, the durability of the semiconductor device including the semiconductor element 3 obtained from the semiconductor wafer 1 is improved.

[0025] <Implementation method 2> Next, a semiconductor wafer 1 according to Embodiment 2 will be described. In Embodiment 2, the same components as those described in Embodiment 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0026] The distance Lx is affected by the finish of the cutting line 2, which refers to the cutting degree of the cutting line width W and the cut width C. Therefore, in order to set the shape of the end of the interlayer insulating film 9 with high accuracy, it is necessary to consider the finish of the cutting line 2. Therefore, in the second embodiment, in addition to the mathematical formula 1, in order to consider the finish of the cutting line 2, the shape of the end of the interlayer insulating film 9 is set to satisfy the relationship of the mathematical formula 2 shown below.

[0027] The shape of the end of the interlayer insulating film 9 is set so that the width removed by cutting in the cutting line 2, i.e., the cut width C, the width L from the end of the surface protection film 8 to the end of the interlayer insulating film 9 in each semiconductor element 3, the curvature R of the interlayer insulating film 9 in the corner of the semiconductor element 3, and the distance Lx satisfy the relationship of mathematical formula 2.

[0028] [Mathematical formula 2]

[0029] use Figure 2 The following explains how to derive Mathematical Formula 2. Figure 2As shown, in a square with a side length of R+L+(WC) / 2), the diagonal length is Lx+R. The diagonal length of the square is expressed by Lx+R=R+L+(WC) / 2)×√2. From this formula, we can get the mathematical formula 2

[0030] Here, the width W of the cutting line 2 is, for example, about 150 μm, and the cut width C is, for example, about 50 μm. In addition, in each semiconductor element 3, the width L from the end of the surface protection film 8 to the end of the interlayer insulating film 9 is, for example, about 80 μm, and the curvature R of the interlayer insulating film 9 is, for example, about 500 μm. As a result, the distance Lx is, for example, 391 μm. In addition, in addition to the relationship of mathematical formula 1, the point that the shape of the end of the interlayer insulating film 9 is set to satisfy the relationship of mathematical formula 2 can also be adopted in the following embodiments 3 and 4.

[0031] As described above, in the semiconductor wafer 1 according to the second embodiment, in addition to the relationship of the mathematical formula 1, the shape of the end of the interlayer insulating film 9 is set to satisfy the relationship of the mathematical formula 2. Therefore, by considering the completion of the dicing line 2, the shape of the end of the interlayer insulating film 9 can be set with high accuracy. As a result, when external stress accompanied by thermal shrinkage stress is applied to the corner of the semiconductor element 3, the effect of suppressing the extension of cracks to the lower side of the interlayer insulating film 9 can be further improved.

[0032] <Implementation method 3> Next, a semiconductor wafer 1A according to the third embodiment will be described. Figure 4 It is a cross-sectional view of a corner portion of a semiconductor element 3A to be formed by dicing in a semiconductor wafer 1A according to Embodiment 3. In Embodiment 3, the same components as those described in Embodiments 1 and 2 are denoted by the same reference numerals and their description is omitted.

[0033] like Figure 4 As shown, in the third embodiment, in each semiconductor element 3A, an AlSi film 14 is arranged on the outer peripheral surface of the end of the interlayer insulating film 9 to cover the end of the interlayer insulating film 9. The AlSi film 14 is arranged to cover the entire outer peripheral surface of the end of the interlayer insulating film 9, and acts as a buffer material for cracks extending from the corner of the semiconductor element 3A. In addition, the AlSi film 14 is not only arranged on the outer peripheral surface of the end of the interlayer insulating film 9, but also can rise from the end of the interlayer insulating film 9 to the upper surface of the interlayer insulating film 9.

[0034] As described above, in each semiconductor wafer 1A involved in the third embodiment, the AlSi film 14 is arranged on the outer peripheral surface of the end of the interlayer insulating film 9 so as to cover the end of the interlayer insulating film 9 in each semiconductor element 3A. Therefore, the AlSi film 14 acts as a buffer material for cracks extending from the corners of the semiconductor element 3A, and therefore, when external stress accompanied by thermal shrinkage stress is applied to the corners of the semiconductor element 3, the effect of suppressing the extension of cracks to the lower side of the interlayer insulating film 9 can be further improved.

[0035] <Implementation method 4> Next, a semiconductor wafer 1B according to the fourth embodiment will be described. Figure 5 It is a cross-sectional view of a corner portion of a semiconductor element 3B to be formed by dicing in a semiconductor wafer 1B according to Embodiment 4. In Embodiment 4, the same components as those described in Embodiments 1 to 3 are denoted by the same reference numerals and their description is omitted.

[0036] like Figure 5 As shown, in the fourth embodiment, the AlSi film 14 is formed thicker than the interlayer insulating film 9, and is arranged from the outer peripheral surface of the end of the interlayer insulating film 9 to the end of the semiconductor substrate 10 to be formed by cutting in each semiconductor element 3B. The AlSi film 14 is arranged to cover the entire outer peripheral surface of the end of the interlayer insulating film 9 and the upper surface portion of the periphery thereof, and acts as a buffer material for cracks extending from the corner of the semiconductor element 3A.

[0037] In the case where the AlSi film 14 is not arranged between the semiconductor substrate 10 and the surface protection film 8, external stress is applied to the contact point between the semiconductor substrate 10 and the surface protection film 8. In contrast, in the fourth embodiment, the AlSi film 14 is arranged from the end of the interlayer insulating film 9 to the end of the semiconductor substrate 10 to be formed by dicing in each semiconductor element 3B. That is, by arranging the AlSi film 14 from the end of the interlayer insulating film 9 to the end of the semiconductor element 3B, external stress is applied to the contact point between the end of the surface protection film 8 stacked in a manner covering the interlayer insulating film 9 and the AlSi film 14 arranged from the end of the interlayer insulating film 9 to the end of the semiconductor element 3A. The linear expansion coefficient of the AlSi film 14 is larger than that of the semiconductor substrate 10, so that the external stress applied to the contact point becomes easy to relax.

[0038] As described above, in the semiconductor wafer 1B involved in the fourth embodiment, when external stress accompanied by thermal shrinkage stress is applied to the corner of the semiconductor element 3, the effect of suppressing crack extension to the lower side of the interlayer insulating film 9 can be further improved compared with the case of the third embodiment.

[0039] <Implementation method 5> This embodiment is an embodiment in which the semiconductor device involved in the above-mentioned embodiments 1 to 4 is applied to a power conversion device. The application of the semiconductor device involved in the embodiments 1 to 4 is not limited to a specific power conversion device, but as an embodiment 5, the case where the semiconductor device involved in the embodiments 1 to 4 is applied to a three-phase inverter is described below.

[0040] Figure 6 This is a block diagram showing the configuration of a power conversion system to which the power conversion device 16 according to the fifth embodiment is applied.

[0041] Figure 6 The power conversion system shown is composed of a power supply 15, a power conversion device 16, and a load 18. The power supply 15 is a DC power supply and provides DC power to the power conversion device 16. The power supply 15 can be constructed in various forms, for example, it can be composed of a DC system, a solar cell, a storage battery, or it can be composed of a rectifier circuit or an AC / DC converter connected to an AC system. In addition, the power supply 15 can be composed of a DC / DC converter that converts the DC power output from the DC system into a specified power.

[0042] The power conversion device 16 is a three-phase inverter connected between the power source 15 and the load 18, converting the DC power provided by the power source 15 into AC power and providing the AC power to the load 18. Figure 6 As shown, the power conversion device 16 includes: a main conversion circuit 17, which converts DC power into AC power and outputs it; a drive circuit 19, which outputs a drive signal for driving each switching element of the main conversion circuit 17; and a control circuit 20, which outputs a control signal for controlling the drive circuit 19 to the drive circuit 19.

[0043] Load 18 is a three-phase motor driven by AC power supplied from power conversion device 16. Load 18 is not limited to a specific use, but is a motor installed in various electrical equipment, for example, a hybrid car, an electric car, a railway vehicle, an elevator, or a motor for air conditioning equipment.

[0044] The power conversion device 16 is described in detail below. The main conversion circuit 17 includes a switching element (not shown) and a return diode (not shown), and converts the DC power provided from the power supply 15 into AC power by switching the switching element, and provides the AC power to the load 18. Although the specific circuit structure of the main conversion circuit 17 is varied, the main conversion circuit 17 involved in this embodiment is a two-level three-phase full-bridge circuit, and can be composed of six switching elements and six return diodes connected in reverse parallel to each switching element. For at least any of the switching elements and return diodes of the main conversion circuit 17, the semiconductor device of any one of the above-mentioned embodiments 1 to 4 is applied. Every two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Moreover, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 17, are connected to the load 18.

[0045] The drive circuit 19 generates a drive signal for driving the switch element of the main conversion circuit 17, and supplies the drive signal to the control electrode of the switch element of the main conversion circuit 17. Specifically, a drive signal for turning on the switch element and a drive signal for turning off the switch element are output to the control electrode of each switch element according to a control signal from a control circuit 20 described later. When the switch element is kept in the on state, the drive signal is a voltage signal (on signal) above the threshold voltage of the switch element, and when the switch element is kept in the off state, the drive signal is a voltage signal (off signal) below the threshold voltage of the switch element.

[0046] The control circuit 20 controls the switching elements of the main conversion circuit 17 so as to provide the desired power to the load 18. Specifically, the time (on-time) that each switching element of the main conversion circuit 17 should be in the on state is calculated based on the power that should be provided to the load 18. For example, the main conversion circuit 17 can be controlled by PWM control that modulates the on-time of the switching element based on the voltage to be output. Then, the control instruction (control signal) is output to the drive circuit 19 so that the on signal is output to the switching element that should be in the on state at each moment, and the off signal is output to the switching element that should be in the off state. The drive circuit 19 outputs the on signal or the off signal as a drive signal to the control electrode of each switching element according to the control signal.

[0047] In the power conversion device according to the present embodiment, since the semiconductor devices according to the first to fourth embodiments are applied as switching elements of the main conversion circuit 17 , it is possible to improve durability.

[0048] In this embodiment, an example of applying the semiconductor device involved in embodiments 1 to 4 to a two-level three-phase inverter is described, but the application of the semiconductor device involved in embodiments 1 to 4 is not limited to this, and can be applied to various power conversion devices. In this embodiment, although a two-level power conversion device is used, it can also be a three-level or multi-level power conversion device. When power is supplied to a single-phase load, the semiconductor device involved in embodiments 1 to 4 can be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the semiconductor device involved in embodiments 1 to 4 can be applied to a DC / DC converter or an AC / DC converter.

[0049] In addition, the power conversion device using the semiconductor device involved in embodiments 1 to 4 is not limited to the case where the above-mentioned load is a motor. For example, it can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0050] <Implementation method 6> Next, the cooling system 26 according to the sixth embodiment will be described. Figure 7 This is a block diagram showing the configuration of a cooling system 26 according to the sixth embodiment.

[0051] For example, power modules (semiconductor devices) of power conversion devices mounted on vehicles are used in a harsh thermal cycle environment with a wider operating temperature range (eg, a range of -40°C to 150°C) than power modules used indoors.

[0052] In addition, in a low temperature environment, torque is applied to the motor at startup, so the temperature of the entire drive device rises sharply. For example, in the case of snow accumulation in winter, high torque is required, so the drive device is subjected to a high load. Therefore, there is a problem that the sealing resin in the power module and the semiconductor element are peeled off, causing the insulation of the semiconductor element to be broken. In embodiment 6, it is completed to solve such a problem, and the following is a detailed description.

[0053] like Figure 7 As shown, the cooling system 26 includes a radiator 21 , a pump 22 , a battery cooling device 23 , a flow regulating device 24 , a refrigerant flow path 25 , and a PCU cooling device 27 .

[0054] In the cooling system 26, the devices for cooling the PCU (not shown) and the battery (not shown) in the radiator (heat converter) 21 are connected in parallel via the refrigerant flow path 25. The refrigerant flowing through the refrigerant flow path 25 flows in the direction of F shown in the figure by the operation of the pump 22. The refrigerant passing through the radiator 21 may also have a flow regulating device 24 at the branching point where it branches into the battery cooling device 23 and the PCU. In addition, the battery cooling device 23 and the PCU cooling device 27 may also be connected in series with the radiator 21.

[0055] This can prevent the sealing resin (not shown) and the semiconductor element 3 (see Figure 1 ) cracks, so the cooling load of the PCU cooling device 27 is reduced compared to the past, and the cooling capacity can be distributed to the battery. By improving the cooling performance of the battery, the cruising range of the vehicle can be further extended than before. Furthermore, the size of the PCU cooling device 27 for cooling the PCU equipped with a semiconductor device can be miniaturized. Therefore, the space in the vehicle can be effectively used.

[0056] The present disclosure has been described in detail, but the above description is in all aspects illustrative and not restrictive, and it is understood that numerous modifications not shown are conceivable.

[0057] The embodiments can be freely combined, or can be appropriately modified or omitted. Description of symbols

[0058] 1Semiconductor wafer 2a Opening 3. 3A, 3B semiconductor components 8 Surface protection film 9 Interlayer insulation film 10 Semiconductor substrate 14 AlSi film 16 Power conversion device 17 Main conversion circuit 19. Driving Circuit 20 Control Circuit 21 Radiator 23 Battery Cooling Device 25 Refrigerant flow path 26 Cooling System 27 PCU cooling unit.

Claims

1. A semiconductor wafer, The semiconductor wafer includes a semiconductor substrate having an interlayer insulating film and a surface protective film covering the interlayer insulating film stacked on the upper surface, and a plurality of semiconductor elements cut into small pieces along openings formed on the surface protective film are formed on the semiconductor substrate. The semiconductor wafer is characterized in that: With respect to an end portion of the semiconductor substrate to be formed by dicing, an end portion of the interlayer insulating film is retreated from an end portion of the surface protection film, The shape of the end of the interlayer insulating film is set so that in each of the semiconductor elements after cutting, the distance Lx from the corner of the semiconductor substrate to be formed by cutting to the end of the interlayer insulating film and the thickness d of the semiconductor substrate satisfy the following relationship: [Mathematical formula 1] Lx>10×d-717μm.

2. The semiconductor wafer according to claim 1, wherein At corners of each of the semiconductor elements, the interlayer insulating film is formed in a curved shape when viewed from above. The shape of the end of the interlayer insulating film is set so that the width W of the cutting line, the width of the cutting line removed by the cutting, that is, the cut width C, the width L from the end of the surface protection film to the end of the interlayer insulating film in each of the semiconductor elements, the curvature R of the interlayer insulating film in the corner of the semiconductor element, and the distance Lx satisfy the following relationship: [Mathematical formula 2] 3. The semiconductor wafer according to claim 1 or 2, wherein: In each of the semiconductor elements, an AlSi film is disposed on an outer peripheral surface of an end portion of the interlayer insulating film so as to cover the end portion of the interlayer insulating film.

4. The semiconductor wafer according to claim 3, wherein: The AlSi film is formed thicker than the interlayer insulating film, and is arranged from the outer peripheral surface of the end of the interlayer insulating film to the end of the semiconductor substrate to be formed by dicing in each of the semiconductor elements.

5. A semiconductor device, characterized in that: The semiconductor element is obtained from the semiconductor wafer according to any one of claims 1 to 4.

6. A semiconductor device, characterized in that: A semiconductor element is provided, the semiconductor element comprising a semiconductor substrate having an interlayer insulating film and a surface protection film covering the interlayer insulating film stacked on an upper surface, With respect to an end of the semiconductor substrate serving as an end of the semiconductor element, an end of the interlayer insulating film is retreated from an end of the surface protection film. The shape of the end of the interlayer insulating film is set so that in the semiconductor element, the distance Lx from the corner of the semiconductor substrate to the end of the interlayer insulating film and the thickness d of the semiconductor substrate satisfy the following relationship: [Mathematical formula 3] Lx>10×d-717μm.

7. The semiconductor device according to claim 6, wherein: In the semiconductor element, an AlSi film is disposed on an outer peripheral surface of an end portion of the interlayer insulating film so as to cover the end portion of the interlayer insulating film.

8. The semiconductor device according to claim 7, wherein: The AlSi film is formed thicker than the interlayer insulating film, and is arranged in the semiconductor element from the outer peripheral surface of the end of the interlayer insulating film to the end of the semiconductor substrate.

9. A power conversion device, characterized in that: include: A main conversion circuit, the main conversion circuit having the semiconductor device according to claim 5, converting input power and outputting the power; a driving circuit that outputs a driving signal for driving the semiconductor device to the semiconductor device; as well as A control circuit outputs a control signal for controlling the drive circuit to the drive circuit.

10. A cooling system, characterized in that: include: A PCU comprising the semiconductor device according to claim 5; a radiator, which cools the refrigerant; a battery, the battery supplying power to the PCU; a battery cooling device, the battery cooling device cooling the battery by means of the refrigerant; A PCU cooling device that cools the PCU using the refrigerant; and A refrigerant flow path through which the refrigerant flows.

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