Ru liner over barrier layer

Abstract

A method of producing a multi-layer substrate includes the steps of: depositing a diffusion barrier layer on a substrate; depositing an underlayer comprising a Group 6 metal on the barrier layer; and depositing a ruthenium layer on the underlying layer to produce a multi-layer substrate. A multilayer substrate is also disclosed.

Description

Technical Field

[0001] Embodiments of the present invention relate generally to the field of semiconductor manufacturing processes, and more particularly to processes for producing layered semiconductor substrates. Background Art

[0002] Portions of the substrate are covered by a conductive diffusion barrier layer, which in turn is covered by another conductive material. Suitable barrier layers may include titanium (Ti) / titanium nitride (TiN) barriers. However, the inventors have observed that typical nitride barriers can be problematic when the conductive layer has a roughness that can have a potentially negative impact on the final product. Therefore, the inventors have provided improved methods for producing multilayer substrates that address these and other issues. Summary of the invention

[0003] Methods of producing a multilayer substrate are provided herein. In an embodiment, a multilayer substrate is provided. In some embodiments, a method of producing a multilayer substrate comprises the following steps: depositing a diffusion barrier layer on a substrate; depositing an underlayer comprising a Group 6 metal on the barrier layer; and depositing a ruthenium layer on the underlayer to produce a multilayer substrate.

[0004] In other embodiments, a multilayer substrate includes a diffusion barrier layer, an underlayer including a Group 6 metal disposed on the diffusion barrier layer, and a ruthenium layer disposed on the underlayer, the multilayer substrate having an average roughness Ra and a root mean square roughness Rq less than or equal to about 2 nm.

[0005] Other and further embodiments of the present invention are described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments of the invention briefly summarized above and discussed in more detail below may be understood by reference to the exemplary embodiments shown in the accompanying drawings. However, the accompanying drawings illustrate only typical embodiments of the invention and are therefore not to be considered limiting of its scope, as the invention may admit to other equally effective embodiments.

[0007] Figure 1 A flow chart showing a method for producing a multi-layer substrate for a semiconductor device according to an embodiment of the present invention.

[0008] FIG. 2 a illustrates a block diagram of a partially completed multi-layer substrate according to embodiments disclosed herein.

[0009] FIG. 2 b illustrates a block diagram of a partially completed multi-layer substrate according to embodiments disclosed herein.

[0010] FIG. 2 c shows a block diagram of a multi-layer substrate according to embodiments disclosed herein.

[0011] FIG. 2 d illustrates a block diagram of another embodiment of a multi-layer substrate according to embodiments disclosed herein.

[0012] Figure 3 A cluster tool suitable for performing this method to produce a multi-layer substrate according to embodiments disclosed herein is shown.

[0013] For ease of understanding, the same component numbers have been used as much as possible to refer to the same components common to the various figures. The figures are not drawn to scale and may be simplified for clarity. The components and features of one embodiment may be advantageously incorporated into other embodiments without further elaboration. DETAILED DESCRIPTION

[0014] For purposes of this specification and the claims relating to the specification, the coding scheme for periodic table groups is based on the new notation of the IUPAC periodic table.

[0015] In an embodiment, a method of producing a multi-layer substrate comprises the following steps: depositing a diffusion barrier layer on a substrate; depositing an underlayer comprising a Group 6 metal on the diffusion barrier layer; and depositing a ruthenium layer on the underlayer to produce the multi-layer substrate. In an embodiment, the diffusion barrier layer comprises titanium nitride Ti a N x , Tantalum Nitride Ta a N x 、Zirconium nitride Zr a N x , wherein each a is independently 1 to 3 and x is 1 to 5 to form a neutral compound; titanium zirconium nitride TicZrdN, wherein c+d is equal to an integer from 1 to 3 and x is 1 to 5 to form a neutral compound; or a combination of the foregoing. In some embodiments, the diffusion barrier layer further comprises less than or equal to about 1 weight percent of the Group 6 metal present in the lower layer.

[0016] In an embodiment, the lower layer comprises molybdenum. In other embodiments, the lower layer consists essentially of molybdenum. In some embodiments, the ruthenium layer consists essentially of ruthenium. In an embodiment, the lower layer has a thickness less than the thickness of the ruthenium layer. In some embodiments, the lower layer has a thickness greater than or equal to about 0.5 nm, and less than or equal to about 2 nm. In an embodiment, the ruthenium layer has a thickness greater than or equal to about 5 nm, and less than or equal to about 1000 nm.

[0017] In some embodiments, the method further comprises the step of annealing the multilayer substrate by heating the multilayer substrate at a temperature greater than or equal to about 800° C. in an oxygen-free environment for a period of time greater than or equal to about 5 seconds and less than or equal to about 500 seconds. In some embodiments, the oxygen-free environment comprises nitrogen, argon, neon, krypton, or a combination of the foregoing.

[0018] In an embodiment, the upper surface of the annealed multilayer substrate has an average roughness Ra of less than or equal to about 2 nm. In an embodiment, the upper surface of the annealed multilayer substrate has a root mean square roughness Rq of less than or equal to about 2 nm. In an embodiment, the conductive layer has a center point resistivity of less than or equal to about 10 ohm-cm.

[0019] In one embodiment, the lower layer and the ruthenium layer are separately deposited by physical vapor deposition.

[0020] In some embodiments, the method further comprises the following steps: depositing a nitride capping layer 208 (also referred to in the art as a furnace cap) on the multi-layer substrate to produce a capped multi-layer substrate (see FIG. 2d ). In an embodiment, the nitride capping layer comprises silicon nitride. In an embodiment, the method further comprises depositing a nitride capping layer on the upper surface of the annealed multi-layer substrate.

[0021] In an embodiment, a multilayer substrate comprises a diffusion barrier layer, an underlayer comprising a Group 6 metal disposed on the barrier layer, and a ruthenium layer disposed on the underlayer, the multilayer substrate having an average roughness Ra and a root mean square roughness Rq of less than or equal to about 2 nm. In an embodiment, the multilayer substrate is produced according to any one or combination of the methods disclosed herein. In an embodiment of the multilayer substrate, the underlayer consists essentially of molybdenum, the ruthenium layer consists essentially of ruthenium, or both.

[0022] Figure 1 2a to 2d, and may be performed, for example, in a suitable cluster tool and processing chamber, as described below with respect to Figure 3 Exemplary processing systems that may be used to perform the methods disclosed herein may include, but are not limited to, any commercially available from Applied Materials, Inc. of Santa Clara, California. Other processing chambers, including from other manufacturers, may also be used in conjunction with the teachings provided herein.

[0023] The method 100 is generally performed on a substrate 200 provided to a processing volume of a processing chamber (see FIGS. 2a-2d), such as subsequently Figure 3 The illustrated substrate processing chamber 314 and substrate processing chamber 338. For simplicity, the substrate 200 is shown in Figures 2a-2d as a flat surface. However, the substrate may include various features, such as through holes, trenches, or the like.

[0024] The substrate 200 may be any suitable substrate for use in semiconductor articles and may include one or more of silicon (Si), silicon oxide (SiO2), or the like. In an embodiment, the substrate 200 may include multiple layers, or may consist essentially of a dielectric layer. For example, a low-k material (e.g., a material having a dielectric constant less than that of silicon oxide, or less than about 3.9), or the like. In some embodiments, the dielectric layer may be disposed atop one or more additional dielectric layers (not shown), such as silicon oxide, silicon nitride, silicon carbide, or the like.

[0025] Additionally, the substrate 200 may include additional layers of material or may have one or more completed or partially completed structures or devices formed in or on the substrate 200. In some embodiments, a layer such as a logic device or the like, or a portion of a device requiring electrical connection, such as a gate, a contact pad, a conductive line or a via, or the like, may be disposed in the substrate 200 and aligned with one or more features. As used herein, a "layer" is not necessarily a continuous structure extending across the entire surface of a substrate.

[0026] In an embodiment, the substrate 200 may be, for example, a doped or undoped silicon substrate, a III-V compound substrate, a silicon germanium (SiGe) substrate, an epitaxial substrate, a silicon on insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electroluminescent (EL) lamp display, a light emitting diode (LED) substrate, a solar cell array, a solar panel, or the like. In some embodiments, the substrate 200 may be a semiconductor wafer.

[0027] The substrate 200 is not limited to any particular size or shape. The substrate may be a circular wafer having a 200 mm diameter, a 300 mm diameter, or other diameters, such as 450 mm, etc. The substrate may also be any polygonal, square, rectangular, curved, or non-circular workpiece, such as a polygonal glass substrate used in the manufacture of flat panel displays.

[0028] Reference Figure 1 2a-2d, in an embodiment, a method (generally referred to as 100) of producing a multilayer substrate (e.g., 200, see FIG. 2) includes block 102, depositing a diffusion barrier layer (202, see FIG. 2a) on top of the substrate. As shown in FIG. 2a, the diffusion barrier layer 202 is deposited on the upper surface of the substrate 200. The diffusion barrier layer 202 can be deposited on the substrate 200 in a processing chamber configured to deposit layers (e.g., substrate processing chambers 312, 314 discussed later). In an embodiment, the diffusion barrier layer 202 is deposited by physical vapor deposition, however any deposition method known in the art can be used. The diffusion barrier layer 202 can further enhance the adhesion of a metal layer disposed on the diffusion barrier layer 202.

[0029] In an embodiment, the diffusion barrier layer 202 includes a nitride, which in an embodiment may include titanium nitride Ti a N x , Tantalum Nitride Ta a N x 、Zirconium nitride Zr a N x , wherein each a is independently 1 to 3 and x is 1 to 5 to form a neutral compound; titanium zirconium nitride Ti c Zr d N x , wherein c+d is equal to an integer from 1 to 3 and x is from 1 to 5 to result in a neutral compound; or a combination of the foregoing.

[0030] In an embodiment, the nitride layer is deposited using reactive physical vapor deposition, for example, by sputtering a titanium or tantalum target in a nitrogen / argon plasma. The diffusion barrier layer is configured to limit the diffusion of the underlying layer and / or the ruthenium layer into the semiconductor substrate and dielectric layer, thereby significantly increasing the reliability of the connection. In an embodiment, the diffusion barrier layer has a thickness greater than or equal to about or greater than or equal to approximately or greater than or equal to approximately or greater than or equal to approximately and less than or equal to approximately or less than or equal to approximately or less than or equal to approximately

[0031] In some embodiments, the diffusion barrier layer further comprises an amount of the underlayer, for example, a material used in the underlayer that is doped in an amount effective to increase or promote adhesion between the diffusion barrier layer and the underlayer. In some embodiments, the diffusion barrier layer further comprises less than or equal to about 1 weight percent of a Group 6 metal present in the underlayer, or less than or equal to about 0.1 weight percent of a Group 6 metal present in the underlayer, or less than or equal to about 0.01 weight percent of a Group 6 metal present in the underlayer, based on the total amount of the diffusion barrier layer present.

[0032] Next, the method 100 includes a block 104 of depositing a lower layer (204) comprising a Group 6 metal on the barrier layer in the processing chamber (see FIG. 2 b). In an embodiment, the lower layer 204 has a thickness less than the thickness of a ruthenium layer 206 discussed later. In an embodiment, the lower layer has a thickness greater than or equal to about 0.1 nm, or less than or equal to about 2 nm. In an embodiment, the lower layer is deposited by physical vapor deposition.

[0033] In an embodiment, the lower layer 204 may include or consist of a Group 6 metal, i.e., chromium, molybdenum, or tungsten. In an embodiment, the lower layer consists essentially of pure molybdenum, which is defined herein as including no more than 5 wt% impurities. In other embodiments, the lower layer 204 includes or consists essentially of a molybdenum alloy. For example, useful molybdenum alloys include molybdenum-tungsten alloys, molybdenum-chromium alloys, and / or alloys including one or more metals selected from Groups 3 to 14 of the periodic table.

[0034] Next, the method 100 includes block 106, depositing a ruthenium layer 206 on the lower layer 204 in the processing chamber, followed by block 108 to produce a multilayer substrate 200, which is shown in FIG2c. In an embodiment, the ruthenium layer 206 has a thickness greater than or equal to about 5 nm, or less than or equal to about 500 nm. In an embodiment, the lower layer 204 is deposited by physical vapor deposition.

[0035] In an embodiment, the ruthenium layer 206 may include or consist of ruthenium metal. In an embodiment, the ruthenium layer consists of pure ruthenium, which is defined herein as including no more than 5 wt% impurities. In other embodiments, the ruthenium layer 206 includes or consists of a ruthenium alloy. Useful ruthenium alloys include alloys comprising ruthenium and one or more metals selected from Groups 3 to 14 of the periodic table.

[0036] In some embodiments, the method 100 further includes block 110, block 112 of annealing the multilayer substrate 200 to produce an annealed multilayer substrate block 114 by heating the multilayer substrate 200 at a temperature greater than or equal to about 800°C for a period of time sufficient to remove internal stresses and irregularities present in the deposited ruthenium layer. In some embodiments, the annealing of the substrate comprises or consists of a rapid thermal process. In some embodiments, the multilayer substrate 200 is heated at a temperature greater than or equal to about 800°C for a period greater than or equal to about 5 seconds in an oxygen-free environment, a so-called soak anneal. In some embodiments, the thermal process may be a rapid heating of the substrate to a temperature equal to or greater than 1000°C followed by rapid cooling, a so-called spike anneal. In some embodiments, the oxygen-free environment comprises nitrogen, argon, neon, krypton, hydrogen, or a combination of the foregoing.

[0037] In an embodiment, the upper surface of the ruthenium layer after the annealing step has an average roughness Ra of less than or equal to about 2 nm, or less than or equal to about 1.8 nm, or less than or equal to about 1.5 nm, or less than or equal to about 1 nm. In an embodiment, the upper surface of the ruthenium layer after the annealing step has a root mean square roughness Rq of less than or equal to about 2 nm, or less than or equal to about 1.8 nm, or less than or equal to about 1.5 nm, or less than or equal to about 1 nm. In some embodiments, the ruthenium layer has a center point resistivity of less than or equal to about 10 ohm-cm, or less than or equal to about 8 ohm-cm, or less than or equal to about 7 ohm-cm.

[0038] In an embodiment, processing may be performed in substrate processing chamber 338 (see Figure 3 ), which can be any PVD chamber configured to deposit the diffusion barrier layer, and / or the underlying layer and / or the ruthenium layer in the manner disclosed herein. An exemplary PVD processing system suitable for modification and use in accordance with the teachings herein to perform the above-described processes is a PVD system commercially available from Applied Materials, Inc. in Santa Clara, California. In embodiments, suitable PVD chambers include those described in U.S. Patent No. 8,795,487 issued on August 5, 2014 to Ritchie et al. and U.S. Patent Publication No. 2002 / 0144889 published on October 10, 2002 to Rong Tao et al.

[0039] To perform the deposition process, RF and DC power are provided to a target containing the desired material disposed in a PVD processing chamber. In addition, the PVD processing chamber is maintained at a pressure of about 4 mTorr to about 150 mTorr, or about 10 mTorr to about 150 mTorr. In an embodiment, RF bias power may be provided to a substrate support.

[0040] The PVD process includes a suitable gas to facilitate the process. The gas source may provide a suitable gas species lacking oxygen, such as an inert gas, such as argon, krypton, neon, or the like. The process chamber may include a high temperature heater suitable for heating the substrate to a suitable annealing temperature.

[0041] In some embodiments, target atoms impact the substrate. A deposition rate in the range of 0.1-10 angstroms / second is suitable for use in accordance with the present invention. Thus, the physical vapor deposition chamber may be configured to apply a deposition rate in the range of 0.1-10 angstroms / second.

[0042] The methods described herein may be performed in individual processing chambers, which may be provided in a standalone configuration or as part of one or more cluster tools, e.g., Figure 3The integrated tool 300 (i.e., cluster tool) is described. In some embodiments, the method 100 for producing a multilayer substrate described above may be performed in individual processing chambers provided as separate chambers or as part of a cluster tool. In an embodiment, a cluster tool is configured to perform a method for processing a substrate as described herein, comprising: depositing a diffusion barrier layer by a physical vapor deposition process, followed by depositing an underlying layer, and then subsequently depositing a ruthenium layer.

[0043] Examples of integrated tool 300 include the integrated tools commercially available from Applied Materials, Inc. of Santa Clara, California. However, the methods described herein may be practiced using other cluster tools having suitable processing chambers coupled thereto, or in other suitable processing chambers. For example, in some embodiments, the methods of the present invention described above may be advantageously performed in an integrated tool such that there is limited or no vacuum break during processing.

[0044] The integrated tool 300 may include two load lock chambers 306A, 306B for transferring substrates into and out of the integrated tool 300. Typically, since the integrated tool 300 is under vacuum, the load lock chamber 306 may "pump down" the substrates introduced into the integrated tool 300. The first robot 310 may transfer substrates between the load lock chambers 306A, 306B and a first set of one or more substrate processing chambers 312, 314, 316, 318 (four are shown) coupled to the first central transfer chamber 350. Each substrate processing chamber 312, 314, 316, 318 may be equipped to perform a number of substrate processing operations. In some embodiments, the first set of one or more substrate processing chambers 312, 314, 316, 318 may include any combination of PVD, ALD, CVD, etching, or degas chambers. For example, in some embodiments, substrate processing chambers 312 and 314 include CVD and / or ALD processing chambers configured to deposit one or more of the diffusion barrier layer, the underlying layer, the ruthenium layer, and / or the nitride capping layer 208 .

[0045] The first robot 310 may also transfer substrates to / from the two intermediate transfer chambers 322, 324. The intermediate transfer chambers 322, 324 may be used to maintain an extremely high vacuum state while allowing substrates to be transferred within the integrated tool 300. The second robot 330 may transfer substrates between the intermediate transfer chambers 322, 324 and a second set of one or more substrate processing chambers 332, 334, 336, 338 coupled to the second central transfer chamber 355. The substrate processing chambers 332, 334, 336, 338 may be configured to perform a variety of substrate processing operations, including the method 100 described above, in addition to physical vapor deposition processing (PVD), chemical vapor deposition (CVD), etching, orientation, and other substrate processing. In some embodiments, the second set of one or more substrate processing chambers 332, 334, 336, 338 may include any combination of PVD, ALD, CVD, etching, or degas chambers. Any substrate processing chamber may be removed from the integrated tool 300 if not necessary for the particular process to be performed by the integrated tool 300 .

[0046] Embodiments of the present invention further include a multilayer substrate produced according to one or more embodiments disclosed herein, comprising a diffusion barrier layer, a lower layer comprising a Group 6 metal disposed on the barrier, and a ruthenium layer disposed on the lower layer, the multilayer substrate having an average roughness Ra and a root mean square roughness Rq less than or equal to approximately 2 nm.

[0047] In some of these embodiments, the lower layer consists essentially of molybdenum, the ruthenium layer consists essentially of ruthenium, or both.

[0048] Example

[0049] According to embodiments of the present invention, at least the following embodiments are contemplated.

[0050] E1. A method for producing a multilayer substrate, comprising:

[0051] depositing a diffusion barrier layer on the substrate;

[0052] depositing an underlayer comprising a Group 6 metal on the barrier layer; and

[0053] A ruthenium layer is deposited over the underlying layer to produce a multi-layer substrate.

[0054] E2. The method according to embodiment E1, wherein the diffusion barrier layer comprises TiN x 、TaN x 、Zr 3 N 4 、TiZr y N x , or a combination of the foregoing.

[0055] E3. The method of embodiment E1 or E2, wherein the diffusion barrier layer further comprises less than or equal to about 1 weight percent of the Group 6 metal present in the underlying layer.

[0056] E4. The method of any one of embodiments E1 to E3, wherein the underlying layer has a thickness less than a thickness of the ruthenium layer.

[0057] E5. The method of any one of embodiments E1 to E4, wherein the lower layer has a thickness greater than or equal to about 0.5 nm and less than or equal to about 10 nm.

[0058] E6. The method of any one of embodiments E1 to E5, wherein the lower layer comprises molybdenum, or wherein the lower layer consists essentially of molybdenum.

[0059] E7. The method of any one of embodiments E1 to E6, wherein the ruthenium layer consists essentially of ruthenium.

[0060] E8. The method of any one of embodiments E1 to E7, wherein the ruthenium layer has a thickness greater than or equal to about 5 nm and less than or equal to about 1000 nm.

[0061] E9. The method of any one of embodiments E1 to E8, further comprising annealing the multilayer substrate by heating the multilayer substrate at a temperature greater than or equal to about 800° C. in an oxygen-free environment for a period greater than or equal to about 5 seconds and less than or equal to about 500 seconds.

[0062] E10. The method according to embodiment E9, wherein the oxygen-free environment comprises nitrogen, argon, neon, krypton, hydrogen, or a combination of the foregoing.

[0063] E11. The method of embodiment E9 or E10, wherein the upper surface of the annealed multilayer substrate has an average roughness Ra of less than or equal to about 10 nm.

[0064] E12. The method of any one of embodiments E9 to E11, wherein the upper surface of the annealed multilayer substrate has a root mean square roughness Rq of less than or equal to about 10 nm.

[0065] E13. The method of any one of embodiments E9 to E12, wherein the ruthenium layer has a center-point resistivity of less than or equal to about 10 ohm-cm.

[0066] E14. The method according to any one of embodiments E1 to E13, wherein the lower layer and the ruthenium layer are deposited separately by physical vapor deposition.

[0067] E15. The method according to any one of embodiments E9 to E14, further comprising depositing a nitride capping layer on the upper surface of the annealed multilayer substrate.

[0068] E16. The method of embodiment E15, wherein the nitride capping layer comprises silicon nitride.

[0069] E17. A multi-layer substrate comprising a diffusion barrier layer, an underlayer comprising a Group 6 metal disposed on the barrier layer, and a ruthenium layer comprising ruthenium disposed on the underlayer, the multi-layer substrate being produced according to the method of any one of embodiments E1 to E16.

[0070] E18. A multilayer substrate comprising a diffusion barrier layer, a lower layer comprising a Group 6 metal disposed on the barrier layer, and a ruthenium layer comprising ruthenium disposed on the lower layer, the multilayer substrate having an average roughness Ra and a root mean square roughness Rq of less than or equal to about 2 nm.

[0071] E19. The multilayer substrate according to embodiment E17 or E18, wherein at least one of the following: the lower layer consists essentially of molybdenum, or the ruthenium layer consists essentially of ruthenium.

[0072] Examples

[0073] Although the present invention has been described in conjunction with its specific embodiments, the above description is intended to illustrate and not limit the scope of the present invention. For those skilled in the art, other aspects, advantages and modifications of the present invention will be apparent.

[0074] Therefore, the following examples are presented in order to provide complete disclosure and description to those skilled in the art and are not intended to limit the scope of the present invention.

[0075] The inventors have discovered that a relatively thin substrate of molybdenum affects the ruthenium layer during the annealing process. For example, the inventors have observed that annealing as described above causes the grain structure (i.e., crystal growth) of the ruthenium layer to be oriented along an XY plane parallel to the molybdenum underlying layer, with only limited (if any) crystal growth in a direction perpendicular to the molybdenum underlying layer and thus limiting or eliminating expansion of the ruthenium layer in a direction perpendicular to the molybdenum underlying layer. Transmission electron micrographs of comparative examples at different magnifications, with ruthenium deposited directly on a silicon support by physical vapor deposition The TiN layer on The ruthenium layer, when annealed by rapid thermal processing (RTP) in a nitrogen atmosphere at 950°C for 30 seconds, results in a range of to about The thickness of the ruthenium surface.

[0076] Transmission electron micrograph of the inventive example at the same magnification as the comparative example, with the deposited directly on the The molybdenum lower layer The ruthenium layer and the molybdenum underlayer are deposited on the same silicon support as used in the comparative example. After annealing by the same rapid thermal treatment as in the comparative example at 950° C. for 30 seconds in a nitrogen atmosphere, a TiN layer having a range of about to about The thickness of the ruthenium surface.

[0077] A ruthenium layer for a comparative example, wherein The ruthenium layer is deposited directly on the silicon support by physical vapor deposition. The TiN layer resulted in a center point sheet resistance of about 6.2 as deposited, about 4.7 after RTP at 950° C. for 30 seconds in nitrogen, and about 4.8 after RTP at 950° C. for 30 seconds in argon.

[0078] In another comparative example, The molybdenum layer is deposited directly on the silicon support by physical vapor deposition. The TiN layer on The ruthenium layer was deposited over the ruthenium layer, resulting in a center point resistivity of about 6.1 as deposited, about 5.9 after RTP at 950°C for 30 seconds in nitrogen, and about 6.0 after RTP at 950°C for 30 seconds in argon.

[0079] According to the embodiments disclosed herein, a deposition method is used to deposit The ruthenium layer is deposited directly on The molybdenum layer is deposited on The ruthenium layer and the molybdenum layer are deposited directly on the silicon support. The TiN layer was annealed over the as-deposited center point sheet resistance of about 8.0, about 4.1 after RTP in nitrogen at 950°C for 30 seconds, and about 4.2 after RTP in argon at 950°C for 30 seconds. These data show that the center point resistivity of the top layer is greatly reduced compared to both the as-deposited layer (no annealing) and the comparative example. These data further show that annealing in nitrogen is essentially equivalent to annealing in argon.

[0080] Table 1 below discloses the average roughness data and RMS roughness for the three examples utilized in FIGS. 5a-5c.

[0081] Table 1

[0082]

[0083]

[0084] These data show that there is a substantial reduction in the roughness of the Ruthenium layer deposited over the Mo underlying layer in accordance with embodiments of the present invention.

[0085] Other semiconductor substrate processing systems may be used to implement the present invention, wherein processing parameters may be adjusted to achieve characteristics acceptable to those of ordinary skill in the art by utilizing the teachings disclosed herein without departing from the spirit of the present invention. Although the foregoing is with respect to embodiments of the present invention, other and further embodiments of the present invention may be conceived without departing from the basic scope of the present invention.

Claims

1. A method for producing a multilayer substrate, comprising the following steps: depositing a diffusion barrier layer on the substrate; depositing an underlayer on the diffusion barrier layer, the underlayer comprising a Group 6 metal; and A ruthenium layer is deposited on the underlying layer to produce the multi-layer substrate.

2. The method according to claim 1, wherein the diffusion barrier layer comprises: Titanium Nitride Ti a N x , Tantalum Nitride Ta a N x , or zirconium nitride Zr a N x , wherein each a is independently 1 to 3 and x is 1 to 5 to produce a neutral compound; Titanium Zirconium Nitride Ti c Zr d N x , wherein c+d is equal to an integer from 1 to 3 and x is from 1 to 5 to result in a neutral compound; or A combination of the foregoing.

3. The method of claim 1 wherein the diffusion barrier layer further comprises less than or equal to about 1 weight percent of the Group 6 metal present in the underlying layer. The method of claim 1 , wherein the lower layer has a thickness that is less than a thickness of the ruthenium layer. 5 . The method of claim 1 , wherein the lower layer has a thickness greater than or equal to about 0.5 nm and less than or equal to about 10 nm. The method of claim 1 , wherein the lower layer comprises molybdenum.

7. The method of claim 1, wherein the lower layer consists essentially of molybdenum.

8. The method of claim 1, wherein the ruthenium layer consists essentially of ruthenium.

9. The method of claim 1, wherein the ruthenium layer has a thickness greater than or equal to about 5 nm and less than or equal to about 1000 nm.

10. The method of claim 1, wherein the lower layer and the ruthenium layer are individually deposited by physical vapor deposition.

11. The method of any one of claims 1 to 10, further comprising the step of annealing the multilayer substrate by heating the multilayer substrate at a temperature greater than or equal to about 800°C in an oxygen-free environment for a period greater than or equal to about 5 seconds and less than or equal to about 500 seconds.

12. The method of claim 11, wherein the oxygen-free environment comprises nitrogen, argon, neon, krypton, hydrogen, or a combination of the foregoing.

13. The method of claim 11, wherein the upper surface of the annealed multi-layer substrate has an average roughness Ra of less than or equal to about 10 nm.

14. The method of claim 11, wherein the upper surface of the annealed multi-layer substrate has a root mean square roughness Rq of less than or equal to about 10 nm.

15. The method of claim 11, wherein the ruthenium layer has a center-point resistivity of less than or equal to about 10 ohm-cm.

16. The method of claim 11, further comprising the step of depositing a nitride capping layer on the upper surface of the annealed multi-layer substrate. The method of claim 16 , wherein the nitride capping layer comprises silicon nitride.

18. A multilayer substrate comprising a diffusion barrier layer, an underlayer, and a ruthenium layer, wherein the underlayer comprises a Group 6 metal and is disposed on the diffusion barrier layer, and the ruthenium layer is disposed on the underlayer, wherein the ruthenium layer has an average roughness Ra and a root mean square roughness Rq less than or equal to about 2 nm.

19. The multi-layer substrate of claim 18, wherein the lower layer consists essentially of molybdenum.

20. The multi-layer substrate of any one of claims 18 to 19, wherein the ruthenium layer consists essentially of ruthenium.

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