Bias block for bias transistors exhibiting non-linearity when designed for linear operations

Abstract

A bias block for a bias transistor that exhibits nonlinearity when designed for linear operation, the bias block for providing a bias voltage, includes a transistor having a control terminal, a first current terminal, and a second current terminal. The voltage level of the control end determines the magnitude of the current between the first current end and the second current end. The first current terminal is connected to a supply voltage through a first impedance, and the second current terminal is connected to a constant reference potential through a second impedance. The second current terminal provides a bias voltage. The bias block also includes a capacitor connected between the control terminal of the transistor and the second current terminal. The bias block provided by the invention can solve the following defects of the existing bias block: (1) any gate leakage current of the QLNA can lead to significant reduction of voltage at two ends of the resistor; and (2) the leakage current of the QLNA changes along with the working temperature, which may cause the change of the size of Vb, so that the performance of the LNA changes greatly along with the change of the temperature, and the like.

Description

[0001] The present patent application is related to and claims priority from the pending Indian provisional patent application, titled “Processing method and temperature compensated bias block with non-linear elimination”, application number IN202241044467, filing date August 3, 2022, attorney case number AURA-336-INPR, which is incorporated herein in its entirety to the extent not inconsistent with the description in the present application.

[0002] The present application is related to and claims priority from a U.S. formal patent application, entitled “BIAS BLOCK FOR BIASING TRANSISTORS EXHIBIT NON-LINEARITY WHEN DESIGNED FOR LINEAR OPERATION”, filed on January 19, 2023, with attorney case number AURA037-US, which is hereby incorporated into the present application in its entirety to the extent that it does not conflict with the description of the present application specification. Technical Field

[0003] Embodiments of the present application generally relate to a bias block, and more particularly to a bias block for biasing transistors that exhibit nonlinearity when designed for linear operation. Background Art

[0004] Transistors are generally used to provide linear operation. A common example of such operation is when the transistor is amplifying in a "linear mode operating region" (e.g., the "saturation region" of a field effect transistor (JFET, MOSFET, etc.) and the "amplification region" of a bipolar transistor (BJT), which is well known in the relevant art.

[0005] Biasing is required when the transistor is used for linear mode operation. Biasing refers to setting an operating point for the transistor for such operation, which is also well known in the relevant art. The operating point is usually defined by a corresponding bias voltage. The "linear mode operating region" is an ideal characteristic of the transistor during operation, but in reality contains nonlinearities, which can cause distortion in the generated output signal. The effect of this nonlinearity is significantly less than the ideal linearity provided by the transistor in generating the overall output signal. As an example of the "degree" of nonlinearity, the output signal obtained from a pure single-tone signal as input to the transistor may contain spurious components (harmonics) whose amplitude is 15-20 decibels (dB) lower than the fundamental signal component corresponding to the ideal pure single-tone output.

[0006] Various aspects disclosed herein are directed to biasing blocks for biasing transistors that exhibit nonlinearity in linear operation. Summary of the invention

[0007] A bias block is used to provide a bias voltage to a first transistor, the bias block comprising: a second transistor having a control terminal, a first current terminal and a second current terminal, wherein the voltage level of the control terminal determines the current size between the first current terminal and the second current terminal; the first current terminal is connected to a power supply voltage through a first impedance; the second current terminal is connected to a constant reference potential through a second impedance; wherein the second current terminal provides the bias voltage to the first transistor.

[0008] The bias block also includes: a first capacitor connected between the control terminal and the second current terminal, wherein the second current terminal, one end of the first capacitor and one end of the second impedance are interconnected at a node; wherein the bias voltage is provided at the node.

[0009] The first current terminal is a drain terminal, the second current terminal is a source terminal, and the control terminal is a gate terminal.

[0010] The first transistor and the second transistor are both pseudo-high electron mobility transistors (pHEMTs).

[0011] The bias block also includes a third transistor, whose drain terminal is connected to the power supply voltage through the temperature compensation block, and whose source terminal is connected to the constant reference potential; a fourth transistor, whose drain terminal is connected to the power supply voltage through a fourth impedance, and whose source terminal is connected to the constant reference potential through a fifth impedance; wherein the control terminal of the third transistor is connected to the source terminal of the fourth transistor; wherein the drain terminal of the third transistor is connected to the control terminal of the second transistor.

[0012] The bias block further includes a second capacitor connected between the third transistor drain terminal and the constant reference potential.

[0013] The temperature compensation block includes a sixth impedance, a seventh impedance and a diode; wherein the sixth impedance and the seventh impedance are connected in series between the power supply voltage and the drain terminal of the third transistor, wherein the anode of the diode is connected to the power supply voltage, and the cathode of the diode is connected to the connection point of the sixth impedance and the seventh impedance.

[0014] The first capacitor has a nonlinear capacitance value capable of predistorting a signal applied at the node; wherein the predistortion is configured to eliminate nonlinearity of the circuit when the circuit is biased by the bias voltage.

[0015] The first capacitor causes the bias block to present a high impedance to a high frequency signal applied at the node.

[0016] Providing the bias voltage at the source terminal of the second transistor causes the bias block to present a DC low impedance at the node; wherein the node provides a drain current of the first transistor.

[0017] A circuit includes an amplifier and a bias block for generating a bias voltage for the amplifier, wherein the bias block includes: a second transistor having a control terminal, a first current terminal and a second current terminal, wherein a voltage level of the control terminal of the second transistor determines a current magnitude between the first current terminal of the second transistor and the second current terminal of the second transistor; the first current terminal of the second transistor is connected to a power supply voltage through a first impedance; the second current terminal of the second transistor is connected to a constant reference potential through a second impedance; wherein the second current terminal of the second transistor provides the bias voltage.

[0018] The amplifier includes a first transistor having a control terminal, a first current terminal and a second current terminal; a load connected between a power supply voltage and the first current terminal, and a source impedance connected between the second current terminal and a constant reference potential; wherein the first transistor is a pseudo-matched high electron mobility transistor (pHEMT); wherein the control terminal of the first transistor is configured to receive a signal to be amplified, and the amplifier generates an amplified signal at the first current terminal of the first transistor; the bias block also includes a first capacitor connected between the control terminal of the second transistor and the second current terminal of the second transistor, the second current terminal of the second transistor, one end of the first capacitor and one end of the second impedance are interconnected at a node; and the bias voltage is provided at the node.

[0019] The first current terminal is a drain terminal, the second current terminal is a source terminal, and the control terminal is a gate terminal, wherein the second transistor is a pseudo-high electron mobility transistor (pHEMT), the amplifier is a low noise amplifier (LNA), and the signal and the amplified signal are both radio frequency (RF) signals.

[0020] The bias block also includes a third transistor, whose drain terminal is connected to the power supply voltage through the temperature compensation block, and whose source terminal is connected to the constant reference potential; a fourth transistor, whose drain terminal is connected to the power supply voltage through a fourth impedance, and whose source terminal is connected to the constant reference potential through a fifth impedance; wherein the control terminal of the third transistor is connected to the source terminal of the fourth transistor, and the drain terminal of the third transistor is connected to the control terminal of the second transistor.

[0021] The bias block also includes a second capacitor connected between the drain terminal of the third transistor and the constant reference potential; wherein the temperature compensation block includes a sixth impedance, a seventh impedance and a diode; the sixth impedance and the seventh impedance are connected in series between the power supply voltage and the drain terminal of the third transistor, the anode of the diode is connected to the power supply voltage, and the cathode of the diode is connected to the connection point of the sixth impedance and the seventh impedance.

[0022] The first capacitor has a capacitance value capable of predistorting a signal applied at the node; wherein the predistortion is configured to eliminate nonlinearity of the amplifier.

[0023] A system includes an antenna and a first transceiver, which includes a transmitting part and a receiving part, each of which is connected to a first duplexer, the first transceiver is used to send a communication signal to a wireless medium through the first duplexer and the antenna, and the first transceiver is also used to receive a communication signal from the wireless medium through the first duplexer and the antenna, wherein the receiving part includes a low noise amplifier (LNA) and a bias block for generating a bias voltage for the LNA, wherein the bias block includes a second transistor, which has a control terminal, a first current terminal and a second current terminal, wherein the voltage level of the control terminal of the second transistor determines the current size between the first current terminal of the second transistor and the second current terminal of the second transistor; the first current terminal of the second transistor is connected to a power supply voltage through a first impedance; the second current terminal of the second transistor is connected to a constant reference potential through a second impedance; wherein the second current terminal of the second transistor provides the bias voltage.

[0024] The amplifier includes a first transistor having a control terminal, a first current terminal and a second current terminal; a load connected between a power supply voltage and the first current terminal, and an impedance connected between the second current terminal and a constant reference potential; wherein the first transistor is a pseudo-matched high electron mobility transistor (pHEMT); the bias block also includes: a first capacitor connected between the control terminal of the second transistor and the second current terminal of the second transistor, wherein the second current terminal of the second transistor, one end of the first capacitor and one end of the second impedance are interconnected at a node; and the bias voltage is provided at the node.

[0025] The first current terminal is a drain terminal, the second current terminal is a source terminal, and the control terminal is a gate terminal, wherein the second transistor is a pseudo-high electron mobility transistor (pHEMT), and the bias block also includes a third transistor, whose drain terminal is connected to the power supply voltage through a temperature compensation block, and whose source terminal is connected to the constant reference potential; a fourth transistor, whose drain terminal is connected to the power supply voltage through a fourth impedance, and whose source terminal is connected to the constant reference potential through a fifth impedance; wherein the control terminal of the third transistor is connected to the source terminal of the fourth transistor, and the drain terminal of the third transistor is connected to the control terminal of the second transistor.

[0026] The bias block also includes a second capacitor connected between the drain terminal of the third transistor and the constant reference potential; wherein the temperature compensation block includes a sixth impedance, a seventh impedance and a diode; the sixth impedance and the seventh impedance are connected in series between the power supply voltage and the drain terminal of the third transistor, the anode of the diode is connected to the power supply voltage, and the cathode of the diode is connected to the connection point of the sixth impedance and the seventh impedance; the first capacitor has a nonlinear capacitance value, which can pre-distort the signal applied at the node; the pre-distortion configuration is to eliminate the nonlinearity of the circuit when the circuit is biased by the bias voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Example embodiments disclosed in the present application will be described below with reference to the accompanying drawings which are briefly described later.

[0028] FIG. 1 is a block diagram of an example circuit in which several aspects disclosed herein may be implemented.

[0029] Figure 2 is a circuit diagram showing implementation details of a bias block in an embodiment disclosed in the present application.

[0030] Figure 3 is a schematic diagram of relevant parts of a bias block in an embodiment disclosed in the present application, for illustrating the determination of the apparent impedance (under various conditions) at a node providing a bias voltage.

[0031] Figure 4 It is a partial schematic diagram of a bias block in an embodiment disclosed in the present application, and is used to illustrate the elimination of nonlinearity of a device / circuit using the bias block.

[0032] Figure 5 is a block diagram illustrating implementation details of a system including one or more devices that employ one or more bias blocks implemented according to several aspects disclosed herein.

[0033] In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit in the corresponding reference numeral. DETAILED DESCRIPTION

[0034] 1. Overview

[0035] According to one aspect disclosed in the present application, a bias block for providing a bias voltage includes a transistor having a control terminal, a first current terminal, and a second current terminal. The voltage level of the control terminal determines the magnitude of the current between the first current terminal and the second current terminal. The first current terminal is connected to a power supply voltage through a first impedance, and the second current terminal is connected to a constant reference potential through a second impedance. The second current terminal provides the bias voltage.

[0036] The bias block also includes a capacitor connected between the transistor control terminal and the second current terminal. The capacitor enables the bias block to present a high impedance to a high frequency signal applied at the node. The bias voltage provided at the second current terminal enables the bias block to present a DC low impedance at the node.

[0037] According to another aspect of the present disclosure, a capacitor has a capacitance value capable of predistorting a signal applied at a node, the predistortion being configured to eliminate nonlinearity of the circuit when the circuit is biased by a bias voltage.

[0038] In one embodiment, the transistors of the bias block are pseudo-matched high electron mobility transistors (pHEMTs).

[0039] Several aspects disclosed in the present application will be described below with reference to examples. However, those skilled in the relevant art will recognize that the disclosure of the present application can be implemented in the absence of one or more specific details or using other methods, components, materials, etc. In other cases, in order to avoid blurring the features disclosed in the present application, known structures, materials or operations are not shown in detail. In addition, the described features / aspects can be implemented in various combinations, but for the sake of brevity, only some of these combinations are described herein.

[0040] 2. Example Circuit / Equipment

[0041] FIG. 1 is a block diagram of an example circuit expanded according to several aspects disclosed herein. The circuit 100 shown includes an existing bias block 10 and a low noise amplifier (LNA) 20. The specific details of the LNA 20 are shown only by way of illustration. The LNA 20 may also be implemented in different ways, which will be apparent to those skilled in the relevant art. In addition, the LNA is only an example circuit that may employ the bias block disclosed herein. In general, in alternative embodiments according to other aspects of the present application, any circuit or block / device that includes one or more transistors that need to operate in a linear mode may replace the LNA.

[0042] In the description provided below, the transistors shown and described are pseudo-matched high electron mobility transistors (pHEMTs), also known as heterojunction field effect transistors (HFETs) or modulation doped heterojunction field effect transistors (MODFETs), which can be used as junction field effect transistors (JFETs), and the circuits / blocks using such transistors are radio frequency (RF) circuits used in wireless communications. As is well known in the art, pHEMT transistors use two materials with different band gaps (i.e., heterojunctions) to form a junction that acts as a current channel. Commonly used material combinations for pHEMT include gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs). In the specific embodiments described herein, all transistors are enhancement-mode pHEMTs (represented in the accompanying drawings by symbols that are usually n-channel JFETs). However, as described in the following sections, other types of transistors (including depletion-mode transistors) may also be used according to the aspects disclosed in the present application.

[0043] LNA 20 may be a circuit / block in a receiver chain of a wireless or wired receiver (located after the antenna) that is used to amplify a received input signal and reduce noise to a minimum or even no signal. With respect to LNA 20, signal 141 (RFin) represents a received radio frequency (RF) signal to be amplified. The LNA 20 shown in the figure includes a DC blocking capacitor 140, a pHEMT transistor 160, an inductor 150, an inductor 171, a resistor 172, a capacitor 173, and a DC blocking capacitor 180. Inductor 150 is used to improve the noise performance of LNA 20. A resistor with an appropriate resistance value may also be used instead of inductor 150. Vc (101) represents a power supply voltage and node 199 represents a ground terminal. The common combination of elements 171, 172, and 173 forms a load that sets the passband of LNA 20 (usually the same as the signal band of RFin). RFout (190) is the amplified output of LNA 20.

[0044] A bias voltage is required for linear operation of transistor 160. Various aspects of the present disclosure may be better understood by comparing with the disadvantages of existing bias blocks, which are briefly described below.

[0045] The bias voltage Vb (161) is generated by the existing bias block 10, which is shown to include a pHEMT transistor 120, resistors 110, 112 and 114, and a bypass capacitor 130. Transistor 120 is configured as a diode-connected transistor. The values ​​of resistors 110 and 120 determine the voltage at the gate terminal of transistor 120, which is generally slightly greater than the threshold voltage (Vth) of transistor 120 due to the configuration of transistor 120. Resistor 112 is used to limit current consumption when the gate node of transistor 120 is grounded (via a switch, not shown) to set circuit 100 to a "sleep", "standby" or low power mode. Resistor 114 has a relatively large resistance to isolate bias block 10 from RFin (141) by preventing or minimizing Rfin from flowing / leaking into bias block 10. Generally, at least for LNAs, the resistance value of resistor 114 needs to be high enough so that its contribution to the noise figure (NF) is less than that of the LNA. Assuming that the gate current in transistor 160 (QLNA) is zero, the gate voltage of transistor 160 is equal to the gate voltage of transistor 120. Bypass capacitor 130 is used to minimize (high frequency) fluctuations in the gate voltage of transistor 120.

[0046] One disadvantage of the prior art bias block 10 is that any gate leakage current of the QLNA will cause a significant voltage drop across resistor 114. As a result, the gate voltage of the QLNA (which is the same as Vb, assuming only DC conditions) will be less than the gate voltage of transistor 120. In addition, the leakage current of the QLNA varies with operating temperature. This can cause changes in the magnitude of Vb, and thus cause the performance of the LNA 20 to vary significantly with temperature, because the leakage current will vary. Changes in leakage current are generally difficult to model and therefore difficult to compensate for.

[0047] The bias voltage Vb may also vary due to temperature variations of the transistor 120 , for example, due to temperature-induced changes in the threshold voltage of the transistor 120 .

[0048] The above-mentioned variation of Vb generally causes distortion of RFout generated by LNA 20 .

[0049] In addition, the inherent nonlinearity of the LNA 20 itself may be another source of RFout distortion.

[0050] The bias blocks employed in accordance with several aspects of the present disclosure reduce or eliminate the above-mentioned problems, as described below.

[0051] 3. Bias block

[0052] Figure 22 is a circuit diagram showing implementation details of the bias block in the embodiment disclosed in the present application. The bias block 200 shown in the figure includes resistors 250 (R1), 255 (R2), 227 (R4), 263 (R5), 225 (R6), 226 (R7), 235 (R8) and 236 (R9), pHEMT transistors 210 (Q1), 220 (Q2) and 230 (Q3), diode 240 and capacitors 260 (C1) and 270 (Cgs). Vcc (201) represents the power supply voltage and node 299 represents the ground terminal. The bias voltage Vbias (233) is provided at the source terminal of Q3.

[0053] The series connection of R1 and R2 is between Vcc and the drain terminal of Q1. A diode 240 is connected in parallel with R1. The anode of diode 240 is connected to Vcc, and the cathode of diode 240 is connected to the connection point of R1 and R2. The drain of Q1 is connected to the gate of Q2 through R4. The source of Q1 is grounded. Resistor R7 is connected between the source terminal of Q2 and ground. The source terminal of Q2 is connected to the gate of Q1. Resistor R6 is connected between the drain of Q2 and Vcc.

[0054] Capacitor C1 is connected between the drain of Q1 and ground. Resistor R5 is connected between the drain of Q1 and the gate of Q3. Resistor R8 is connected between the drain of Q3 and Vcc. Resistor R9 is connected between the source of Q3 and ground. Capacitor Cgs is connected between the gate and source of Q3. The source of Q3 provides a bias voltage Vbias (233).

[0055] In bias block 200, instead of providing Vbias from the gate of Q1 (as shown in prior art bias block 10 in FIG. 1), the drain of Q1 is connected to the gate of Q3, and Vbias is provided at the source of Q3 (233). In effect, the voltage at the gate of Q1 is "raised" by connecting the drain of Q1 to the gate of Q3 (via R5). The voltage at the gate of Q3 is then "lowered" by the same magnitude as the "raised" voltage at the gate of Q1. Ideally, the magnitude of the raise would be substantially equal to the magnitude of the lowering. Thus, the operating points or operating conditions of transistors Q2 and Q3 are substantially the same.

[0056] To ensure this is the case, the resistance values ​​of resistor pairs 227 and 263, 225 and 235, and 226 and 236 should be selected accordingly. For example, the resistance values ​​of resistors 227 and 263 may be selected to be substantially equal, the resistance values ​​of resistors 225 and 235 may be selected to be substantially equal, and the resistance values ​​of resistors 226 and 236 may be selected to be substantially equal. Transistors Q2 and Q3 are also matched transistors. Therefore, the voltage Vbias (233) is substantially equal to the gate voltage of Q1. However, it will be appreciated that since Vbias is now provided at the source terminal of Q3, the Vbias node presents a low impedance at DC (0 Hz), as described below. The application of Cgs causes the impedance at Vbias (the input impedance) to be higher at RF, as described below.

[0057] C1 provides high frequency noise filtering. Cgs enables the bias block 200 to provide a high impedance at RF while also helping to eliminate non-linearities of a device / circuit, such as an LNA connected to receive Vbias to bias the transistors of the device / circuit.

[0058] The specific structure of the bias block 200 makes Vbias (233) a temperature compensated stable voltage. The bias block 200 provides low impedance at DC (0 Hz), high impedance at high frequency (RF) (no need to use large value resistors, such as resistor 114 of the existing bias block 10), and can provide the additional current (due to gate leakage) required by the gate of the pHEMT transistor (e.g., LNA) biased by Vbias.

[0059] In addition, the application of Cgs can also adjust the nonlinear impedance presented at the Vbias node 233 (for example, presented by the pHEMT transistor of the LNA in FIG. 1), thereby being able to cancel the inherent nonlinearity of the LNA ( Figure 2 1 ), thereby achieving better LNA linearity. In order to ensure this cancellation, the capacitance value of capacitor Cgs needs to be nonlinear in order to offset (mitigate or eliminate) the inherent nonlinearity of the LNA. In the embodiment disclosed in the present application, this nonlinear capacitance is achieved by implementing Cgs as a reverse biased diode using another pHEMT transistor of appropriate construction. As is well known in the art, the capacitance value of a reverse biased diode depends on the voltage across the reverse biased diode. However, other implementations of Cgs may also be used.

[0060] The manner in which the bias block 200 achieves the above-mentioned advantages is described next.

[0061] 4. DC low impedance and RF high impedance

[0062] The bias block 200 provides a low impedance at DC and a high impedance at RF. Specifically, the high impedance at RF is achieved at least in part by applying Cgs to the gate and source nodes of Q3.

[0063] Figure 3 is a schematic diagram of the relevant portion of bias block 200, which is used to determine the impedance presented by bias block 200 to an external signal (not shown, but may be an RF input signal to the LNA biased by bias block 200) (i.e., the apparent impedance at the source terminal of Q3). Transistor Q3 of bias block 200 is shown as its equivalent circuit model. For high frequencies (RF), capacitors may be replaced by short circuits, so at RF, C1 may be shorted to ground, as shown in FIG. Figure 3 As shown. Vgs is the gate-source voltage of Q3. Gm is the transconductance of Q3. At RF, Cgs is short-circuited, so Vgs is zero. Current source 310 generates a current of gm*Vgs. The apparent impedance Zin at the Vbias node can be expressed by the following relationship:

[0064] Zin=R9||R5||((1 / gm)+R8))………… Formula 1

[0065] in,

[0066] The symbol || indicates "parallel" operation.

[0067] 1 / gm is the impedance caused by element 310 .

[0068] Since the capacitance Cgs causes Vgs=0 at RF, 1 / gm is reduced to 0.

[0069] Therefore, Zin=R9||R5||R8…………Formula 2

[0070] R8 and R5 are usually large value resistors. R9 is usually much smaller in value than R8 and R5, so R9 is the primary factor in determining Zin, as shown in Equation 2 above. By deliberately choosing a sufficiently large value for R9 (while still achieving the appropriate / desired current through transistor Q3), Zin in Equation 2 can be made into a large impedance.

[0071] At DC, the input impedance Zin is approximately equal to 0, or a very small value, because the (1 / gm) component of Zin is very close to 0 (gm is usually a very high value) as shown in Equation 1 above.

[0072] Therefore, Zin is very large at RF and very small at DC.

[0073] Thus, at RF, bias block 200 presents a larger impedance to a signal applied to Vbias. In the case of an LNA (connected to Vbias in a manner similar to FIG. 1 ), an RF signal applied to Vbias will “see” a higher input impedance Zin and will therefore not leak into the bias block and thus will not affect the magnitude of Vbias (233). Furthermore, bias block 200 achieves this effect without the need for a large value resistor such as resistor 114 of prior bias block 10.

[0074] Furthermore, any gate leakage current of a transistor (e.g., an LNA) whose gate is connected to Vbias can be supplied by the bias block 200 (due to the low impedance at DC) without causing large changes in the magnitude of Vbias. Furthermore, since the changes in Vbias are zero or very small, temperature-related changes in gate leakage current do not cause large changes in the performance of the LNA with temperature changes.

[0075] Next, the manner in which the bias block 200 eliminates or minimizes the nonlinear effects of the device / circuit (eg, LNA) connected thereto will be described.

[0076] 4. Nonlinear elimination

[0077] According to another aspect disclosed herein, the bias block 200 can be adjusted to minimize or eliminate the nonlinearity of a device / circuit (e.g., LNA) biased by Vbias. Specifically, the application of Cgs can achieve pre-distortion, which can be used to eliminate the inherent nonlinearity of the device / circuit, thereby achieving better linearity.

[0078] Figure 4 FIG. 2 is a partial schematic diagram of the bias block 200. The LNA 20 in FIG. 1 is also shown in the figure. In the bias block 200 portion shown, except for R5, R8, R9 and Cgs (with Figure 2 2 ), a parasitic gate-to-ground capacitance Cgg (420) and a gate-to-source diode 410 internal to (i.e., intrinsic to) Q3 are also shown. Cgg and diode 410 are not additional elements added to bias block 200, but rather are intrinsic parasitic capacitors and diodes formed by the gate and source of Q3, respectively.

[0079] It can be seen that at high frequencies (and with the resistance value of R9 set to a high value), the apparent impedance Zin at the Vbias node (233) is expressed by the following formula:

[0080] Zin=(1 / gm)*[(Cd+Cgs+Cgg) / Cgg]……Formula 4

[0081] in,

[0082] gm is the transconductance of Q3,

[0083] Cd is the capacitance of the reverse biased (below the knee voltage or breakdown voltage) gate-source diode, which is externally represented as diode 410,

[0084] Cgg is the gate-to-ground parasitic capacitance between the gate of Q3 and ground,

[0085] “*” represents multiplication operation.

[0086] As is well known, Cd, as the capacitance value of a diode (particularly a reverse biased diode), varies in a nonlinear manner as the voltage across the diode varies. Applying Rfin (141) to the LNA 20 (now biased to Vbias) changes the voltage across the diode, causing Cd and, accordingly, Zin to vary in a nonlinear manner. This property can be used to eliminate or minimize the inherent nonlinearity of the LNA 20. It should be noted that even though the capacitance of Cd varies as the voltage at the Vbias node varies, Cd itself is typically too small to eliminate the nonlinearity. Therefore, the cancellation is achieved by selecting the capacitance value of Cgs. That is, the capacitance value of (Cd+Cgs) varies (due to the variation of Cd) such that the variation of (Cd+Cgs) is within the range required to eliminate the nonlinearity of the LNA 20.

[0087] To determine the capacitance value of Cgs required for cancellation, the characteristics and degree of nonlinearity of LNA 20 are determined in a known manner. The capacitance of Cgs is then determined so that (Cd + Cgs) causes a change in Zin (due to Cd) that cancels or minimizes the nonlinearity. For example, such a numerical determination may be made using circuit simulation or any other appropriate technique. Cgs applied in bias block 200 has a determined capacitance value. Thus, Rfin causes Zin to change in a manner such that the voltage provided as input to LNA 20 (i.e., the voltage at Vbias) is intentionally predistorted to the extent required to cancel or minimize the nonlinearity caused by LNA 20. Thus, the relationship between Rfout and Rfin may appear substantially linear.

[0088] It can be appreciated from the above description that providing Vbias at the source of Q3 in combination with applying Cgs can eliminate non-linearity of the device / circuit biased by the bias block 200 .

[0089] According to another aspect of the present disclosure, the bias block 200 has built-in temperature compensation, which will be described below.

[0090] 5. Built-in temperature compensation

[0091] The use of diode 240, R1 and R2 can compensate (or correct) for temperature variations in Vbias (233). Figure 2As mentioned above, the magnitude of Vbias (233) is substantially equal to the voltage at the gate of Q1. As the operating (ambient) temperature increases, the threshold voltage Vth of the pHEMT transistor (or FET in general) decreases, resulting in a decrease in Vbias (the magnitude of Vbias is the same as the voltage (Vth) at the gate of Q1). Therefore, a temperature compensation mechanism is required to keep Vbias substantially constant as the temperature changes.

[0092] As temperature increases, the current-voltage (IV) relationship curve of the forward biased diode 240 moves to the left, which is well known in the relevant art. Therefore, the voltage (Vf) across the diode 240 decreases, thereby increasing the voltage at the drain terminal of Q1. Therefore, the gate voltage of Q1 and Vbias (233) increase accordingly to compensate for the decrease in Vbias due to the increase in temperature if there is no temperature compensation. Therefore, despite the change in temperature, Vbias remains constant. The resistance values ​​of R1 and R2 are selected to accurately compensate for the degree of temperature changes to keep Vbias (233) constant. The combination of R1, R2 and diode 240 can be considered as a temperature compensation block 290.

[0093] The bias block 200 as described above may be incorporated into one or more devices of a system, as will be described below.

[0094] 6. System

[0095] Figure 5 is a block diagram showing implementation details of a system including one or more devices that employs one or more bias blocks such as the bias block 200 described above. Figure 5 In the example of FIG. 5 , RF devices such as LNA 516, receive RF block 515, transmit RF block 512, and power amplifier 513 may employ bias block 200 to bias corresponding transistors (eg, pHEMTs or other types described above) therein.

[0096] Figure 5The system can be deployed in a base transceiver station (BTS) of a cellular telephone system (eNodeB in LTE-Long Term Evolution) and is labeled herein as BTS system 500. Broadly speaking, BTS system 500 facilitates wireless communications between user equipment (UE), which can be a mobile station (e.g., a cell phone) or a fixed user equipment such as a computer with an Internet connection. BTS system 500 can be implemented in accordance with technologies and standards such as GSM, CDMA, 3G, 4G, LTE, 5G, etc. The BTS system 500 shown includes transceivers 510A to 510N, duplexers 520A to 520N, a combiner 530, and an antenna 540. The specific elements / blocks of BTS system 500 are shown only by way of illustration. However, as is known in the relevant art, BTS system 500 may generally include more elements / blocks, such as temperature sensors, maintenance and configuration blocks, etc.

[0097] Each of the transceivers 510A to 510N is used to send communication signals to and receive communication signals from wireless user devices via corresponding duplexers 520A-520N, combiners 530, and antennas 540. Each transceiver includes a transmitting portion and a receiving portion. Therefore, the illustrated transceiver 510A includes a transmitting portion including a transmitting baseband block 511, a transmitting RF block 512, and a power amplifier 513, and a receiver portion including a low noise amplifier (LNA) 516, a receiving RF block 515, and a receiving baseband block 514.

[0098] The transmit baseband block 511 receives information signals (e.g., voice, data) from a base station controller (BSC) (which in turn receives communication signals from another user device (wireless or fixed) in the downstream network of the BSC) via the corresponding paths shown in the bus 599, processes the signals for modulation, channel coding and other operations according to the corresponding techniques and protocols, and forwards the processed signals to the transmit RF block 512. The transmit RF block 512 may perform operations such as up-conversion to RF (radio frequency) and forward the RF signals to the power amplifier 513. The power amplifier 513 amplifies the received RF signals and transmits the power-amplified signals to the corresponding wireless user devices via the duplexer 520A, the combiner 530 and the antenna 540.

[0099] LNA 516 may be implemented as LNA 20 (as shown in FIG. 1 and further expanded according to the above disclosure), and may employ bias block 200 as described above. LNA 516 receives an RF signal from a wireless user device through duplexer 520A, combiner 530, and antenna 540, amplifies the RF signal, and forwards the amplified RF signal to receive RF block 515. Receive RF block 515 down-converts the RF signal to a baseband frequency and forwards the baseband signal to receive baseband block 514. Receive baseband block 514 may perform operations such as demodulation, error correction, etc. on the baseband signal to obtain an information signal (e.g., data, voice), and forward the information signal to BSC through a corresponding path in bus 599.

[0100] The clock 517 generates one or more clocks required for the operation of digital units in the transceiver 510. For example, the transmit baseband block 511 and the receive baseband block 514 may contain one or more processors that require clock driving operation.

[0101] Figure 5 The transmitters, receivers and clocks of the other transceivers in the embodiment operate similarly to the transceiver 510A described above and include corresponding transmitter and receiver blocks.

[0102] Each of the duplexers 520A to 520N is capable of implementing respective transmit and receive signals (i.e., bidirectional (duplex) communication) on a single path between the corresponding duplexer and the combiner 530. Each of the duplexers 520A to 520N may be implemented by using two parallel bandpass filters, one of which provides a path between the corresponding transmitter and the combiner 530, and the other of which provides a path between the combiner 530 and the corresponding receiver.

[0103] The combiner 530 combines signals from / to the transceivers 510A to 510N so that all signals can be transmitted and received using a single antenna 540 .

[0104] Antenna 540 is used to receive and transmit wireless signals carrying information from and to the wireless medium between the transceiver and the wireless user equipment.

[0105] For at least the reasons described above, the implementation and use of bias block 200 solves some of the problems noted with prior bias blocks, such as prior bias block 10. Specifically, due to the low impedance of bias block 200 at DC, it can provide the additional gate leakage current required to bias the transistor. The new bias block provides a high impedance at RF without any series elements between the bias block and the amplifier, and thus does not have the aforementioned problems. The new bias block can also be adjusted to provide a nonlinear impedance to the signal path, which in turn can be used to improve the nonlinearity of a circuit (e.g., an LNA) using the new bias block.

[0106] Although the above description is directed to pHEMT transistors, it must be understood that other types of transistors may be used in place of pHEMTs, with or without corresponding changes to the circuit, which will be apparent to a person skilled in the art from reading the disclosure of the application. In general, any transistor that is a "voltage controlled current source" type device and has a gate-source diode (e.g., 410) that is inherently present in the transistor or added to the outside of the transistor can be used in place of Q3 and each transistor of the applied bias block 200. If it is not desired to eliminate or mitigate the nonlinearity of a device / circuit (e.g., an LNA) biased by the bias block, then any transistor that is a "voltage controlled current source" type component will suffice. In addition, circuits / blocks using transistors may also be implemented to process wired signals (and / or RF / wireless signals)

[0107] 6. Conclusion

[0108] References to "one embodiment", "an embodiment" or similar expressions in this specification mean that a particular feature, structure or characteristic associated with the embodiment is included in at least one embodiment disclosed in the present application. Therefore, the phrases "in one embodiment", "in an embodiment" and similar expressions appearing in this specification may (but not necessarily) all refer to the same embodiment.

[0109] Although in Figures 1 to Figure 5 The terminals / nodes are shown as being directly connected (i.e., "connected to") various other terminals, but it should be understood that other elements may also be present in the path (as appropriate to the particular environment), so the connections can be viewed as being "electrically coupled" to the same connection terminal.

[0110] It should be understood that the specific types of transistors described above (e.g., pHEMT, N-type, P-type, etc.) are for illustration only. However, alternative embodiments using different configurations and transistors will be apparent to those skilled in the art by reading the disclosure provided herein. For example, an N-type transistor may be replaced with a P-type transistor, while also swapping the connections to the power and ground terminals.

[0111] Therefore, in this application, the power supply and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) of the transistor (providing a current path when turned on and an open circuit when turned off) are referred to as current terminals, and the gate (base) terminal is referred to as the control terminal.

[0112] Although various embodiments of the present disclosure have been described above, it should be understood that these embodiments are presented by way of example only and not limitation. Therefore, the breadth and scope of the present disclosure should not be limited by any of the above embodiments, but should be defined according to the claims and their equivalents.

Claims

1. A bias block for providing a bias voltage to a first transistor, the first transistor being used to amplify an RF signal connected to a control terminal of the first transistor, characterized in that The bias block comprises: A second transistor having a control terminal, a first current terminal and a second current terminal, wherein a voltage level of the control terminal determines a current magnitude between the first current terminal and the second current terminal; The first current terminal is connected to a power supply voltage via a first impedance; The second current terminal is connected to a constant reference potential via a second impedance; The second current terminal provides the bias voltage to the first transistor.

2. The bias block according to claim 1, characterized in that The bias block further comprises: A first capacitor connected between the control terminal and the second current terminal wherein the second current terminal, one end of the first capacitor and one end of the second impedance are connected to each other at a node; Wherein, the bias voltage is provided at the node.

3. The bias block according to claim 2, characterized in that: The first current terminal is a drain terminal, the second current terminal is a source terminal, and the control terminal is a gate terminal.

4. The bias block according to claim 3, characterized in that: The first transistor and the second transistor are both pseudo-high electron mobility transistors (pHEMTs).

5. The bias block according to claim 3, characterized in that: Also includes a third transistor having a drain terminal connected to the supply voltage through a temperature compensation block and a source terminal connected to the constant reference potential; a fourth transistor having a drain terminal connected to the supply voltage via a fourth impedance and a source terminal connected to the constant reference potential via a fifth impedance; wherein the control terminal of the third transistor is connected to the source terminal of the fourth transistor; Wherein, the drain terminal of the third transistor is connected to the control terminal of the second transistor.

6. The bias block according to claim 5, characterized in that: A second capacitor is also included, which is connected between the drain terminal of the third transistor and the constant reference potential.

7. The bias block according to claim 6, characterized in that: The temperature compensation block includes a sixth impedance, a seventh impedance and a diode; wherein the sixth impedance and the seventh impedance are connected in series between the power supply voltage and the drain terminal of the third transistor, The anode of the diode is connected to the power supply voltage, and the cathode of the diode is connected to a connection point of the sixth impedance and the seventh impedance.

8. The bias block according to claim 3, characterized in that: The first capacitor has a nonlinear capacitance value capable of pre-distorting a signal applied at the node; Wherein the predistortion is configured to eliminate nonlinearity of the circuit when the circuit is biased by the bias voltage.

9. The bias block according to claim 3, characterized in that: The first capacitor causes the bias block to present a high impedance to a high frequency signal applied at the node.

10. The bias block according to claim 3, characterized in that: providing the bias voltage at the source terminal of the second transistor so that the bias block presents a DC low impedance at the node; The node provides a leakage current of the first transistor.

11. A circuit comprising an amplifier and a bias block for generating a bias voltage for the amplifier, wherein the amplifier is used to amplify an RF signal, characterized in that: The bias block comprises: a second transistor having a control terminal, a first current terminal, and a second current terminal, wherein a voltage level of the control terminal of the second transistor determines a current magnitude between the first current terminal of the second transistor and the second current terminal of the second transistor; A first current terminal of the second transistor is connected to a power supply voltage via a first impedance; A second current terminal of the second transistor is connected to a constant reference potential via a second impedance; The second current terminal of the second transistor provides the bias voltage.

12. The circuit according to claim 11, characterized in that The amplifier comprises: A first transistor having a control terminal, a first current terminal, and a second current terminal; a load connected between the supply voltage and the first current terminal, and a source impedance connected between the second current terminal and a constant reference potential; Wherein, the first transistor is a pseudo-matched high electron mobility transistor (pHEMT); wherein the control terminal of the first transistor is configured to receive a signal to be amplified, and the amplifier generates an amplified signal at the first current terminal of the first transistor; Wherein, the bias block further includes: a first capacitor connected between the control terminal of the second transistor and the second current terminal of the second transistor, wherein the second current terminal of the second transistor, one end of the first capacitor and one end of the second impedance are connected to each other at a node; Wherein, the bias voltage is provided at the node.

13. The circuit according to claim 12, characterized in that: The first current terminal is a drain terminal, the second current terminal is a source terminal, and the control terminal is a gate terminal. Wherein, the second transistor is a pseudo-matched high electron mobility transistor (pHEMT), The amplifier is a low noise amplifier (LNA), and both the signal and the amplified signal are radio frequency (RF) signals.

14. The circuit according to claim 13, characterized in that The bias block further comprises: a third transistor having a drain terminal connected to the supply voltage through a temperature compensation block and a source terminal connected to the constant reference potential; a fourth transistor having a drain terminal connected to the supply voltage via a fourth impedance and a source terminal connected to the constant reference potential via a fifth impedance; Wherein, the control terminal of the third transistor is connected to the source terminal of the fourth transistor, Wherein, the drain terminal of the third transistor is connected to the control terminal of the second transistor.

15. The circuit according to claim 14, characterized in that: The bias block further includes a second capacitor connected between the third transistor drain terminal and the constant reference potential; Wherein, the temperature compensation block includes a sixth impedance, a seventh impedance and a diode; wherein the sixth impedance and the seventh impedance are connected in series between the power supply voltage and the drain terminal of the third transistor, The anode of the diode is connected to the power supply voltage, and the cathode of the diode is connected to a connection point of the sixth impedance and the seventh impedance.

16. The circuit according to claim 12, characterized in that: The first capacitor has a capacitance value capable of predistorting a signal applied at the node; Wherein, the predistortion is configured to eliminate the nonlinearity of the amplifier.

17. A system, characterized in that: include Antenna, and a first transceiver including a transmitting portion and a receiving portion, each portion being connected to a first duplexer, the first transceiver being configured to transmit a communication signal to a wireless medium via the first duplexer and the antenna, and the first transceiver being configured to receive a communication signal from the wireless medium via the first duplexer and the antenna, Wherein, the receiving part comprises: a low noise amplifier (LNA) and a bias block for generating a bias voltage for the LNA, Wherein, the bias block comprises: a second transistor having a control terminal, a first current terminal, and a second current terminal, wherein a voltage level of the control terminal of the second transistor determines a current magnitude between the first current terminal of the second transistor and the second current terminal of the second transistor; A first current terminal of the second transistor is connected to a power supply voltage via a first impedance; A second current terminal of the second transistor is connected to a constant reference potential via a second impedance; Wherein, the second current terminal of the second transistor provides the bias voltage; The sizes of the first impedance and the second impedance are both implemented so that the bias block provides a high input impedance for the received communication signal at the second current terminal.

18. The system according to claim 17, characterized in that The amplifier comprises: A first transistor having a control terminal, a first current terminal, and a second current terminal; a load connected between the supply voltage and the first current terminal, and an impedance connected between the second current terminal and a constant reference potential; Wherein, the first transistor is a pseudo-matched high electron mobility transistor (pHEMT); Wherein, the bias block further includes: a first capacitor connected between the control terminal of the second transistor and the second current terminal of the second transistor, wherein the second current terminal of the second transistor, one end of the first capacitor and one end of the second impedance are connected to each other at a node; Wherein, the bias voltage is provided at the node.

19. The system according to claim 18, characterized in that: The first current terminal is a drain terminal, the second current terminal is a source terminal, and the control terminal is a gate terminal. Wherein, the second transistor is a pseudo-matched high electron mobility transistor (pHEMT), Wherein, the bias block further includes: a third transistor having a drain terminal connected to the supply voltage through a temperature compensation block and a source terminal connected to the constant reference potential; a fourth transistor having a drain terminal connected to the supply voltage via a fourth impedance and a source terminal connected to the constant reference potential via a fifth impedance; Wherein, the control terminal of the third transistor is connected to the source terminal of the fourth transistor, Wherein, the drain terminal of the third transistor is connected to the control terminal of the second transistor.

20. The system according to claim 19, characterized in that: The bias block further includes a second capacitor connected between the third transistor drain terminal and the constant reference potential; Wherein, the temperature compensation block includes a sixth impedance, a seventh impedance and a diode; wherein the sixth impedance and the seventh impedance are connected in series between the power supply voltage and the drain terminal of the third transistor, wherein the anode of the diode is connected to the power supply voltage, and the cathode of the diode is connected to a connection point of the sixth impedance and the seventh impedance; wherein the first capacitor has a nonlinear capacitance value, which can predistort a signal applied at the node; Wherein the predistortion is configured to eliminate nonlinearity of the circuit when the circuit is biased by the bias voltage.

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