Circuit board and method for manufacturing circuit board

Abstract

This circuit board is provided with a fluororesin layer, an adherend layer, and an adhesive layer that adheres the fluororesin layer and the adherend layer, the fluororesin layer containing polytetrafluoroethylene and a first inorganic filler, and the content of the first inorganic filler in the fluororesin layer being 50-66 vol%, inclusive. The adhesive layer contains a resin and a second inorganic filler, the fluororesin content of the resin is 5% by mass or less, the second inorganic filler content of the adhesive layer is 29-47% by volume, and through-holes penetrating the fluororesin layer and the adhesive layer are formed.

Description

Technical Field

[0001] The present disclosure relates to a circuit substrate and a method for manufacturing the circuit substrate.

[0002] This application claims the benefit of priority based on Japanese Application No. 2022-162209 filed on October 7, 2022, and incorporates by reference all the contents described in the aforementioned Japanese Application. Background Art

[0003] In order to improve the high frequency characteristics of a printed wiring board, use of a fluororesin layer containing a fluororesin such as polytetrafluoroethylene and an inorganic filler such as silica as a dielectric layer has been studied (Patent Document 1).

[0004] In order to stack a substrate (circuit substrate) in which a circuit is formed by processing a metal layer of a substrate with other substrates or other circuit substrates, a bonding sheet is used. For example, after the circuit substrate, the bonding sheet and other substrates are stacked in sequence, the bonding sheet is heated until the bonding sheet softens. In the softened state of the bonding sheet, the bonding sheet is pressurized to deform it. The bonding sheet is used to fill the circuit space, and the circuit substrate is bonded to other substrates (Patent Document 2).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2021 / 235276

[0008] Patent Document 2: Japanese Patent Application Publication No. 2016-27131 Summary of the invention

[0009] The circuit board of the present disclosure comprises:

[0010] Fluororesin layer;

[0011] a bonded layer; and

[0012] an adhesive layer for bonding the fluororesin layer to the adhered layer,

[0013] The fluororesin layer comprises polytetrafluoroethylene and a first inorganic filler,

[0014] The content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less,

[0015] The adhesive layer comprises a resin and a second inorganic filler,

[0016] The fluororesin content of the resin is 5% by mass or less,

[0017] The content of the second inorganic filler in the adhesive layer is 29 volume % or more and 47 volume % or less,

[0018] A through hole is formed that penetrates the fluororesin layer and the adhesive layer.

[0019] The method for manufacturing a circuit substrate disclosed in the present invention is the method for manufacturing the circuit substrate described above.

[0020] The method further comprises the step of bonding the fluororesin layer to the adhered layer by holding a laminated body in which the fluororesin layer, the adhesive layer, and the adhered layer are laminated in this order at a temperature of 180° C. or lower to soften the adhesive layer.

[0021] The method for manufacturing a circuit substrate disclosed in the present invention comprises:

[0022] A process for preparing a fluororesin laminate, the fluororesin laminate comprising: a fluororesin layer including a first main surface and a second main surface opposite to the first main surface; and a second metal layer provided on the second main surface and composed of metal;

[0023] A step of preparing a first resin laminate, the first resin laminate comprising: a first resin layer including a third main surface and a fourth main surface opposite to the third main surface; and a first metal layer disposed on the third main surface;

[0024] A process for preparing an adhesive layer;

[0025] The step of laminating the fluororesin laminate, the adhesive layer, and the first resin laminate in this order so that the first main surface is in contact with the adhesive layer, and softening the adhesive layer by maintaining the adhesive layer at a temperature of 180° C. or less, thereby laminating the fluororesin laminate and the first resin laminate to form a first laminate;

[0026] a step of removing at least a portion of the fluororesin layer and at least a portion of the adhesive layer to form a through hole penetrating the fluororesin layer and the adhesive layer; and

[0027] forming a connecting portion between an inner wall surface of the fluororesin layer defining a portion of the through hole and an inner wall surface of the adhesive layer defining a portion of the through hole,

[0028] The fluororesin layer comprises polytetrafluoroethylene and a first inorganic filler,

[0029] The content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less,

[0030] The adhesive layer comprises a resin and a second inorganic filler,

[0031] The fluororesin content of the resin is 5% by mass or less,

[0032] The content of the second inorganic filler in the adhesive layer is 29 volume % or more and 47 volume % or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic cross-sectional view of the circuit board according to the first embodiment.

[0034] Figure 2A It is a diagram for explaining the method for manufacturing the circuit board involved in the second embodiment.

[0035] Figure 2B It is a diagram for explaining the method for manufacturing the circuit board involved in the second embodiment.

[0036] Figure 2C It is a diagram for explaining the method for manufacturing the circuit board involved in the second embodiment.

[0037] Figure 3 This is a schematic cross-sectional view of a circuit board according to the third embodiment.

[0038] Figure 4A It is a diagram for explaining the method for manufacturing a circuit board according to the third embodiment.

[0039] Figure 4B It is a diagram for explaining the method for manufacturing a circuit board according to the third embodiment.

[0040] Figure 4C It is a diagram for explaining the method for manufacturing a circuit board according to the third embodiment.

[0041] Figure 5 This is a schematic cross-sectional view of a circuit substrate according to a fourth embodiment.

[0042] Figure 6 This is a schematic cross-sectional view of a circuit substrate according to the fifth embodiment.

[0043] Fig. 7A It is a diagram for explaining the method for manufacturing a circuit substrate according to the fifth embodiment.

[0044] Figure 7B It is a diagram for explaining the method for manufacturing a circuit substrate according to the fifth embodiment.

[0045] Figure 8 It is a figure explaining a notch.

[0046] Fig. 9 It is a diagram for explaining the method of measuring the length of the notch. DETAILED DESCRIPTION

[0047] [Technical Problems to be Solved by the Present Disclosure]

[0048] In recent years, the amount of information communication has increased. For example, in devices such as IC cards and mobile phone terminals, communication in high-frequency areas such as microwaves and millimeter waves has become popular. Therefore, a printed wiring board with excellent high-frequency characteristics, such as a printed wiring board with low transmission loss in the high-frequency area, is required. As a substrate for manufacturing such a high-frequency printed wiring board, a laminated body in which a metal layer (e.g., copper foil) is laminated on a dielectric layer is generally used.

[0049] The bonding sheet with a low softening temperature can be bonded by a general press machine, and has excellent productivity. However, the inventors have found that when a through hole for a through hole is formed by laser processing, a laminate made using a bonding sheet with a low softening temperature is prone to notches.

[0050] Reference Figure 8 The notch is described. The circuit substrate 1 has an adhesive layer 12 (equivalent to a bonding sheet) with polypropylene as the main component. When a through hole penetrating the fluororesin layer 10 and the adhesive layer 12 is formed by laser processing from the fluororesin layer 10 to the first metal layer 13, a notch 25 is generated near the interface between the fluororesin layer 10 and the adhesive layer 12. The inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12 are plated to form a through hole. However, the portion of the notch 25 is difficult to be plated. Therefore, an insufficiently plated portion is generated in the through hole, and the reliability of the circuit substrate is easily reduced.

[0051] The present invention aims to provide a circuit substrate in which a fluororesin layer and an adhesive layer are bonded by stamping at low temperature. In addition, the present invention aims to provide a circuit substrate in which a through hole penetrating the fluororesin layer and the adhesive layer is formed, and the generation of a notch near the interface between the fluororesin layer and the adhesive layer is suppressed.

[0052] [Effects of the present disclosure]

[0053] According to the present disclosure, a circuit substrate can be provided in which a fluororesin layer and an adhesive layer are bonded by stamping at low temperature. In addition, the present disclosure can provide a circuit substrate in which the generation of notches near the interface between the fluororesin layer and the adhesive layer is suppressed when a through hole is formed that penetrates the fluororesin layer and the adhesive layer.

[0054] [Description of Embodiments of the Present Disclosure]

[0055] First, embodiments of the present disclosure will be listed and described.

[0056] (1) The circuit board of the present disclosure comprises:

[0057] Fluororesin layer;

[0058] a bonded layer; and

[0059] an adhesive layer for bonding the fluororesin layer to the adhered layer,

[0060] The fluororesin layer comprises polytetrafluoroethylene and a first inorganic filler,

[0061] The content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less,

[0062] The adhesive layer comprises a resin and a second inorganic filler,

[0063] The fluororesin content of the resin is 5% by mass or less,

[0064] The content of the second inorganic filler in the adhesive layer is 29 volume % or more and 47 volume % or less,

[0065] A through hole is formed that penetrates the fluororesin layer and the adhesive layer.

[0066] According to the present disclosure, a circuit substrate can be provided in which a fluororesin layer and an adhesive layer are bonded by stamping at low temperature. In addition, according to the present disclosure, a circuit substrate can be provided in which, in the case where a through hole penetrating the fluororesin layer and the adhesive layer is formed, the generation of a notch near the interface between the fluororesin layer and the adhesive layer is suppressed. In the present disclosure, "low temperature" refers to a temperature below 180°C.

[0067] (2) In the above (1), the first inorganic filler may also contain silicon dioxide. This can reduce the thermal expansion coefficient of the fluororesin layer. Here, the thermal expansion coefficient of the fluororesin layer is the linear expansion coefficient in the thickness direction of the fluororesin layer (the thermal expansion coefficient along the length of the axis perpendicular to the layer surface of the fluororesin layer).

[0068] (3) In the above (1) or (2), the second inorganic filler may contain silica. This can further suppress the occurrence of notches.

[0069] (4) In any one of the above (1) to (3), the second inorganic filler may include boron nitride. This can further suppress the occurrence of notches.

[0070] (5) In any of the above (1) to (4), at least one of the inner wall surface of the fluororesin layer defining a portion of the through hole and the inner wall surface of the adhesive layer defining a portion of the through hole may have a notch, and the length of the notch is less than 25 μm. This improves the reliability of the circuit board.

[0071] (6) In any of the above (1) to (5), the ratio A / B of the elastic modulus A of the adhesive layer at 160°C to the elastic modulus B at 20°C may be 0.08 or less. This improves the low-temperature adhesion between the fluororesin layer and the metal layer.

[0072] (7) In any one of the above (1) to (6), the resin may contain a polyolefin or a polystyrene-based elastomer. This improves the adhesion between the fluororesin layer and the metal layer at low temperatures.

[0073] (8) In any one of the above (1) to (7), the adherend layer may include a first metal layer and a first resin layer, and the first metal layer may be provided on a surface of the first resin layer facing the fluororesin layer.

[0074] Thus, a circuit can be formed in the first metal layer.

[0075] (9) In any one of the above (1) to (7), the adhered layer may include a first metal layer and a first resin layer, and the first resin layer may be provided on a surface of the first metal layer that faces the fluororesin layer. Thus, a circuit may be formed on the first metal layer.

[0076] (10) In the above (8) or (9), the fluororesin layer includes a first main surface facing the adhesive layer and a second main surface opposite to the first main surface,

[0077] The circuit board may further include a second metal layer provided on the second main surface.

[0078] Thus, a circuit can be formed in the second metal layer.

[0079] (11) In the above (10), a connection portion for electrically connecting the first metal layer and the second metal layer may be further provided.

[0080] The connection portion is formed in the through hole.

[0081] Thereby, the first metal layer and the second metal layer can be electrically connected.

[0082] (12) In the above (10) or (11), the first metal layer may be formed in a region overlapping the through hole when viewed from a direction perpendicular to the second main surface. This allows the shape of the connection portion to be precisely defined.

[0083] (13) In the above (10) or (11), the second metal layer may be formed in a region overlapping the through hole when viewed from a direction perpendicular to the first main surface. This allows the shape of the connection portion to be precisely defined.

[0084] (14) The method for manufacturing a circuit substrate disclosed herein is a method for manufacturing a circuit substrate as described in any one of (1) to (13) above,

[0085] The method further comprises the step of bonding the fluororesin layer to the adhered layer by holding a laminated body in which the fluororesin layer, the adhesive layer, and the adhered layer are laminated in this order at a temperature of 180° C. or lower to soften the adhesive layer.

[0086] According to the present disclosure, a circuit substrate can be provided in which a fluororesin layer and an adhesive layer are bonded by stamping at low temperature. In addition, according to the present disclosure, a circuit substrate can be provided in which the generation of a notch near the interface between the fluororesin layer and the adhesive layer is suppressed even when a through hole penetrating the fluororesin layer and the adhesive layer is formed.

[0087] (15) The method for manufacturing a circuit board disclosed in the present invention comprises:

[0088] A process for preparing a fluororesin laminate, the fluororesin laminate comprising: a fluororesin layer including a first main surface and a second main surface opposite to the first main surface; and a second metal layer disposed on the second main surface;

[0089] A step of preparing a first resin laminate, the first resin laminate comprising: a first resin layer including a third main surface and a fourth main surface opposite to the third main surface; and a first metal layer disposed on the third main surface;

[0090] A process for preparing an adhesive layer;

[0091] The step of laminating the fluororesin laminate, the adhesive layer, and the first resin laminate in this order so that the first main surface is in contact with the adhesive layer, and softening the adhesive layer by maintaining the adhesive layer at a temperature of 180° C. or less, thereby laminating the fluororesin laminate and the first resin laminate to form a first laminate;

[0092] a step of removing at least a portion of the fluororesin layer and at least a portion of the adhesive layer to form a through hole penetrating the fluororesin layer and the adhesive layer; and

[0093] forming a connecting portion between an inner wall surface of the fluororesin layer defining a portion of the through hole and an inner wall surface of the adhesive layer defining a portion of the through hole,

[0094] The fluororesin layer comprises polytetrafluoroethylene and a first inorganic filler,

[0095] The content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less,

[0096] The adhesive layer comprises a resin and a second inorganic filler,

[0097] The fluororesin content of the resin is 5% by mass or less,

[0098] The content of the second inorganic filler in the adhesive layer is 29 volume % or more and 47 volume % or less.

[0099] According to the present disclosure, a circuit substrate can be provided in which a fluororesin layer and an adhesive layer are bonded by stamping at low temperature. In addition, according to the present disclosure, a circuit substrate can be provided in which the generation of a notch near the interface between the fluororesin layer and the adhesive layer is suppressed even when a through hole penetrating the fluororesin layer and the adhesive layer is formed.

[0100] (16) In the above (15), the step of preparing the first resin laminate may further include a step of forming a first circuit on the first resin laminate by etching at least a portion of the first metal layer. In this way, the first circuit can be embedded in the adhesive layer.

[0101] (17) In the above (15) or (16), the step of preparing the fluororesin laminate may further include a step of forming a second circuit on the fluororesin laminate by etching at least a portion of the second metal layer. Thus, the wiring density of the circuit board can be increased by forming the second circuit.

[0102] (18) In the above (15) or (16), the step of forming the first laminate may further include a step of forming a second circuit on the fluororesin laminate by etching at least a portion of the second metal layer. Thus, the wiring density of the circuit board can be increased by forming the second circuit.

[0103] (19) In any one of the above (15) to (18), the through hole may be formed by laser processing. Thus, the through hole can be formed with high precision.

[0104] (20) In any one of the above (15) to (19), at least one of the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer may have a notch,

[0105] The length of the notch is less than 25 μm. Thus, the reliability of the circuit substrate is improved.

[0106] [Details of the embodiments of the present disclosure]

[0107] Hereinafter, the circuit substrate and the manufacturing method thereof disclosed in the present invention will be described with reference to the accompanying drawings. In the drawings disclosed in the present invention, the same reference numerals represent the same parts or equivalent parts. For the clarity and simplification of the drawings, the dimensional relationships such as length, width, thickness, depth, etc. are appropriately changed and may not represent the actual dimensional relationships.

[0108] In the present disclosure, the expression "A to B" (A and B are numerical values) means a range from an upper limit to a lower limit (A or more and B or less). When A has no unit and only B has a unit, the unit of A is the same as that of B.

[0109] In the present disclosure, when a compound is represented by a chemical formula and the atomic ratio is not limited, the compound includes compounds of all conventionally known atomic ratios and is not limited to compounds within the stoichiometric range.

[0110] In the present disclosure, when the lower limit and the upper limit of the numerical range are respectively more than one numerical value, a combination of any numerical value recorded as the lower limit and any numerical value recorded as the upper limit is disclosed. For example, when a1, b1, and c1 are recorded as the lower limit and a2, b2, and c2 are recorded as the upper limit, more than a1 and less than a2, more than a1 and less than b2, more than a1 and less than c2, more than b1 and less than a2, more than b1 and less than b2, more than b1 and less than c2, more than c1 and less than a2, more than c1 and less than b2, and more than c1 and less than c2 are disclosed.

[0111] [Embodiment 1: Circuit Board (1)]

[0112] use Figure 1 A circuit substrate and a manufacturing method thereof according to an embodiment of the present disclosure (hereinafter also referred to as “embodiment 1”) are described. The circuit substrate 1 of embodiment 1 comprises a fluororesin layer 10, an adhered layer 17, and an adhesive layer 12 for bonding the fluororesin layer 10 to the adhered layer 17. The fluororesin layer 10 comprises polytetrafluoroethylene and a first inorganic filler. The content of the first inorganic filler in the fluororesin layer 10 is greater than 50% by volume and less than 66% by volume. The adhesive layer 12 comprises a resin and a second inorganic filler. The content of the fluororesin in the resin is less than 5% by mass. The content of the second inorganic filler in the adhesive layer 12 is greater than 29% by volume and less than 47% by volume. A through hole penetrating the fluororesin layer 10 and the adhesive layer 12 is formed on the circuit substrate 1.

[0113] The circuit substrate 1 of the first embodiment is a circuit substrate in which the fluororesin layer 10 and the adhered layer 17 are bonded by the adhesive layer 12 by stamping at low temperature. In the circuit substrate 1, even when a through hole penetrating the fluororesin layer 10 and the adhesive layer 12 is formed, the generation of a notch near the interface between the fluororesin layer 10 and the adhesive layer 12 can be suppressed. Therefore, the circuit substrate 1 of the first embodiment can have excellent reliability.

[0114] In the present disclosure, the circuit substrate is not limited to a substrate in which a circuit is formed by processing a metal layer of a substrate. The circuit substrate of the present disclosure includes a laminate formed by bonding a substrate or other circuit substrate to a circuit substrate using a bonding sheet, and a laminate provided with connection holes such as through holes.

[0115] <Structure>

[0116] like Figure 1 As shown, the circuit substrate 1 of Embodiment 1 includes a fluororesin layer 10, an adhered layer 17, and an adhesive layer 12 that adheres the fluororesin layer 10 to the adhered layer 17. The fluororesin layer 10 includes a first main surface 10a facing the adhesive layer 12, and a second main surface 10b opposite to the first main surface 10a. The adhered layer 17 includes a first resin layer 16 and a first metal layer 13 provided on a portion of the surface of the first resin layer 16. The first resin layer 16 may be a laminate that includes a metal layer, a glass cloth layer, a non-woven fabric layer, or the like in addition to the resin layer. The resin layer may also contain an inorganic filler. As Figure 1 As shown, the first main surface 10 a may also be close to the adhesive layer 12 .

[0117] The 1A surface 13a of the first metal layer 13 is a surface opposite to the surface of the first metal layer 13 in contact with the first resin layer 16. The 1B surface 12a of the adhesive layer 12 is a surface opposite to the surface of the adhesive layer 12 in contact with the fluororesin layer 10. The 1A surface 13a is in contact with the 1B surface 12a. At least a portion of the first metal layer 13 is buried in the adhesive layer 12. The third main surface 16a of the first resin layer 16 is a surface opposite to the first metal layer 13. The area of ​​the third main surface 16a where the first metal layer 13 is not provided is in contact with the adhesive layer 12.

[0118] The circuit board 1 further includes a second metal layer 11 provided on the second main surface 10b of the fluororesin layer 10. The second metal layer 11 is made of metal. The fluororesin layer 10 and the second metal layer 11 may be in contact with each other. An adhesive film (not shown) may be arranged between the fluororesin layer 10 and the second metal layer 11 to bond the fluororesin layer 10 and the second metal layer 11.

[0119] The circuit board 1 further includes a connection portion 14. The connection portion 14 is made of metal and electrically connects the first metal layer 13 and the second metal layer 11. A through hole is formed on the circuit board 1, which passes through the fluororesin layer 10 and the adhesive layer 12. That is, the fluororesin layer 10 and the adhesive layer 12 have a through hole that passes through the fluororesin layer 10 and the adhesive layer 12. The connection portion 14 is formed in the through hole. More specifically, the connection portion 14 is formed on the inner wall surface of the fluororesin layer 10 that defines a portion of the through hole, and on the inner wall surface that defines a portion of the adhesive layer 12. The first metal layer 13 defines the bottom surface of the through hole, and the connection portion 14 is also formed on the bottom surface.

[0120] When the circuit substrate 1 is observed from a direction perpendicular to the second main surface 10b, the second metal layer 11 is not formed in the region overlapping the through hole. The second metal layer 11 has an opening connected to the through hole. When the circuit substrate 1 is observed from a direction perpendicular to the second main surface 10b, the first metal layer 13 is formed in the region overlapping the through hole. The first metal layer 13 is a hole bottom that blocks the through hole.

[0121] The cross-sectional area of ​​the through hole increases continuously from the first metal layer 13 toward the second metal layer 11. In the present disclosure, the cross-sectional area of ​​the through hole is a cross-sectional area when viewed in a cross section perpendicular to the direction from the first metal layer 13 toward the second metal layer 11.

[0122] <Fluororesin layer>

[0123] In Embodiment 1, the fluororesin layer contains polytetrafluoroethylene and the first inorganic filler. Polytetrafluoroethylene has a small dielectric constant and dielectric loss tangent. Therefore, the high-frequency characteristics of the circuit board using the fluororesin layer as the insulating layer are good.

[0124] In embodiment 1, the volume-based content of the first inorganic filler of the fluororesin layer is 50% by volume or more and 66% by volume or less. Thus, since the thermal expansion coefficient of the fluororesin layer is small, the dimensional stability is excellent. In addition, the electrical connection reliability of the connection portion provided on the inner wall surface of the fluororesin layer is excellent. From the viewpoint of reducing the thermal expansion coefficient, the lower limit of the content of the first inorganic filler of the fluororesin layer is 50% by volume, and it can also be 60% by volume, and it can also be 63% by volume. If the content of the first inorganic filler of the fluororesin layer is 50% by volume or more, the thermal expansion coefficient of the fluororesin layer becomes smaller, if the content is 60% by volume or more, the thermal expansion coefficient becomes smaller, and if it is 63% by volume or more, the thermal expansion coefficient becomes further smaller. The upper limit of the content of the first inorganic filler of the fluororesin layer is 66% by volume, and it can also be 65% by volume. If the content of the first inorganic filler of the fluororesin layer is 66% by volume or less, the electrical connection stability of the connection portion is excellent, and if the content is 65% by volume or less, the thermal expansion coefficient and the electrical connection stability of the connection portion are more excellent. The content of the first inorganic filler in the fluororesin layer may be 60% by volume or more and 66% by volume or less, or 63% by volume or more and 65% by volume or less.

[0125] In the present disclosure, the method for determining the volume-based content of the first inorganic filler of the fluororesin layer is as follows. The circuit substrate is cut by argon ion milling to expose a cross section of the fluororesin layer. The cross section is set as a plane perpendicular to or parallel to the stacking surface of the circuit substrate. If the cross section is a plane parallel to the stacking surface of the circuit substrate, the area of ​​the cross section tends to become larger. If the cross section is a plane perpendicular to the stacking surface, it is easy to form a cross section. Use a high-resolution scanning electron microscope (SEM) (SU8020 manufactured by Hitachi High-Technologies Corporation) to observe the cross section of the fluororesin layer at 10,000 times at a low acceleration voltage to obtain a SEM image. A rectangular measurement area of ​​8μm×12μm is set in the SEM image. In this measurement area, the area-based content (area percentage) occupied by the first inorganic filler is determined. The determination of the area percentage is performed by extracting a portion of the first inorganic filler using multi-valued image analysis processing software. For 30 different measurement areas, the area percentage of the first inorganic filler is measured, and the average value of the area percentage is calculated. Next, for a total of 40 measurement areas obtained by adding 10 new measurement areas whose area percentages have not yet been measured to the measurement areas whose area percentages have already been measured, calculate the average area percentage of the first inorganic filler. If the difference between the average area percentage before adding the 10 measurement areas and the average area percentage of the measurement areas after adding the 10 measurement areas is within 1%, the average area percentage of the measurement areas after the addition is set as the volume-based content of the first inorganic filler in the fluororesin layer. In the case where the difference is greater than 1%, 10 measurement areas whose area percentages have not yet been measured are added, and the average area percentage of the measurement areas after the addition is calculated. Repeat this operation until the difference before and after the measurement areas are added is within 1%. The average area percentage when the difference before and after the measurement areas are added is within 1% is set as the volume-based content of the first inorganic filler in the fluororesin layer.

[0126] In embodiment 1, the content rate of the mass basis of the first inorganic filler of the fluororesin layer can also be 50 mass % or more and 67 mass % or less. Thus, since the thermal expansion coefficient of the fluororesin layer decreases, the dimensional stability is excellent. In addition, the electrical connection reliability of the connection portion provided on the inner wall surface of the fluororesin layer is excellent. From the viewpoint of reducing the thermal expansion coefficient, the lower limit of the content rate of the first inorganic filler of the fluororesin layer can be 50 mass %, 60 mass %, or 63 mass %. If the content rate of the first inorganic filler of the fluororesin layer is 50 mass % or more, the thermal expansion coefficient of the fluororesin layer decreases, if the content rate is 60 mass % or more, the thermal expansion coefficient becomes smaller, and if it is 63 mass % or more, the thermal expansion coefficient further decreases. The upper limit of the content rate of the first inorganic filler of the fluororesin layer can be 67 mass % or 66 mass %. If the content rate of the first inorganic filler of the fluororesin layer is 67 mass % or less, the electrical connection stability of the connection portion is excellent, and if the content rate is 67 mass % or less, the electrical connection stability of the connection portion is more excellent. The content of the first inorganic filler in the fluororesin layer may be 50% by mass or more and 67% by mass or less, 60% by mass or more and 66% by mass or less, or 63% by mass or more and 65% by mass or less.

[0127] In the present disclosure, the method for determining the mass-based content of the first inorganic filler of the fluororesin layer is as follows. The fluororesin layer is heated in a nitrogen atmosphere using a differential thermal thermogravimetric simultaneous measurement device (TG-DSC), and the temperature of the fluororesin layer is increased from 30°C to 700°C at 20°C / min. The initial weight of the fluororesin layer and the recovered weight of the recovered material after heating are measured. The ratio of the recovered weight to the initial weight is set as the mass-based content of the first inorganic filler of the fluororesin layer.

[0128] The first inorganic filler can be a non-metallic inorganic filler, or it can include silicon dioxide. Silicon dioxide is cheap and easy to obtain. In addition, the dielectric loss tangent of silicon dioxide is smaller than the dielectric loss tangent of other inorganic fillers. Since the dielectric constant of silicon dioxide is close to the dielectric constant of fluororesin, even if the first inorganic filler contains a large amount of silicon dioxide, the dielectric constant of the first inorganic filler will not change significantly. From the viewpoint of reducing the dielectric loss tangent of the fluororesin layer, the content of silicon dioxide in the first inorganic filler can be more than 80% by mass, more than 90% by mass, or more than 92% by mass. The upper limit of the content of silicon dioxide in the first inorganic filler can also be 100% by mass. From the viewpoint of suppressing the decline of the dielectric loss tangent of the fluororesin layer, the content of silicon dioxide in the first inorganic filler can be more than 80% by mass and less than 100% by mass, more than 90% by mass and less than 100% by mass, or more than 92% by mass and less than 100% by mass.

[0129] In the present disclosure, the method for determining the mass-based content of silicon dioxide in the first inorganic filler in the fluororesin layer is as follows. First, the recovered weight of the recyclate obtained in the method for determining the mass-based content of the first inorganic filler in the fluororesin layer described above is determined. Using the recyclate, the content of silicon (Si) in the recyclate is determined by high-frequency inductively coupled plasma (ICP) analysis. Assuming that silicon dioxide is composed of SiO2, the content of silicon dioxide in the recyclate is calculated based on the content of silicon. This content is the mass-based content of silicon dioxide in the first inorganic filler in the fluororesin layer.

[0130] The silicon dioxide in the first inorganic filler may be a natural product or a synthetic product. The silicon dioxide in the first inorganic filler may be crystalline or non-crystalline. The silicon dioxide in the first inorganic filler may be silicon dioxide based on a dry method or silicon dioxide based on a wet method. From the perspective of ease of acquisition and quality, the silicon dioxide in the first inorganic filler may also be synthetic silicon dioxide based on a dry method.

[0131] The silicon dioxide in the first inorganic filler may also include spherical silicon dioxide. Thus, in the manufacturing process of the circuit substrate, the processability of the hole processing etc. becomes good. The content of the spherical silicon dioxide of silicon dioxide can be more than 80 mass % and less than 100 mass %, or more than 90 mass % and less than 100 mass %, or more than 95 mass % and less than 100 mass %. If the content of the spherical silicon dioxide of silicon dioxide is more than 80 mass % and less than 100 mass %, the processability of the circuit substrate becomes good, if it is more than 90 mass % and less than 100 mass %, the processability of the circuit substrate becomes even better, and if it is more than 95 mass % and less than 100 mass %, the processability of the circuit substrate becomes further good. In the present disclosure, spherical silicon dioxide refers to silicon dioxide with a sphericity of more than 0.80.

[0132] The average particle size of spherical silica can also be 0.2 μm or more and 7.0 μm or less. As a result, the fluororesin layer has a large elongation at break, excellent mechanical strength, and excellent processability such as cutting and perforation. From the viewpoint of mechanical strength such as elongation at break, the lower limit of the average particle size of spherical silica can be 0.2 μm, 0.5 μm, or 1.0 μm. If the average particle size of spherical silica is 0.2 μm or more, the mechanical strength is excellent, and if it is 0.5 μm or more, the mechanical strength of the fluororesin layer is further excellent, and if it is 1.0 μm or more, the mechanical strength of the fluororesin layer is further excellent. From the viewpoint of processability such as cutting and perforation, the upper limit of the average particle size of spherical silica can be 7.0 μm, 5.0 μm, or 3.0 μm. If the average particle size of the spherical silica is 7.0 μm or less, the processability of the fluororesin layer is excellent, if it is 5.0 μm or less, the processability of the fluororesin layer is further excellent, and if it is 3.0 μm or less, the processability of the fluororesin layer is further excellent. The average particle size of the spherical silica may be 0.2 μm or more and 7.0 μm or less, 0.5 μm or more and 5.0 μm or less, or 1.0 μm or more and 3.0 μm or less.

[0133] In the present disclosure, the average particle size of spherical silica is the average particle size of primary particles. The average particle size is expressed by the mode particle size of the volume particle size distribution. In the present disclosure, the method for determining the average particle size of spherical silica in the fluororesin layer is as follows. Using a differential thermal thermogravimetric simultaneous measurement device (TG-DSC), the fluororesin layer is heated under a nitrogen atmosphere, and the temperature of the fluororesin layer is increased from 30°C to 700°C at 20°C / min to obtain a recyclate. The recyclate contains silica. The recyclate is observed by SEM. 100 silicas are randomly selected, the particle size is measured, and the particle size distribution is obtained to calculate the average particle size.

[0134] The first inorganic filler may also contain titanium oxide. Since the dielectric constant of titanium oxide is large, the dielectric constant of the fluororesin layer can be adjusted by adding a small amount of titanium oxide to the first inorganic filler. The content of titanium oxide in the first inorganic filler may be 1% by mass or more, or 2% by mass or more. The upper limit of the content of titanium oxide in the first inorganic filler may be 20% by mass or 10% by mass. The content of titanium oxide in the first inorganic filler may be 1% by mass or more and 20% by mass or more and 10% by mass or less.

[0135] The method for determining the mass-based content of titanium oxide in the first inorganic filler in the fluororesin layer is as follows. First, the recovered weight of the recyclate obtained in the method for determining the mass-based content of the first inorganic filler in the fluororesin layer described above is measured. Using the recyclate, the content of titanium (Ti) in the recyclate is determined by ICP analysis. Assuming that titanium oxide is composed of TiO2, the content of titanium oxide in the recyclate is calculated based on the content of titanium. This content is the mass-based content of titanium oxide in the first inorganic filler.

[0136] The first inorganic filler may include both silicon dioxide and titanium oxide. As a result, since the dielectric constant of titanium oxide has a temperature change characteristic opposite to that of silicon dioxide, the temperature stability of the dielectric constant can be improved.

[0137] As long as the effect of the present disclosure is not impaired, the first inorganic filler can include non-metallic inorganic fillers other than silica and titanium oxide (hereinafter, also referred to as "other inorganic fillers".). Generally speaking, since the thermal expansion coefficient of the inorganic filler is small, when the first inorganic filler includes other inorganic fillers other than silica and titanium oxide, the content of silica or titanium oxide can be reduced according to the content thereof. As other inorganic fillers, for example, aluminum oxide, magnesium oxide, calcium oxide, talc, barium sulfate, boron nitride, zinc oxide, potassium titanate, glass and mica can be listed. One of these inorganic fillers can be used, or two or more can be used.

[0138] The fluororesin layer can be composed of polytetrafluoroethylene, the first inorganic filler and inevitable impurities. The fluororesin layer can also contain resins other than polytetrafluoroethylene (other fluororesins). That is, the fluororesin layer can be composed of polytetrafluoroethylene, the first inorganic filler, other fluororesins and inevitable impurities. In this case, the upper limit of the content of other fluororesins can be 10% by mass, or 5% by mass.

[0139] The fluororesin layer may contain components other than polytetrafluoroethylene and the first inorganic filler as long as the effect of the present disclosure is not impaired. In the fluororesin layer, the total of polytetrafluoroethylene, the first inorganic filler, other fluororesins and inevitable impurities, and components that can be contained as long as the effect of the present disclosure is not impaired is set to 100% to define the content of polytetrafluoroethylene and the like.

[0140] The fluororesin layer may not contain glass cloth. In a fluororesin layer not containing glass cloth, the inner wall surface is less likely to have irregularities, and the electrical connection reliability is excellent when a connection portion is formed on the inner wall surface.

[0141] The lower limit of the average thickness of the fluororesin layer may be 20 μm, 40 μm, or 60 μm. If the average thickness is less than 20 μm, the mechanical strength may become insufficient. In addition, since the influence of the dimensional error on the high-frequency characteristics of the circuit substrate becomes greater, the circuit design and the manufacture of circuit components may become difficult. The upper limit of the average thickness of the fluororesin layer may be 500 μm, 300 μm, or 150 μm. If the average thickness exceeds 500 μm, the thickness of the circuit substrate may become too large. In addition, when flexibility is required for the circuit substrate, the flexibility may be insufficient. The average thickness of the fluororesin layer may be greater than 20 μm and less than 500 μm, or greater than 40 μm and less than 300 μm, or greater than 60 μm and less than 150 μm.

[0142] In the present disclosure, "average thickness" refers to the distance between the average line of the interface close to the surface of the circuit board and the average line of the interface close to the back surface in the cross section cut along the thickness direction of the object. The "average line" is an imaginary line drawn along the interface, which is a line that makes the total area of ​​the peak divided by the interface and the imaginary line (the total area above the imaginary line) and the total area of ​​the valley (the total area below the imaginary line) equal. The average thickness of each layer described below is also defined in the same way.

[0143] In an area of ​​1m 2 In the fluororesin layer, the upper limit of the difference between the maximum and minimum values ​​of the thickness of the fluororesin layer (maximum value - minimum value) can be 10 μm, 5 μm, or 2 μm. If the difference is less than 10 μm, less than 5 μm, or less than 2 μm, circuit design and circuit component manufacturing become easy. The maximum and minimum values ​​of the thickness of the fluororesin layer are measured using an outside micrometer MDH-25MB manufactured by Mitutoyo Co., Ltd., with the terminal surface of the measuring terminal as a "plane".

[0144] <Adhesive layer>

[0145] In order to reduce the transmission loss of the substrate, it is considered that the bonding layer uses fluororesin in the same manner as the dielectric layer of the substrate. However, since the softening temperature of the fluororesin is high, a press capable of stamping at high temperatures is required. In addition, since heating and cooling take time, productivity decreases. Furthermore, the thermal shrinkage when the fluororesin is cooled to room temperature and changes from a softened state to a hardened state is large, and the dimensional stability is poor. Therefore, it is required to have an bonding layer that is mainly composed of a resin with a small dielectric loss tangent and can be bonded at low temperatures.

[0146] In embodiment 1, the adhesive layer contains a resin and a second inorganic filler. The circuit substrate of embodiment 1 includes a laminate in which the adhesive layer and the above-mentioned fluororesin layer are in contact and bonded to each other. Even in the case where the circuit substrate is formed with a through hole that penetrates the fluororesin layer and the adhesive layer, it is also possible to suppress the generation of a notch near the interface between the fluororesin layer and the adhesive layer. In addition, the adhesive layer has excellent adhesion to both the fluororesin layer and the adhered layer. Therefore, the reliability of the circuit substrate of embodiment 1 is improved. The content of the fluororesin in the resin of the adhesive layer is less than 5% by mass. In the resin of the adhesive layer, the content of the fluororesin with a high softening temperature is reduced. Therefore, the adhesive layer can bond the fluororesin layer to the adhered layer at low temperatures.

[0147] The resin may contain polyolefin or polystyrene elastomer. This reduces the transmission loss of the circuit due to a small dielectric loss tangent, and enables bonding at a temperature of 180° C. or less due to a low softening temperature.

[0148] The polyolefin is, for example, polyethylene or polypropylene. The polyolefin may also be an acid-modified polyolefin. This is because the acid-modified polyolefin has a strong adhesion to the fluororesin layer and the metal layer. The acid-modified polyolefin is a polyolefin containing a carboxyl group.

[0149] From the viewpoint of lowering the softening temperature of the adhesive layer and obtaining good mechanical strength, the lower limit of the content of the polyolefin of the resin can be 70 mass %, 80 mass %, or 90 mass %. The upper limit of the content of the polyolefin of the resin can be 100 mass %, or 95 mass %. The content of the polyolefin of the resin can be 70 mass % or more and 100 mass %, 80 mass % or more and 97 mass % or less, or 90 mass % or more and 95 mass %.

[0150] From the viewpoint of lowering the softening temperature of the adhesive layer and obtaining good mechanical strength, the lower limit of the content of the acid-modified polyolefin in the resin may be 70% by mass, 80% by mass, or 90% by mass. The upper limit of the content of the acid-modified polyolefin in the resin may be 100% by mass or 95% by mass. The content of the acid-modified polyolefin in the resin may be 70% by mass or more and 100% by mass or less, 80% by mass or more and 97% by mass or less, or 90% by mass or more and 95% by mass or less.

[0151] Examples of the polystyrene elastomer include styrene-ethylene-butylene-styrene block copolymer (SEBS), styrene-ethylene-propylene-styrene copolymer (SEPS), and styrene-ethylene-ethylene-propylene-styrene block copolymer (SEEPS).

[0152] From the viewpoint of lowering the softening temperature of the adhesive layer and obtaining good mechanical strength, the lower limit of the content of the polystyrene elastomer in the resin may be 50% by mass, 55% by mass, or 60% by mass. The upper limit of the content of the polystyrene elastomer in the resin may be 100% by mass, or 80% by mass. The content of the polystyrene elastomer in the resin may be 50% by mass or more and 100% by mass or less, 55% by mass or more and 90% by mass or less, or 60% by mass or more and 80% by mass or less.

[0153] The adhesive layer may contain resins other than polyolefin and polystyrene elastomer (other resins). For example, other resins include polyphenylene ether.

[0154] In the adhesive layer, when the resin is a polyolefin, the upper limit of the content of other resins may be 30% by mass, 20% by mass, or 10% by mass. In the adhesive layer, when the resin is a polystyrene elastomer, the upper limit of the content of other resins may be 50% by mass, 45% by mass, or 40% by mass.

[0155] In embodiment 1, the content of the volume basis of the second inorganic filler of the adhesive layer is 29 volume % or more and 47 volume % or less. Thus, the length of the notch can be made smaller than 25 μm. Since the softening temperature of the adhesive layer is low, the large thermal expansion coefficient of the adhesive layer will not be a problem. Therefore, in order to reduce the thermal expansion coefficient of the adhesive layer, the adhesive layer does not need to include the second inorganic filler. From the viewpoint of making the length of the notch smaller, the lower limit of the content of the second inorganic filler of the adhesive layer can be 29 volume %, can also be 33 volume %, can also be 38 volume %. From the viewpoint of maintaining strong bonding strength, the upper limit of the content of the second inorganic filler of the adhesive layer is 47 volume %, can also be 43 volume %, can also be 40 volume %. The content of the second inorganic filler of the adhesive layer is 29 volume % or more and 47 volume %, can also be 33 volume % or more and 43 volume %, can also be 38 volume % or more and 40 volume %.

[0156] In the present disclosure, the method for determining the volume-based content of the second inorganic filler in the adhesive layer is as follows. The circuit substrate is cut by argon ion milling to expose the cross section of the adhesive layer. The cross section is set to a plane perpendicular to the laminated surface of the circuit substrate or a perpendicular plane. If the cross section is a plane parallel to the laminated surface of the circuit substrate, the area of ​​the cross section tends to become larger. If the cross section is a plane perpendicular to the laminated surface, it is easy to form a cross section. Use a high-resolution scanning electron microscope (SEM) (SU8020 manufactured by Hitachi High-Technologies Corporation) to observe the cross section of the adhesive layer at 10,000 times at a low acceleration voltage to obtain a SEM image. A rectangular measurement area of ​​5μm×12μm is set in the SEM image. In the measurement area, the area-based content (area percentage) occupied by the second inorganic filler is measured. The area percentage is determined by extracting the portion of the second inorganic filler through multi-valued image analysis processing software. For 30 different measurement areas, the area percentage of the second inorganic filler is measured, and the average value of the area percentage is calculated. Next, for a total of 40 measurement areas obtained by adding 10 new measurement areas whose area percentages have not yet been measured to the measurement areas whose area percentages have already been measured, calculate the average area percentage of the second inorganic filler. If the difference between the average area percentage before adding 10 measurement areas and the average area percentage of the measurement areas after adding 10 measurement areas is within 1%, the average area percentage of the measurement areas after adding is set as the volume-based content of the second inorganic filler in the adhesive layer. In the case where the difference is greater than 1%, add 10 measurement areas whose area percentages have not yet been measured, and calculate the average area percentage of the measurement areas after adding. Repeat this operation until the difference before and after the measurement areas are added is within 1%. The average area percentage when the difference before and after the measurement areas are added is within 1% is set as the volume-based content of the second inorganic filler in the adhesive layer.

[0157] In embodiment 1, the content rate of the mass basis of the second inorganic filler of the adhesive layer can also be 40 mass % or more and 70 mass % or less. Thus, the length of the notch can be smaller than 25 μm. The lower limit of the content rate of the second inorganic filler of the adhesive layer can be 40 mass %, 50 mass %, or 55 mass %. The upper limit of the content rate of the second inorganic filler of the adhesive layer can be 70 mass %, 67 mass %, or 63 mass %. The content rate of the second inorganic filler of the adhesive layer can be 40 mass % or more and 70 mass %, 50 mass % or more and 67 mass %, or 55 mass % or more and 63 mass %.

[0158] In the present disclosure, the method for determining the mass-based content of the second inorganic filler in the adhesive layer is as follows. The adhesive layer is heated in a nitrogen atmosphere using a differential thermal thermogravimetric simultaneous measurement device (TG-DSC), and the temperature of the adhesive layer is increased from 30°C to 700°C at 20°C / min. The initial weight of the adhesive layer and the recovered weight of the recyclate after heating are measured. The ratio of the recovered weight to the initial weight is set as the mass-based content of the second inorganic filler in the adhesive layer.

[0159] When the mass-based content of the first inorganic filler of the fluororesin layer is X (mass %) and the mass-based content of the second inorganic filler of the adhesive layer is Y (mass %), the absolute value Z of the difference between X and Y may be 0 or more and 17 or less, further 0 or more and 10 or less, and further 0 or more and 7 or less. Thus, the length of the notch can be further reduced.

[0160] The second inorganic filler may be a non-metallic inorganic filler, or may contain silicon dioxide. The specific gravity of silicon dioxide is relatively small. The surface of silicon dioxide is easily treated by a silane coupling agent, for example. Therefore, silicon dioxide is easily mixed with the resin of the adhesive layer. Silicon dioxide is cheap and easily available. The content of silicon dioxide in the second inorganic filler may be 50% by mass or more and 100% by mass or less, 70% by mass or more and 100% by mass or less, or 90% by mass or more and 100% by mass or less.

[0161] In the present disclosure, the method for determining the mass-based content of the second inorganic filler in the adhesive layer is as follows. First, the recovered weight of the recyclate obtained in the method for determining the mass-based content of the second inorganic filler in the adhesive layer described above is measured. Using the recyclate, the content of silicon (Si) in the recyclate is measured by ICP analysis. Assuming that silicon dioxide is a composition of SiO2, the content of silicon dioxide in the recyclate is calculated based on the content of silicon. The content is the mass-based content of the second inorganic filler in the adhesive layer.

[0162] The second inorganic filler may also include boron nitride. Since the dielectric constant of boron nitride is low, even if the second inorganic filler contains a large amount of boron nitride, the dielectric constant of the adhesive layer will not change significantly. In addition, since the thermal conductivity of boron nitride is high, the heat dissipation of the circuit substrate can be improved by containing boron nitride through the second inorganic filler. From the viewpoint of improving thermal conductivity, the content of boron nitride of the second inorganic filler can be more than 20 mass %, can be more than 40 mass %, and can also be more than 60 mass %. The upper limit of the content of boron nitride of the second inorganic filler can also be 100 mass %. The content of boron nitride of the second inorganic filler can be more than 20 mass % and less than 100 mass %, can also be more than 40 mass % and less than 100 mass %, and can also be more than 60 mass % and less than 100 mass %.

[0163] In the present disclosure, the method for determining the mass-based content of the second inorganic filler boron nitride in the adhesive layer is as follows. First, the recovered weight of the recyclate obtained in the method for determining the mass-based content of the second inorganic filler in the adhesive layer described above is measured. Using the recyclate, the boron content in the recyclate is determined by ICP analysis. Assuming that the boron nitride is composed of BN, the content of the boron nitride in the recyclate is calculated based on the boron content. The content is the mass-based content of the boron nitride of the second inorganic filler in the adhesive layer.

[0164] The second inorganic filler can contain both silicon dioxide and boron nitride. Thus, the generation of the notch can be suppressed, and the heat dissipation of the circuit substrate can be improved. In addition, even if the second inorganic filler contains a large amount of silicon dioxide and boron nitride, the dielectric constant of the adhesive layer will not change significantly.

[0165] As long as the effects of the present disclosure are not impaired, the second inorganic filler may include a non-metallic inorganic filler other than silicon dioxide and boron nitride (hereinafter, also referred to as "other inorganic fillers"). Examples of other inorganic fillers include titanium nitride, aluminum oxide, magnesium oxide, calcium oxide, talc, barium sulfate, boron nitride, zinc oxide, potassium titanate, glass, and mica. One of these other inorganic fillers may be used, or two or more may be used.

[0166] The adhesive layer can be composed of a resin, a second inorganic filler and inevitable impurities. In addition, as long as the effect of the present disclosure is not impaired, the adhesive layer can contain components other than the resin and the second inorganic filler. Components other than the resin and the second inorganic filler can be listed, for example, as flame retardants, flame retardant aids, pigments, antioxidants, reflection imparting agents, masking agents, lubricants, processing stabilizers, plasticizers and foaming agents. The adhesive layer can contain one of these components, or it can contain two or more components. The upper limit of the content of the components of the adhesive layer can be 25% by mass, or it can be 10% by mass.

[0167] The ratio A / B of the elastic modulus A of the adhesive layer at 160°C relative to the elastic modulus B at 20°C can also be 0.08 or less. Thus, even if it is stamped at a temperature below 180°C, the adhesive layer can be filled between the circuits of the metal layer. In addition, the adhesive layer is in close contact with the metal layer, and the bonding strength between the adhesive layer and the metal layer is improved. From the viewpoint of ensuring adhesion, the upper limit of the ratio A / B can be 0.08, 0.05, or 0.02. The lower limit of the ratio A / B can be 0.0001, 0.0005, or 0.001. The ratio A / B can be more than 0.0001 and less than 0.08, more than 0.0005 and less than 0.05, or more than 0.001 and less than 0.02.

[0168] In the present disclosure, the elastic modulus B of the adhesive layer at 20°C and the elastic modulus A at 160°C are measured as follows. A dynamic viscosity measurement (DMS) device is used to apply vibration of a frequency of 1 Hz to the bonding sheet constituting the adhesive layer while heating the bonding sheet, and the temperature of the bonding sheet is increased from 15°C to 170°C at 10°C / min, and the elastic modulus at 20°C and 160°C is measured.

[0169] The glass transition temperature of the adhesive layer may also be 160°C or less. Thus, the adhesion is improved when the fluororesin layer and the metal layer are pressed and bonded at a temperature of 180°C or less. The upper limit of the glass transition temperature of the adhesive layer may be 160°C, 150°C, 120°C, or 100°C. If the glass transition temperature of the adhesive layer is 150°C or less, the adhesion is further improved, if it is 120°C or less, the adhesion is further improved, and if it is 100°C or less, the adhesion is further improved. The lower limit of the glass transition temperature of the adhesive layer may also be 10°C. If the glass transition temperature of the adhesive layer is 10°C or more, the heat resistance is improved. Therefore, in the reflow soldering or high-temperature reliability evaluation of the circuit substrate, the possibility of expansion of the adhesive layer or the possibility of peeling of the adhesive layer is reduced. The glass transition temperature of the adhesive layer may be 30° C. to 160° C., 30° C. to 150° C., or 30° C. to 120° C. When the adhesive layer has a plurality of glass transition temperatures, the highest glass transition temperature among the glass transition temperatures caused by resins having a volume ratio of 10% or more relative to the total volume of all resins is set as the glass transition temperature of the adhesive layer.

[0170] In the present disclosure, the method for measuring the glass transition temperature of the adhesive layer is as follows. The glass transition temperature of the adhesive layer is measured using a dynamic viscosity measurement (DMS) device. While applying a vibration of a frequency of 1 Hz to the joint constituting the adhesive layer, the bonding sheet is heated, and the temperature of the bonding sheet is increased from 15°C to 170°C at 10°C / min. Within this temperature range, the complex elastic modulus of the bonding sheet is measured, the phase angle is set to δ, and the temperature at which tanδ reaches a peak value is regarded as the glass transition temperature.

[0171] From the viewpoint of adhesion, the lower limit of the average thickness of the adhesive layer may be 5 μm, 20 μm, or 30 μm. From the viewpoint of finishing the laminate to be thinner, the upper limit of the average thickness of the adhesive layer may be 100 μm, 70 μm, or 50 μm. The average thickness of the adhesive layer may be 5 μm or more and 100 μm or less, 20 μm or more and 70 μm or less, or 30 μm or more and 50 μm or less.

[0172] From the viewpoint of filling between circuits, the average thickness of the adhesive layer may be greater than the thickness of the circuit. The average thickness of the adhesive layer may be greater than the thickness of the circuit by 10 μm or greater, or greater than the thickness of the circuit by 20 μm or greater.

[0173] According to Embodiment 1, even when a through hole penetrating the fluororesin layer 10 and the adhesive layer 12 is formed, the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer can suppress the generation of a notch near the interface between the fluororesin layer 10 and the adhesive layer 12. Even when a notch is generated in the fluororesin layer, the length of the notch can be made very small. In the circuit substrate of Embodiment 1, at least one of the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer has a notch. The length of the notch can be less than 25 μm, less than 20 μm, or less than 15 μm. In the circuit substrate of Embodiment 1, the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer may not have a notch.

[0174] use Fig. 9 The method for measuring the length of the notch in the present disclosure is described below. First, the circuit substrate 1 is cut along a plane including the central axis L1 of the through hole to expose a cross section of the laminate of the fluororesin layer 10 and the adhesive layer 12. Fig. 9 In FIG. 1 , the central axis L1 corresponds to a line connecting the center (geometric center) of the opening of the through hole in the second main surface 10 b of the fluororesin layer 10 and the center (geometric center) of the opening of the through hole in the first B surface 12 a of the adhesive layer 12 .

[0175] In the following, a method for measuring the length of the notch in this cross section is described. The interface between the fluororesin layer 10 and the adhesive layer 12 is defined as interface P1. A straight line located between interface P1 and the fluororesin layer 10, parallel to interface P1, and 10 μm away from interface P1 is defined as straight line P1F. A straight line located between interface P1 and the adhesive layer 12, parallel to interface P1, and 10 μm away from interface P1 is defined as straight line P1B. Determine the notch in the area between interface P1 and straight line P1F, or the area between interface P1 and straight line P1F. Fig. 9 In the embodiment, there is a notch 25 in the interface P1 and in the region between the interface P1 and the straight line P1F. When the interface has projections and depressions, the interface is defined by its average line. The “average line” refers to an imaginary line drawn along the interface on the cross section, and is a line that makes the total area of ​​the peaks divided by the interface and the imaginary line (the total area above the imaginary line) and the total area of ​​the valleys (the total area below the imaginary line) equal.

[0176] In the region between the straight lines P1F and P1B of the cross section, the point S1 closest to the central axis L1 of the inner wall surface 27 is determined. Then, the end S2 of the notch at the position farthest from the central axis L1 is determined. The straight line perpendicular to the interface P1 and passing through the point S1 is the straight line L2. The straight line parallel to L2 and passing through the end S2 of the notch is the straight line L3. The distance L between the straight lines L2 and L3 is measured. The distance L is the length of the notch.

[0177] <Adhesion Layer>

[0178] In the first embodiment, the adherend layer 17 may include the first resin layer 16 and the first metal layer 13 provided on a part of the surface of the first resin layer 16. Figure 1 In the embodiment, the bonded layer 17 includes a first metal layer 13 and a first resin layer 16. The first metal layer 13 is made of metal. The first metal layer 13 is arranged closer to the first main surface 10a of the fluororesin layer 10 than the first resin layer 16. The positional relationship between the first resin layer 16 and the first metal layer 13 may also be reversed. Specifically, the first resin layer 16 may also be arranged closer to the first main surface 10a than the first metal layer 13.

[0179] <First Metal Layer>

[0180] In Embodiment 1, the first metal layer 13 forms a circuit. In the present disclosure, the circuit includes an antenna.

[0181] The first metal layer may also contain copper. Copper has low resistance and low transmission loss. The copper content of the first metal layer may be 90% by mass or more and 100% by mass or less, 95% by mass or more and 100% by mass or less, or 99% by mass or more and 100% by mass or less. The first metal layer may also be a layer composed of copper and unavoidable impurities.

[0182] The first metal layer may contain a metal other than copper. Examples of the metal other than copper include silver, nickel, cobalt, zinc, and chromium. One of these metals may be used, or two or more may be used.

[0183] From the viewpoint of reducing resistance, the average thickness of the first metal layer may be 1 μm or more, 5 μm or more, or 10 μm or more. From the viewpoint of ease of manufacture, the upper limit of the average thickness of the first metal layer may be 100 μm, 70 μm, or 50 μm. The average thickness of the first metal layer may be 1 μm or more and 100 μm or less, 5 μm or more and 70 μm or less, or 10 μm or more and 50 μm or less.

[0184] The upper limit of the maximum height roughness Rz of the surface of the first metal layer opposite to the first resin layer can be 2 μm or 1 μm. If the maximum height roughness Rz is less than 2 μm, the unevenness of the part where the high-frequency signal is concentrated due to the skin effect is small, so the current flows in a straight line easily. Therefore, the transmission loss can be suppressed and the high-frequency characteristics of the circuit substrate can be further improved. "Maximum height roughness Rz" refers to the maximum height roughness measured based on JIS-B-0601 (1982). Specifically, the maximum height roughness Rz is measured using a laser microscope VK-X200 manufactured by Keyence Corporation.

[0185] <First Resin Layer>

[0186] In embodiment 1, the first resin layer 16 may also include epoxy resin and glass cloth. Thus, the circuit substrate can be manufactured at a low cost. The dielectric loss tangent of the first resin layer 16 may be less than 0.01, less than 0.005, or less than 0.002. Thus, the transmission loss of the first metal layer is reduced, and excellent high-frequency characteristics can be obtained. The first resin layer 16 may also include fluororesin and inorganic filler. Thus, the transmission loss of the first metal layer is reduced, and excellent high-frequency characteristics can be obtained.

[0187] <Second Metal Layer>

[0188] In Embodiment 1, the second metal layer 11 forms a circuit. In the present disclosure, the circuit includes an antenna.

[0189] The second metal layer 11 may also contain copper. Copper has low resistance and small transmission loss. The copper content of the second metal layer 11 may be 90% by mass or more and 100% by mass or less, 95% by mass or more and 100% by mass or less, or 99% by mass or more and 100% by mass or less. The second metal layer may also be a layer composed of copper and inevitable impurities.

[0190] The second metal layer 11 may include a metal other than copper. Examples of the metal other than copper include silver, nickel, cobalt, zinc, and chromium. One of these metals may be used, or two or more of them may be used.

[0191] From the viewpoint of reducing resistance, the average thickness of the second metal layer 11 may be 1 μm or more, 5 μm or more, or 10 μm or more. From the viewpoint of ease of manufacture, the upper limit of the average thickness of the second metal layer 11 may be 100 μm, 70 μm, or 50 μm. The average thickness of the second metal layer 11 may be 1 μm or more and 100 μm or less, 5 μm or more and 70 μm or less, or 10 μm or more and 50 μm or less.

[0192] <Connection>

[0193] In the first embodiment, the connection portion 14 is formed as a through hole. Figure 1 In the embodiment, the connection portion 14 is formed on the end surface of the second metal layer 11 defining a portion of the through hole and the through hole vicinity area of ​​the outer side surface of the second metal layer 11, the inner wall surface of the fluororesin layer 10 and the adhesive layer 12, and the surface (1A surface 13a) near the adhesive layer of the first metal layer 13 defining a portion of the through hole. The formation position of the connection portion 14 is not limited to Figure 1 The connection portion 14 only needs to electrically connect the first metal layer 13 and the second metal layer 11. For example, the connection portion 14 only needs to be formed in the through hole. More specifically, the connection portion 14 only needs to be formed on the inner wall surface of the fluororesin layer 10 and the adhesive layer 12, the connection portion 14 near the fluororesin layer 10 only needs to be in contact with at least a portion of the second metal layer 11, and the connection portion 14 near the adhesive layer 12 only needs to be in contact with at least a portion of the first metal layer 13.

[0194] The connection portion may also contain copper, whereby the connection portion has high electrical conductivity and transmission loss can be reduced.

[0195] The connection portion may include a metal other than copper. Examples of metals other than copper include silver, nickel, cobalt, zinc, and chromium. One of these metals may be used, or two or more may be used.

[0196] From the viewpoint of improving electrical reliability, the average thickness of the connecting portion may be 1 μm or more, 5 μm or more, or 10 μm or more. From the viewpoint of ease of manufacture, the upper limit of the average thickness of the connecting portion may be 100 μm, 50 μm, or 30 μm. The average thickness of the connecting portion may be 1 μm or more and 100 μm or less, 5 μm or more and 50 μm or less, or 10 μm or more and 30 μm or less.

[0197] exist Figure 1 In the embodiment, the cross-sectional area of ​​the through hole increases continuously from the first metal layer 13 toward the second metal layer 11. The change in the cross-sectional area of ​​the through hole is not limited thereto. The cross-sectional area of ​​the through hole may be constant or may decrease continuously from the first metal layer 13 toward the second metal layer 11.

[0198] <Adhesive film>

[0199] The circuit board of the embodiment may include an adhesive film disposed between the fluororesin layer and the second metal layer. The adhesive film may improve the adhesive force between the fluororesin layer and the second metal layer.

[0200] The adhesive film may contain a fluororesin. Examples of the resin include perfluoroalkoxyalkane (PFA) and perfluoroethylene-propylene copolymer (FEP).

[0201] The average thickness of the adhesive film may be 3 μm, or may be 2 μm or less so as not to hinder the function of the fluororesin layer.

[0202] <Method for Manufacturing Circuit Board>

[0203] The method for manufacturing a circuit board of the first embodiment includes a step of bonding the fluororesin layer to the adhered layer by keeping a laminated body in which a fluororesin layer, an adhesive layer, and an adhered layer are sequentially laminated at a temperature of 180° C. or less to soften the adhesive layer. Thus, even when a through hole penetrating the fluororesin layer and the adhesive layer is formed, the generation of a notch near the interface between the fluororesin layer and the adhesive layer can be suppressed.

[0204] [Embodiment 2: Method for manufacturing a circuit board (1)]

[0205] use Figure 1 , Figure 2A , Figure 2B and Figure 2C A method for manufacturing a circuit board according to one embodiment of the present disclosure (hereinafter, also referred to as “Embodiment 2”) will be described.

[0206] The method for manufacturing the circuit board 1 according to the second embodiment includes:

[0207] A process for preparing a fluororesin laminate 20 (hereinafter also referred to as a "first process"), wherein the fluororesin laminate 20 comprises: a fluororesin layer 10 comprising a first principal surface 10a and a second principal surface 10b opposite to the first principal surface 10a; and a second metal layer 11 disposed on the second principal surface 10b (see Figure 2A );

[0208] A step of preparing a first resin laminate 22 (hereinafter also referred to as a "second step"), wherein the first resin laminate 22 includes: a first resin layer 16 including a third main surface 16a and a fourth main surface 16b opposite to the third main surface 16a; and a first metal layer 13 disposed on the third main surface 16a (refer to Figure 2A );

[0209] The step of preparing the adhesive layer 12 (hereinafter, also referred to as the "third step") (see Figure 2A );

[0210] A step of laminating the fluororesin laminate 20, the adhesive layer 12, and the first resin laminate 22 in order so that the first main surface 10a is in contact with the adhesive layer 12, and softening the adhesive layer 12 by maintaining the adhesive layer 12 at a temperature of 180°C or less, thereby laminating the fluororesin laminate 20 and the first resin laminate 22 to obtain a first laminate 24 (hereinafter also referred to as the "fourth step"). (See Figure 2B );

[0211] A step of removing at least a portion of the fluororesin layer 10 and at least a portion of the adhesive layer 12 to form a through hole penetrating the fluororesin layer 10 and the adhesive layer 12 (hereinafter also referred to as a “fifth step”) (see Figure 2C );as well as

[0212] A step of forming connecting portion 14 on the inner wall surface of fluororesin laminate 20 defining a portion of the through hole and the inner wall surface of adhesive layer 12 defining a portion of the through hole to obtain circuit board 1 (hereinafter also referred to as "sixth step"). (See Figure 1 ),

[0213] The fluororesin layer 10 includes polytetrafluoroethylene and a first inorganic filler.

[0214] The content of the first inorganic filler in the fluororesin layer 10 is 50% by volume or more and 66% by volume or less.

[0215] The adhesive layer 12 contains a resin and a second inorganic filler.

[0216] The fluororesin content of the resin is 5% by mass or less,

[0217] The content of the second inorganic filler in the adhesive layer 12 is 29% by volume or more and 47% by volume or less.

[0218] The fluororesin layer 10, the adhesive layer 12, the first metal layer 13, the second metal layer 11, the first resin layer 16 and the connecting portion 14 in the second embodiment can be respectively set to be the same as those in the first embodiment. The first step, the second step, the third step, the fourth step, the fifth step and the sixth step are described below. The order of the first step, the second step and the third step may not be in this order, and any one of these steps may be performed first. The first step, the second step and the third step may also be performed simultaneously. After the first step, the second step and the third step, the fourth step, the fifth step and the sixth step are performed in sequence.

[0219] <First step>

[0220] In the first step, a fluororesin laminate 20 is prepared, the fluororesin laminate 20 including: a fluororesin layer 10 including a first main surface 10a and a second main surface 10b opposite to the first main surface 10a; and a second metal layer 11 provided on the second main surface 10b. As a method for providing the second metal layer 11 on the second main surface 10b, for example, a method of thermocompression bonding the fluororesin layer 10 and the second metal layer 11 by high-temperature stamping, a method of bonding the fluororesin layer 10 and the second metal layer 11 by placing an adhesive film between the fluororesin layer 10 and the second metal layer 11, a method of vapor-depositing a metal constituting the second metal layer 11 on the fluororesin layer 10, and a method of plating a metal constituting the second metal layer 11 on the fluororesin layer 10.

[0221] The first step (step of preparing the fluororesin laminate) may further include a step of forming a second circuit on the fluororesin laminate 20 by etching at least a portion of the second metal layer 11. As a method of etching at least a portion of the second metal layer 11, for example, a well-known etching method such as a wet etching method in which the laminate is immersed in a chemical solution containing an acid or an alkali after forming a resist pattern and a dry etching method using an ion beam can be cited.

[0222] <Second step>

[0223] In the second step, a first resin laminate 22 is prepared. The first resin laminate 22 includes a first resin layer 16 including a third main surface 16a and a fourth main surface 16b opposite to the third main surface 16a, and a first metal layer 13 provided on the third main surface 16a.

[0224] As a method for setting the first metal layer 13 on a main surface of the first resin layer 16, for example, there can be listed a method of hot pressing the first resin layer 16 and the first metal layer 13 by high-temperature stamping, a method of bonding the first resin layer 16 and the first metal layer 13 by arranging an adhesive film between the first resin layer 16 and the first metal layer 13, a method of vapor-depositing the metal constituting the first metal layer 13 on the first resin layer 16, and a method of plating the metal constituting the first metal layer 13 on the first resin layer 16.

[0225] The second step (the step of preparing the first resin laminate) may further include a step of forming a first circuit on the first resin laminate 22 by etching at least a portion of the first metal layer 13. As a method for etching at least a portion of the first metal layer 13, for example, a well-known etching method such as a wet etching method in which the laminate is immersed in a chemical solution containing an acid or an alkali after forming a resist pattern, and a dry etching method using an ion beam can be cited.

[0226] <Third step>

[0227] In the third step, the adhesive layer 12 is prepared.

[0228] <Fourth step>

[0229] In the fourth step, the fluororesin laminate 20, the adhesive layer 12, and the first resin laminate 22 are sequentially laminated so that the first main surface 10a is in contact with the adhesive layer 12, and the adhesive layer 12 is softened by maintaining the temperature of 180°C or less, thereby bonding the fluororesin laminate 20 and the first resin laminate 22 to obtain the first laminate 24. In the second embodiment, the first metal layer 13 is arranged to be in contact with the adhesive layer 12 during lamination.

[0230] The temperature at which the adhesive layer is maintained may be 140° C. to 180° C., or 160° C. to 180° C. The adhesive layer may be heated while applying pressure to the laminate of the fluororesin laminate 20, the adhesive layer 12, and the first resin laminate 22. The pressure may be 0.5 MPa to 8 MPa, or 1 MPa to 6 MPa, or 3 MPa to 5 MPa. The adhesive layer is maintained at the above temperature, and the time for applying the above pressure to the laminate may be 20 minutes to 120 minutes.

[0231] The fourth step (step of forming the first laminate) may further include a step of forming a second circuit on the fluororesin laminate 20 by etching at least a portion of the second metal layer 11. As a method of etching at least a portion of the second metal layer 11, for example, a wet etching method in which the laminate is immersed in a liquid containing an acid or an alkali after forming a resist pattern, and a dry etching method using an ion beam, and other known etching methods can be cited. The second circuit may also be formed in the first step or the fourth step.

[0232] <Fifth Step>

[0233] In the fifth step, at least a portion of the fluororesin layer 10 and at least a portion of the adhesive layer 12 are removed to form a through hole penetrating the fluororesin layer 10 and the adhesive layer 12 .

[0234] First, a dry film is pasted on the second metal layer 11 and exposed to light to etch the second metal layer 11. Thereafter, the dry film is peeled off to form an opening in the second metal layer 11. The area other than the opening of the second metal layer 11 is used as a mask (shielding layer), and the fluororesin layer 10 and the adhesive layer 12 are laser processed through the opening. Thus, at least a portion of the fluororesin layer 10 and at least a portion of the adhesive layer 12 are removed to form an opening in the second metal layer 11 and a through hole that penetrates the fluororesin layer 10 and the adhesive layer 12. The second metal layer 11 can also be used as a laser shielding layer. If the second metal layer 11 is used as a laser shielding layer, the shape of the through hole can be controlled.

[0235] CO2 laser can also be used for laser processing. If CO2 laser is used, it is easy to use the second metal layer 11 as a laser shielding layer.

[0236] exist Figure 2C In the embodiment, the through hole does not penetrate the first metal layer 13 but is a blind hole.

[0237] The first metal layer 13 may be provided on the third main surface 16a of the first resin layer 16. In this way, since the distance between the first metal layer 13 and the second metal layer 11 is small, the wiring can be arranged at a high density. In this case, the circuit formed in the first metal layer 13 is embedded in the adhesive layer 12.

[0238] In circuit substrates that effectively utilize the high functional characteristics of the fluororesin layer, such as circuit substrates formed with high-frequency antennas, the fluororesin layer is mostly arranged near the surface. Therefore, the method of first making a general circuit substrate and then forming a high-functional fluororesin layer on its surface is reasonable in terms of ease of circuit design and manufacturing cost. The opening of the blind hole is arranged on the second main surface 10b of the fluororesin layer 10, and the first metal layer 13 arranged on the third main surface 16a of the first resin layer 16 is the bottom of the blind hole. The circuit substrate is easily applicable to this reasonable method. However, in the circuit substrate where the first metal layer 13 is the bottom of the blind hole, when the through hole is formed by laser processing, the laser is reflected by the first metal layer 13. Therefore, the length of the notch near the interface of the fluororesin layer 10 and the adhesive layer 12 is larger than that of the circuit substrate without laser reflection. According to the present disclosure, even if the first metal layer is the bottom of the blind hole, the length of the notch can be suppressed. Therefore, the present disclosure is particularly effective for the circuit substrate where the first metal layer is the bottom of the blind hole.

[0239] After the through-holes are formed, the inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12 may be subjected to a pretreatment step to clean the inner wall surfaces. Examples of the surface treatment include potassium permanganate treatment, alkali treatment, and plasma treatment.

[0240] The alkali treatment is a treatment for etching the surface layers of the inner wall surfaces of the fluororesin layer 10 and the adhesive layer 12 by immersing the first laminate 24 in a strong alkali solution such as potassium hydroxide.

[0241] Plasma treatment is a treatment for etching the surface layer of the inner wall surface by bringing plasma into contact with the inner wall surface of the fluororesin layer 10 and the adhesive layer 12. In atmospheric pressure plasma treatment, which is an example of plasma treatment, plasma gas such as oxygen, nitrogen, hydrogen, argon, ammonia, etc. is sprayed onto the inner wall surface. The entire surface of the first stack 24 can also be subjected to plasma treatment by placing the first stack 24 in a plasma gas atmosphere. In plasma treatment, plasma containing an inert gas of a compound having a hydrophilic group can also be used.

[0242] <Sixth step>

[0243] In the sixth step, the connection portion 14 is formed on the inner wall surface of the fluororesin laminate 20 and the adhesive layer 12 to obtain the circuit board 1.

[0244] In forming the connection portion 14, first, an electroless plating layer is formed by electroless plating on the end surface of the second metal layer 11 defining a portion of the through hole, the area near the opening (through hole) of the outer side surface of the second metal layer 11, the inner wall surface of the fluororesin layer 10, the inner wall surface of the adhesive layer 12, and the surface near the adhesive layer of the first metal layer 13 defining a portion of the through hole (1A surface 13a). Next, a plating layer is formed on the electroless plating layer by electrolytic plating. This plating layer is the connection portion 14.

[0245] [Embodiment 3: Circuit Board (2)]

[0246] use Figure 3 , Figure 4A , Figure 4B and Figure 4C A circuit substrate and a method for manufacturing the circuit substrate according to an embodiment of the present disclosure (hereinafter also referred to as “embodiment 3”) will be described. Figure 3 As shown, the circuit substrate 1 of the third embodiment includes a fluororesin layer 10, an adhered layer 17, and an adhesive layer 12 that adheres the fluororesin layer 10 to the adhered layer 17. The fluororesin layer 10 includes a first main surface 10a facing the adhesive layer 12, and a second main surface 10b opposite to the first main surface 10a. The adhered layer 17 includes a first resin layer 16 and a first metal layer 13 provided on at least a portion of the surface of the first resin layer 16. The first resin layer 16 and the first metal layer 13 may be in contact. A resin layer, a metal layer, an adhesive layer, or a laminate thereof may be arranged between the first resin layer 16 and the first metal layer 13 to adhere the first resin layer 16 to the first metal layer 13.

[0247] The circuit board 1 of the third embodiment includes a first resin layer 16 provided between the first metal layer 13 and the adhesive layer 12 . The fourth principal surface 16 b of the first resin layer 16 which is far from the first metal layer 13 is in contact with the first B surface 12 a of the adhesive layer 12 which is far from the fluororesin layer 10 .

[0248] The circuit board 1 further includes a second metal layer 11 provided on the second main surface 10b of the fluororesin layer 10. The fluororesin layer 10 and the second metal layer 11 may be in contact with each other. The fluororesin layer 10 and the second metal layer 11 may be bonded together by placing an adhesive film (not shown) between the fluororesin layer 10 and the second metal layer 11.

[0249] The circuit board 1 further includes a connection portion 14. The connection portion 14 is made of metal and electrically connects the first metal layer 13 and the second metal layer 11. The second metal layer 11, the fluororesin layer 10, the adhesive layer 12, and the first resin layer 16 include through holes that penetrate through them. The connection portion 14 is formed in the through hole. More specifically, the connection portion 14 is formed on the inner wall surface of the second metal layer 11, the inner wall surface of the fluororesin layer 10, the inner wall surface of the adhesive layer 12, and the inner wall surface of the first resin layer 16. The first metal layer 13 defines the bottom surface of the through hole, and the connection portion 14 is also formed on the bottom surface.

[0250] When the circuit substrate 1 is observed from a direction perpendicular to the second main surface 10b of the fluororesin layer 10, the second metal layer 11 is not formed in the region overlapping with the through hole. The second metal layer 11 has an opening connected to the through hole. When the circuit substrate 1 is observed from a direction perpendicular to the second main surface 10b of the fluororesin layer 10, the first metal layer 13 is formed in the region overlapping with the through hole. The first metal layer 13 is the bottom of the through hole that blocks the through hole. The through hole that penetrates the fluororesin layer 10 and the adhesive layer 12 extends to the first resin layer 16. The connecting portion 14 formed on the inner wall surface of the fluororesin layer 10 and the adhesive layer 12 also extends to the first resin layer 16.

[0251] exist Figure 3 In the embodiment, the cross-sectional area of ​​the through hole increases continuously from the first metal layer 13 toward the second metal layer 11 .

[0252] In the third embodiment, the fluororesin layer 10 , the adhesive layer 12 , the first metal layer 13 , the second metal layer 11 , the first resin layer 16 , and the connecting portion 14 can be respectively the same as those in the first embodiment.

[0253] According to the circuit board 1 of the third embodiment, even when a through hole is formed penetrating the fluororesin layer 10 and the adhesive layer 12, the occurrence of a notch in the fluororesin layer 10 near the interface between the fluororesin layer 10 and the adhesive layer 12 can be suppressed. Therefore, the reliability of the circuit board 1 of the third embodiment is improved.

[0254] <Manufacturing method>

[0255] The method for manufacturing the circuit board 1 according to the third embodiment includes:

[0256] A process for preparing a fluororesin laminate 20 (hereinafter also referred to as "1B process"), wherein the fluororesin laminate 20 comprises: a fluororesin layer 10 comprising a first principal surface 10a and a second principal surface 10b opposite to the first principal surface 10a; and a second metal layer 11 disposed on the second principal surface 10b (refer to Figure 4A );

[0257] A step of preparing a first resin laminate 22 (hereinafter, also referred to as "step 2B"), the first resin laminate 22 comprising: a first resin layer 16 including a third main surface 16a and a fourth main surface 16b opposite to the third main surface 16a; and a first metal layer 13 disposed on the third main surface 16a (refer to Figure 4A );

[0258] The step of preparing the adhesive layer 12 (hereinafter, also referred to as "step 3B") (see Figure 4A );

[0259] A step of laminating the fluororesin laminate 20, the adhesive layer 12, and the first resin laminate 22 in order so that the first main surface 10a is in contact with the adhesive layer 12, and softening the adhesive layer 12 by maintaining the adhesive layer 12 at a temperature of 180°C or less, thereby laminating the fluororesin laminate 20 and the first resin laminate 22 to obtain a first laminate 24 (hereinafter also referred to as "step 4B"). (See Figure 4B );

[0260] A step of removing at least a portion of the fluororesin layer 10 and at least a portion of the adhesive layer 12 to form a through hole penetrating the fluororesin layer 10 and the adhesive layer 12 (hereinafter also referred to as “step 5B”) (see Figure 4C );as well as

[0261] A step of forming the connection portion 14 on the inner wall surface of the fluororesin laminate 20 and the adhesive layer 12 to obtain the circuit board 1 (hereinafter also referred to as the "sixth step"). (See Figure 3 ),

[0262] The fluororesin layer 10 includes polytetrafluoroethylene and a first inorganic filler.

[0263] The content of the first inorganic filler in the fluororesin layer 10 is 50% by volume or more and 66% by volume or less.

[0264] The adhesive layer 12 contains a resin and a second inorganic filler.

[0265] The fluororesin content of the resin is 5% by mass or less,

[0266] The content of the second inorganic filler in the adhesive layer 12 is 29% by volume or more and 47% by volume or less.

[0267] The 1B step, the 2B step, and the 3B step of the third embodiment can be respectively the same as the first step, the second step, and the third step of the second embodiment.

[0268] The step 4B of the third embodiment can be the same as the fourth step of the second embodiment except that the first resin layer 16 and the adhesive layer 12 are laminated so as to be in contact with each other.

[0269] In step 5B of the third embodiment, at least a portion of the second metal layer 11 , at least a portion of the fluororesin layer 10 , at least a portion of the adhesive layer 12 , and at least a portion of the first resin layer 16 are removed to form a through hole penetrating these layers.

[0270] The method for forming the through hole can be the same as the method for forming the through hole in the fifth step of the second embodiment. Figure 4C In the embodiment, the through hole does not penetrate the first metal layer 13 but is a blind hole.

[0271] After the through-holes are formed, the inner wall surfaces of the fluororesin layer 10 , the adhesive layer 12 , and the first resin layer may be subjected to a pretreatment step. The pretreatment step may be the same as the pretreatment step of the second embodiment.

[0272] In step 6B of the third embodiment, the connection portion 14 is formed on the end surface of the second metal layer 11 defining a portion of the through hole, the area near the opening (through hole) of the outer side surface of the second metal layer 11, the inner wall surface of the fluororesin layer 10, the inner wall surface of the adhesive layer 12, the inner wall surface of the first resin layer 16, and the surface near the adhesive layer of the first metal layer 13 defining a portion of the through hole, thereby obtaining the circuit board 1. The connection portion 14 can be formed by using the electroless plating and the electrolytic plating in the second embodiment.

[0273] [Embodiment 4: Circuit Board (3)]

[0274] use Figure 5 A circuit substrate and a manufacturing method thereof according to an embodiment of the present disclosure (hereinafter also referred to as "embodiment 4") are described. The circuit substrate 1 of embodiment 4 is basically the same as the circuit substrate of embodiment 1. The difference from the circuit substrate of embodiment 1 is that it has a filling portion 26 and a third metal layer 15. The filling portion 26 is filled in the through hole formed in the fluororesin layer 10 and the adhesive layer 12, and is in contact with the connecting portion 14. The third metal layer 15 is provided on the first main surface 10a of the fluororesin layer 10 and is buried in the adhesive layer 12.

[0275] The filling portion 26 may also contain resin. Thus, since stress applied to the connection portion, such as stress caused by thermal expansion and contraction of the circuit substrate and external vibration, can be relieved, the electrical connection reliability of the connection portion can be improved. The filling portion 26 containing resin can be easily formed by, for example, screen printing a paste-like material.

[0276] The filling portion 26 may be formed by filling the through hole with metal by a plating method. Thus, since the stress applied to the connection portion, such as the stress caused by thermal expansion and contraction of the circuit board and external vibration, can be relieved, the electrical connection reliability of the connection portion can be improved. Since the filling by the plating method can be easily performed using the connection portion 14, the filling portion 26 can be efficiently manufactured.

[0277] The third metal layer 15 forms a circuit. The third metal layer 15 can have the same structure as the first metal layer 13 .

[0278] The method for manufacturing a circuit board according to Embodiment 4 is basically the same as the method for manufacturing a circuit board according to Embodiment 2. The differences from the method for manufacturing a circuit board according to Embodiment 2 will be described below.

[0279] In embodiment 4, in the first step of embodiment 2, a fluororesin laminate 20 is prepared, which includes: a fluororesin layer 10, including a first main surface 10a and a second main surface 10b opposite to the first main surface 10a; a second metal layer 11, arranged on the second main surface 10b; and a third metal layer 15, arranged on the first main surface 10a, and a circuit is formed on the second main surface 10b and the first main surface 10a by etching at least a portion of the second metal layer 11 and at least a portion of the third metal layer 15.

[0280] In the fourth embodiment, after the sixth step of the second embodiment, a step is performed to fill the through holes of the fluororesin layer 10 and the adhesive layer 12 with resin to form a filled portion 26 in contact with the connecting portion 14. Thus, the circuit board 1 of the fourth embodiment can be obtained.

[0281] [Embodiment 5: Circuit Board (4)]

[0282] use Figure 6 , Fig. 7A and Figure 7B A circuit substrate and a manufacturing method thereof according to an embodiment of the present disclosure (hereinafter also referred to as "embodiment 5") are described. The circuit substrate 1 of embodiment 5 includes a fluororesin layer 10, an adhered layer 17, and an adhesive layer 12 that adheres the fluororesin layer 10 to the adhered layer 17. The fluororesin layer 10 includes a first main surface 10a facing the adhesive layer 12, and a second main surface 10b opposite to the first main surface 10a. The adhered layer 17 is composed of a first metal layer 13 and a first resin layer 16.

[0283] The fourth main surface 16 b of the first resin layer 16 is in contact with the first B surface 12 a of the adhesive layer 12 which is farther from the fluororesin layer 10 .

[0284] The circuit board 1 further includes a second metal layer 11 provided on the second main surface 10b of the fluororesin layer 10. The fluororesin layer 10 and the second metal layer 11 may be in contact with each other. The fluororesin layer 10 and the second metal layer 11 may be bonded together by placing an adhesive film (not shown) between the fluororesin layer 10 and the second metal layer 11.

[0285] The circuit substrate 1 further includes a connection portion 14. The connection portion 14 is made of metal and electrically connects the first metal layer 13 and the second metal layer 11. A through hole is formed on the circuit substrate 1, which passes through the first resin layer 16, the fluororesin layer 10, and the adhesive layer 12. That is, the first resin layer 16, the fluororesin layer 10, and the adhesive layer 12 have a through hole that passes through them. The connection portion 14 is formed in the through hole. More specifically, the connection portion 14 is formed near the through hole on the inner wall surface of the fluororesin layer 10, the inner wall surface of the adhesive layer 12, the inner wall surface of the first resin layer 16, and the end surface and outer side surface of the first metal layer. The second metal layer 11 defines the bottom surface of the through hole, and the connection portion 14 is also formed on the bottom surface.

[0286] When the circuit substrate 1 is observed from a direction perpendicular to the first main surface 10a, the first metal layer 13 is not formed in the region overlapping with the through hole. The first metal layer 13 has an opening connected to the through hole. When the circuit substrate 1 is observed from a direction perpendicular to the first main surface 10a, the second metal layer 11 is formed in the region overlapping with the through hole. The second metal layer 11 is a hole bottom that blocks the through hole.

[0287] The cross-sectional area of ​​the through hole decreases continuously from the first metal layer 13 toward the second metal layer 11 .

[0288] The method for manufacturing a circuit board according to Embodiment 5 is basically the same as the method for manufacturing a circuit board according to Embodiment 2. The differences from the method for manufacturing a circuit board according to Embodiment 2 will be described below.

[0289] The first stacked body 24 is obtained in the same manner as the first to fourth steps of the second embodiment (see Fig. 7A In Embodiment 5, in the fifth step of Embodiment 2, an opening is formed in the first metal layer 13. The area other than the opening of the first metal layer 13 is used as a mask, and laser processing is performed on the first resin layer 16, the adhesive layer 12, and the fluororesin layer 10 through the opening. Thus, at least a portion of the first resin layer 16, at least a portion of the adhesive layer 12, and at least a portion of the fluororesin layer 10 are removed, and a through hole is formed that penetrates the first resin layer 16, the adhesive layer 12, and the fluororesin layer 10 from the opening (see Figure 7B ) That is, the first resin layer 16, the fluororesin layer 10, and the adhesive layer 12 have through holes penetrating therethrough.

[0290] In the fifth embodiment, in the sixth step of the second embodiment, first, an electroless plating layer is formed by electroless plating on the end surface of the first metal layer 13 defining a portion of the through hole and the area near the opening (through hole) of the outer side surface of the first metal layer 13, the inner wall surface of the fluororesin layer 10 and the adhesive layer 12, and the surface near the adhesive layer of the second metal layer 11 defining a portion of the through hole. Next, a plating layer is formed on the electroless plating layer by electrolytic plating (see Figure 6 ). The plating layer is the connecting portion 14.

[0291] In Embodiment 5, in laser processing, the layer in contact with the second metal layer 11 as the bottom of the blind hole (the layer receiving more reflected energy from the second metal layer 11) is the fluororesin layer 10 having excellent heat resistance. Therefore, the length of the notch is reduced.

[0292] Example

[0293] The embodiments are further described in detail by examples, but the embodiments are not limited to these examples.

[0294] [Preparation of Test Laminated Body]

[0295] <Sample 1 to Sample 16>

[0296] like Figure 2A As shown, a fluororesin laminate 20 including a fluororesin layer 10 and a second metal layer 11 provided on one main surface of the fluororesin layer is prepared.

[0297] The fluororesin laminate 20 is produced according to the following steps. The raw materials shown in the "Fluororesin Layer" column of the "Raw Materials" in Tables 1 and 2 are mixed in the mass ratios described in Tables 1 and 2 to obtain a mixture. For example, in Sample 6, polytetrafluoroethylene powder (represented as "PTFE" in Tables 1 and 2), silica and titanium oxide are mixed in a mass ratio of 100:190:10. Next, 17 mass% of naphtha is mixed relative to the total mass of the polytetrafluoroethylene powder, silica and titanium oxide. After forming it into a sheet, it is dried in a constant temperature bath to remove the naphtha to obtain a fluororesin sheet (equivalent to the fluororesin layer 10) with an average thickness of 130 μm. Next, a perfluoroalkoxyalkane layer with an average thickness of 2 μm is formed on one side of a copper foil (equivalent to the second metal layer) with an average thickness of 18 μm. The copper foil is laminated with the fluororesin sheet so that the perfluoroalkoxyalkane layer is in contact with the fluororesin sheet. The laminate was heated at 350° C. for 40 minutes while being compressed at a pressure of 4 MPa, thereby obtaining a fluororesin laminate 20 .

[0298] exist Figure 2AIn the embodiment, the first resin laminate 22 is composed of the first metal layer 13 and the first resin layer 16, but in the laminate for this test, it is composed only of the first metal layer 13. The first metal layer 13 is composed of a copper foil having an average thickness of 18 μm.

[0299] Except for sample 16, the adhesive layer 12 is prepared according to the following steps. The raw materials shown in the "Adhesive Layer" column of the "Raw Materials" in Tables 1 and 2 are mixed in the mass ratios described in Tables 1 and 2 to obtain a mixture. For example, in sample 1, acid-modified polypropylene and epoxy resin are dissolved in a solvent at a mass ratio of 90:10. The solution is mixed with silica so that the ratio of acid-modified polypropylene, epoxy resin and silica is a mass ratio of 90:10:100. The solvent is a mixed solvent of methyl ethyl ketone, toluene, ethyl acetate and cyclohexane in an appropriate ratio that can dissolve acid-modified polypropylene and epoxy resin. A mixture sheet is formed by a scraper method, dried and the solvent is removed to obtain a bonding sheet (equivalent to the adhesive layer 12) with an average thickness of 30 μm. If a scraper method is used, the thickness of the mixture sheet can be adjusted. In Tables 1 and 2, "SEEPS" represents styrene-ethylene-ethylene-propylene-styrene block copolymer, and "PPE" represents polyphenylene ether. In sample 16, polytetrafluoroethylene powder, perfluoroalkoxyalkane powder (referred to as "PFA" in Tables 1 and 2) and silica were mixed at a mass ratio of 90:10:80. Next, 17% by mass of naphtha was mixed with respect to the total mass of polytetrafluoroethylene powder, perfluoroalkoxyalkane powder and silica. After being formed into a sheet, it was dried in a thermostatic chamber to remove the naphtha, and a bonding sheet (equivalent to the adhesive layer 12) with an average thickness of 30 μm was obtained.

[0300] The first metal layer 13, the adhesive layer 12 and the fluororesin laminate 20 are stacked in sequence so that the fluororesin layer 10 and the first metal layer 13 are in contact with the adhesive layer 12. The laminate is maintained at a temperature of 170°C for 30 minutes, while applying a pressure of 3 MPa. Thus, in samples 1 to 15, the first metal layer 13 is bonded to the fluororesin laminate 20 by softening the adhesive layer 12, and a test laminate can be obtained. In the case where a test laminate can be obtained, "Yes" is displayed in the "Possibility of stacking" column of Tables 1 and 2. In sample 16, the first metal layer 13 cannot be bonded to the fluororesin laminate 20. In the case where a test laminate cannot be obtained, "No" is displayed in the "Possibility of stacking" column of Tables 1 and 2.

[0301] [Table 1]

[0302] [Table 1]

[0303]

[0304] [Table 2]

[0305] [Table 2]

[0306]

[0307] <Measurement of Thermal Expansion Coefficient of Fluororesin Layer>

[0308] The thermal expansion coefficient of the fluororesin layer of each sample before lamination was measured. The thermal expansion coefficient of the fluororesin layer in the thickness direction was measured in the range of 20°C to 120°C using a thermal dilatometer (LIX-2) manufactured by Advance Riko Co., Ltd. As described above, in the present disclosure, the linear expansion coefficient of the fluororesin layer in the thickness direction is the thermal expansion coefficient of the fluororesin layer. The results are shown in the "Thermal Expansion Coefficient" column of "Fluororesin Layer" in Tables 1 and 2. In the "Evaluation" column of "Thermal Expansion Coefficient", the case where the thermal expansion coefficient is less than 40ppm / °C is represented as A, the case where the thermal expansion coefficient is greater than 40ppm / °C and less than 90ppm / °C is represented as B, and the case where the thermal expansion coefficient is greater than 90ppm / °C is represented as C. In the case where the evaluation is A or B, the thermal expansion coefficient of the fluororesin layer is judged to be small. In the case where the evaluation is C, the thermal expansion coefficient of the fluororesin layer is judged to be large.

[0309] <Composition of Fluororesin Layer and Adhesive Layer>

[0310] The volume-based content (volume %) and mass-based content (mass %) of the first inorganic filler in the fluororesin layer of each sample are shown in the "volume %" and "mass %" columns of the "content of the first inorganic filler" of the "fluororesin layer" in Tables 1 and 2. Among the raw materials described in Tables 1 and 2, silicon dioxide and titanium oxide correspond to the first inorganic filler. When the sample contains both silicon dioxide and titanium oxide, the content is calculated based on their total.

[0311] The volume-based content (volume %) and mass-based content (mass %) of the second inorganic filler in the adhesive layer of each sample are shown in the "volume %" and "mass %" columns of the "content of the second inorganic filler" of the "adhesive layer" in Tables 1 and 2. Among the materials described in Tables 1 and 2, silicon dioxide and boron nitride are equivalent to the first inorganic filler. When the sample contains both silicon dioxide and boron nitride, the content is calculated based on their total.

[0312] Based on the mass-based content X (mass %) of the first inorganic filler in the fluororesin layer and the content Y (mass %) of the second inorganic filler in the adhesive layer, the absolute value Z of the difference between X and Y was calculated. The results are shown in the "Z" column of Tables 1 and 2.

[0313] <Evaluation of Adhesive Layer>

[0314] The glass transition temperature of the adhesive layer of each sample was measured. In addition, the elastic modulus B at 20°C and the elastic modulus A at 160°C of the adhesive layer of each sample were measured, and the ratio A / B was calculated. The specific measurement method is described in Implementation Example 1. The results are shown in the "Glass Transition Temperature" and "A / B" columns of "Adhesive Layer" in Tables 1 and 2.

[0315] <Evaluation of Peel Strength>

[0316] The evaluation of peel strength is implemented based on JIS-K6854-2 (1999). Specifically, the evaluation is performed by a 180° peel test. A polyimide tape ("P221" manufactured by Nitto Denko Corporation) with a thickness of 66 μm is pasted on the first metal layer of the test laminate of each sample. The thickness of the substrate of the polyimide tape is 25 μm. The interface between the fluororesin layer and the adhesive layer is used as the peeling starting point. The polyimide tape, the first metal layer and the adhesive layer are stretched at 50 mm / min so that the peeling direction is 180° relative to the bonding surface to measure the strength during peeling. The results are shown in the "Peel Strength" column of Tables 1 and 2.

[0317] <Measurement of Notch Length>

[0318] In the laminate of each sample, a through hole was formed from the second metal layer, and the length of the notch in the fluororesin layer near the interface between the fluororesin layer and the adhesive layer was measured. The through hole was formed as follows.

[0319] A dry film is attached to the second metal layer and exposed to light, and the second metal layer is etched. Thereafter, the dry film is peeled off to form an opening of φ125 μm in the second metal layer.

[0320] The opening was irradiated with CO2 laser to form a through hole. The output power of the CO2 laser was set to 18.5 W. Thus, the fluororesin layer and the adhesive layer were removed, and the first metal layer was exposed with a size of φ110 μm. The through hole was a blind hole.

[0321] The laminate is cut to expose a cross section including the central axis of the blind hole, and in the cross section, the length of the notch of the fluororesin layer near the interface between the fluororesin layer and the adhesive layer is measured. The method for measuring the length of the notch is described in Implementation 1. The results are shown in the "Length of the Notch" column of Tables 1 and 2. In the "Evaluation" column of the length of the notch, the case where the length of the notch is less than 15 μm is represented as A, the case where the length of the notch is greater than 15 μm and less than 25 μm is represented as B, and the case where the length of the notch is greater than 25 μm is represented as C. In the case of the evaluation of A or B, it is judged that the generation of the notch is suppressed. In the case of the evaluation of C, it is judged that the generation of the notch is not suppressed.

[0322] <Inspection>

[0323] Samples 3 to 5, 7 to 10, 12, 14, and 15 are examples. In these samples, the fluororesin layer and the adhered layer are bonded to each other by the adhesive layer by stamping at low temperature. In these samples, it was confirmed that even when a through hole penetrating the fluororesin layer and the adhesive layer is formed, the generation of a notch near the interface between the fluororesin layer and the adhesive layer can be suppressed.

[0324] Samples 1, 2, 6, 11, and 13 are comparative examples. In these samples, it was confirmed that the occurrence of notches was not suppressed when through holes penetrating the fluororesin layer and the adhesive layer were formed.

[0325] In sample 16, the fluororesin layer and the bonded layer could not be bonded by stamping at low temperature. It can be inferred that the reason is that the content of the fluororesin (PTFE, PFA) in the resin of the bonding layer is 100% by mass, and the bonding layer 12 does not soften during the stamping process. In sample 16, since a test laminate was not obtained, the laminate could not be laser processed. Therefore, the length of the notch of sample 16 could not be measured.

[0326] It is intended from the outset that the configurations of the above-described embodiments and examples may be appropriately combined and variously modified.

[0327] The embodiments and examples disclosed this time should be considered as illustrative in all aspects and not restrictive. The scope of the present invention is indicated by the claims rather than the embodiments and examples described above, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0328] Description of Reference Numerals

[0329] 1 Circuit board

[0330] 10 Fluororesin layer

[0331] 10a First main surface

[0332] 10b Second main surface

[0333] 11. Second Metal Layer

[0334] 12 Adhesive layer

[0335] 12a Side 1B

[0336] 13. First Metal Layer

[0337] 13a Page 1A

[0338] 14 Connection

[0339] 15 Third Metal Layer

[0340] 16 First resin layer

[0341] 16a Third main surface

[0342] 16b Fourth main surface

[0343] 17 Adhesive layer

[0344] 20 Fluororesin laminate

[0345] 22. First resin laminate

[0346] 24 first stack

[0347] 25 Notch

[0348] 26 Filling

[0349] 27 inner wall

[0350] L1 Center axis

[0351] P1 interface.

Claims

1. A circuit substrate comprising: Fluororesin layer; a bonded layer; and an adhesive layer for bonding the fluororesin layer to the adhered layer, The fluororesin layer comprises polytetrafluoroethylene and a first inorganic filler, The content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less, The adhesive layer comprises a resin and a second inorganic filler, The fluororesin content of the resin is 5% by mass or less, The content of the second inorganic filler in the adhesive layer is 29 volume % or more and 47 volume % or less, A through hole is formed which penetrates the fluororesin layer and the adhesive layer.

2. The circuit substrate according to claim 1, The first inorganic filler comprises silicon dioxide.

3. The circuit substrate according to claim 1 or 2, The second inorganic filler includes silicon dioxide.

4. The circuit substrate according to any one of claims 1 to 3, The second inorganic filler includes boron nitride.

5. The circuit substrate according to any one of claims 1 to 4, At least one of an inner wall surface of the fluororesin layer defining a portion of the through hole and an inner wall surface of the adhesive layer defining a portion of the through hole has a notch, and a length of the notch is less than 25 μm.

6. The circuit substrate according to any one of claims 1 to 5, A ratio A / B of the elastic modulus A of the adhesive layer at 160° C. to the elastic modulus B at 20° C. is 0.08 or less.

7. The circuit substrate according to any one of claims 1 to 6, The resin includes a polyolefin or a polystyrene-based elastomer.

8. The circuit substrate according to any one of claims 1 to 7, The bonded layer includes a first metal layer and a first resin layer. The first metal layer is provided on a surface of the first resin layer that faces the fluororesin layer.

9. The circuit substrate according to any one of claims 1 to 7, The bonded layer includes a first metal layer and a first resin layer. The first resin layer is provided on a surface of the first metal layer that faces the fluororesin layer.

10. The circuit substrate according to claim 8 or 9, The fluororesin layer includes a first main surface facing the adhesive layer and a second main surface opposite to the first main surface. The circuit board further includes a second metal layer provided on the second main surface.

11. The circuit substrate according to claim 10, The circuit substrate further includes a connection portion that electrically connects the first metal layer and the second metal layer. The connection portion is formed in the through hole.

12. The circuit substrate according to claim 10 or 11, The first metal layer is formed in a region overlapping with the through hole when viewed in a direction perpendicular to the second main surface.

13. The circuit substrate according to claim 10 or 11, The second metal layer is formed in a region overlapping with the through hole when viewed from a direction perpendicular to the first main surface.

14. A method for manufacturing a circuit substrate, which is a method for manufacturing the circuit substrate according to any one of claims 1 to 13, The method further comprises the step of bonding the fluororesin layer to the adhered layer by holding a laminated body in which the fluororesin layer, the adhesive layer, and the adhered layer are laminated in this order at a temperature of 180° C. or lower to soften the adhesive layer.

15. A method for manufacturing a circuit substrate, comprising: A process for preparing a fluororesin laminate, the fluororesin laminate comprising: A fluororesin layer comprising a first main surface and a second main surface opposite to the first main surface; and a second metal layer, disposed on the second main surface; A step of preparing a first resin laminate, the first resin laminate comprising: a first resin layer including a third main surface and a fourth main surface opposite to the third main surface; and a first metal layer disposed on the third main surface; A process for preparing an adhesive layer; The step of laminating the fluororesin laminate, the adhesive layer, and the first resin laminate in this order so that the first main surface is in contact with the adhesive layer, and softening the adhesive layer by maintaining the adhesive layer at a temperature of 180° C. or less, thereby laminating the fluororesin laminate and the first resin laminate to form a first laminate; a step of removing at least a portion of the fluororesin layer and at least a portion of the adhesive layer to form a through hole penetrating the fluororesin layer and the adhesive layer; and forming a connecting portion between an inner wall surface of the fluororesin layer defining a portion of the through hole and an inner wall surface of the adhesive layer defining a portion of the through hole, The fluororesin layer comprises polytetrafluoroethylene and a first inorganic filler, The content of the first inorganic filler in the fluororesin layer is 50% by volume or more and 66% by volume or less, The adhesive layer comprises a resin and a second inorganic filler, The fluororesin content of the resin is 5% by mass or less, The content of the second inorganic filler in the adhesive layer is 29 volume % or more and 47 volume % or less.

16. The method for manufacturing a circuit substrate according to claim 15, The step of preparing the first resin laminate further includes the step of forming a first circuit on the first resin laminate by etching at least a portion of the first metal layer.

17. The method for manufacturing a circuit substrate according to claim 15 or 16, The step of preparing the fluororesin laminate further includes the step of forming a second circuit on the fluororesin laminate by etching at least a portion of the second metal layer.

18. The method for manufacturing a circuit substrate according to claim 15 or 16, The step of forming the first laminate further includes the step of forming a second circuit on the fluororesin laminate by etching at least a portion of the second metal layer.

19. The method for manufacturing a circuit substrate according to any one of claims 15 to 18, The through hole is formed by laser processing.

20. The method for manufacturing a circuit substrate according to any one of claims 15 to 19, At least one of the inner wall surface of the fluororesin layer and the inner wall surface of the adhesive layer has a notch, The length of the notch is less than 25 μm.

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